Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8817519 |
1 |
|
|
T24 |
257 |
|
T25 |
71796 |
|
T26 |
143 |
| auto[1] |
6724724 |
1 |
|
|
T25 |
66186 |
|
T26 |
158 |
|
T31 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14695835 |
1 |
|
|
T24 |
257 |
|
T25 |
129769 |
|
T26 |
296 |
| auto[1] |
846408 |
1 |
|
|
T25 |
8213 |
|
T26 |
5 |
|
T31 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8856379 |
1 |
|
|
T24 |
257 |
|
T25 |
71980 |
|
T26 |
155 |
| auto[1] |
6685864 |
1 |
|
|
T25 |
66002 |
|
T26 |
146 |
|
T31 |
61 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2897708 |
1 |
|
|
T25 |
29964 |
|
T26 |
72 |
|
T31 |
7 |
| auto[1] |
auto[0] |
auto[1] |
418968 |
1 |
|
|
T25 |
4326 |
|
T1 |
1075 |
|
T11 |
32 |
| auto[1] |
auto[1] |
auto[0] |
2941748 |
1 |
|
|
T25 |
27825 |
|
T26 |
69 |
|
T31 |
51 |
| auto[1] |
auto[1] |
auto[1] |
427440 |
1 |
|
|
T25 |
3887 |
|
T26 |
5 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |