Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8809543 |
1 |
|
|
T24 |
257 |
|
T25 |
71586 |
|
T26 |
142 |
| auto[1] |
6732700 |
1 |
|
|
T25 |
66396 |
|
T26 |
159 |
|
T31 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12854464 |
1 |
|
|
T24 |
257 |
|
T25 |
111773 |
|
T26 |
204 |
| auto[1] |
2687779 |
1 |
|
|
T25 |
26209 |
|
T26 |
97 |
|
T31 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8811507 |
1 |
|
|
T24 |
257 |
|
T25 |
67562 |
|
T26 |
126 |
| auto[1] |
6730736 |
1 |
|
|
T25 |
70420 |
|
T26 |
175 |
|
T31 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2011935 |
1 |
|
|
T25 |
24368 |
|
T26 |
42 |
|
T31 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1342988 |
1 |
|
|
T25 |
14164 |
|
T26 |
35 |
|
T31 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2031022 |
1 |
|
|
T25 |
19843 |
|
T26 |
36 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1344791 |
1 |
|
|
T25 |
12045 |
|
T26 |
62 |
|
T31 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |