Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8840346 |
1 |
|
|
T24 |
257 |
|
T25 |
72859 |
|
T26 |
150 |
| auto[1] |
6701897 |
1 |
|
|
T25 |
65123 |
|
T26 |
151 |
|
T31 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12873907 |
1 |
|
|
T24 |
257 |
|
T25 |
112128 |
|
T26 |
268 |
| auto[1] |
2668336 |
1 |
|
|
T25 |
25854 |
|
T26 |
33 |
|
T31 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8842933 |
1 |
|
|
T24 |
257 |
|
T25 |
67843 |
|
T26 |
204 |
| auto[1] |
6699310 |
1 |
|
|
T25 |
70139 |
|
T26 |
97 |
|
T31 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2011994 |
1 |
|
|
T25 |
23725 |
|
T26 |
38 |
|
T1 |
5165 |
| auto[1] |
auto[0] |
auto[1] |
1329212 |
1 |
|
|
T25 |
13850 |
|
T26 |
21 |
|
T31 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2018980 |
1 |
|
|
T25 |
20560 |
|
T26 |
26 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1339124 |
1 |
|
|
T25 |
12004 |
|
T26 |
12 |
|
T31 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |