Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8838619 |
1 |
|
|
T24 |
257 |
|
T25 |
69540 |
|
T26 |
172 |
| auto[1] |
6703624 |
1 |
|
|
T25 |
68442 |
|
T26 |
129 |
|
T31 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14693457 |
1 |
|
|
T24 |
257 |
|
T25 |
129902 |
|
T26 |
296 |
| auto[1] |
848786 |
1 |
|
|
T25 |
8080 |
|
T26 |
5 |
|
T1 |
2339 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8843317 |
1 |
|
|
T24 |
257 |
|
T25 |
72124 |
|
T26 |
197 |
| auto[1] |
6698926 |
1 |
|
|
T25 |
65858 |
|
T26 |
104 |
|
T31 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2926598 |
1 |
|
|
T25 |
30148 |
|
T26 |
66 |
|
T31 |
9 |
| auto[1] |
auto[0] |
auto[1] |
424563 |
1 |
|
|
T25 |
4230 |
|
T26 |
2 |
|
T1 |
1064 |
| auto[1] |
auto[1] |
auto[0] |
2923542 |
1 |
|
|
T25 |
27630 |
|
T26 |
33 |
|
T1 |
7484 |
| auto[1] |
auto[1] |
auto[1] |
424223 |
1 |
|
|
T25 |
3850 |
|
T26 |
3 |
|
T1 |
1275 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |