Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8826221 |
1 |
|
|
T24 |
257 |
|
T25 |
64781 |
|
T26 |
137 |
| auto[1] |
6716022 |
1 |
|
|
T25 |
73201 |
|
T26 |
164 |
|
T31 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14690454 |
1 |
|
|
T24 |
257 |
|
T25 |
129141 |
|
T26 |
294 |
| auto[1] |
851789 |
1 |
|
|
T25 |
8841 |
|
T26 |
7 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8830537 |
1 |
|
|
T24 |
257 |
|
T25 |
68348 |
|
T26 |
162 |
| auto[1] |
6711706 |
1 |
|
|
T25 |
69634 |
|
T26 |
139 |
|
T31 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2914179 |
1 |
|
|
T25 |
26586 |
|
T26 |
76 |
|
T31 |
16 |
| auto[1] |
auto[0] |
auto[1] |
423481 |
1 |
|
|
T25 |
3846 |
|
T26 |
3 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2945738 |
1 |
|
|
T25 |
34207 |
|
T26 |
56 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[1] |
428308 |
1 |
|
|
T25 |
4995 |
|
T26 |
4 |
|
T1 |
1114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |