Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8840603 |
1 |
|
|
T24 |
257 |
|
T25 |
69875 |
|
T26 |
193 |
| auto[1] |
6701640 |
1 |
|
|
T25 |
68107 |
|
T26 |
108 |
|
T31 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14696433 |
1 |
|
|
T24 |
257 |
|
T25 |
129159 |
|
T26 |
295 |
| auto[1] |
845810 |
1 |
|
|
T25 |
8823 |
|
T26 |
6 |
|
T21 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8874219 |
1 |
|
|
T24 |
257 |
|
T25 |
67321 |
|
T26 |
192 |
| auto[1] |
6668024 |
1 |
|
|
T25 |
70661 |
|
T26 |
109 |
|
T31 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2904314 |
1 |
|
|
T25 |
30221 |
|
T26 |
57 |
|
T31 |
12 |
| auto[1] |
auto[0] |
auto[1] |
422466 |
1 |
|
|
T25 |
4325 |
|
T26 |
4 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2917900 |
1 |
|
|
T25 |
31617 |
|
T26 |
46 |
|
T31 |
11 |
| auto[1] |
auto[1] |
auto[1] |
423344 |
1 |
|
|
T25 |
4498 |
|
T26 |
2 |
|
T1 |
995 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |