Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8847997 |
1 |
|
|
T24 |
257 |
|
T25 |
66565 |
|
T26 |
193 |
| auto[1] |
6694246 |
1 |
|
|
T25 |
71417 |
|
T26 |
108 |
|
T31 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14696703 |
1 |
|
|
T24 |
257 |
|
T25 |
129148 |
|
T26 |
291 |
| auto[1] |
845540 |
1 |
|
|
T25 |
8834 |
|
T26 |
10 |
|
T31 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8867355 |
1 |
|
|
T24 |
257 |
|
T25 |
68536 |
|
T26 |
168 |
| auto[1] |
6674888 |
1 |
|
|
T25 |
69446 |
|
T26 |
133 |
|
T31 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2912298 |
1 |
|
|
T25 |
30738 |
|
T26 |
81 |
|
T31 |
14 |
| auto[1] |
auto[0] |
auto[1] |
422743 |
1 |
|
|
T25 |
4568 |
|
T26 |
7 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2917050 |
1 |
|
|
T25 |
29874 |
|
T26 |
42 |
|
T31 |
24 |
| auto[1] |
auto[1] |
auto[1] |
422797 |
1 |
|
|
T25 |
4266 |
|
T26 |
3 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |