Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8847294 |
1 |
|
|
T24 |
257 |
|
T25 |
67526 |
|
T26 |
159 |
| auto[1] |
6694949 |
1 |
|
|
T25 |
70456 |
|
T26 |
142 |
|
T31 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14691433 |
1 |
|
|
T24 |
257 |
|
T25 |
128897 |
|
T26 |
294 |
| auto[1] |
850810 |
1 |
|
|
T25 |
9085 |
|
T26 |
7 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8844922 |
1 |
|
|
T24 |
257 |
|
T25 |
66062 |
|
T26 |
154 |
| auto[1] |
6697321 |
1 |
|
|
T25 |
71920 |
|
T26 |
147 |
|
T31 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2914014 |
1 |
|
|
T25 |
31065 |
|
T26 |
66 |
|
T31 |
36 |
| auto[1] |
auto[0] |
auto[1] |
423819 |
1 |
|
|
T25 |
4629 |
|
T26 |
3 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2932497 |
1 |
|
|
T25 |
31770 |
|
T26 |
74 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
426991 |
1 |
|
|
T25 |
4456 |
|
T26 |
4 |
|
T1 |
1072 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |