Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8834404 |
1 |
|
|
T24 |
257 |
|
T25 |
67541 |
|
T26 |
153 |
| auto[1] |
6707839 |
1 |
|
|
T25 |
70441 |
|
T26 |
148 |
|
T31 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14686361 |
1 |
|
|
T24 |
257 |
|
T25 |
129946 |
|
T26 |
292 |
| auto[1] |
855882 |
1 |
|
|
T25 |
8036 |
|
T26 |
9 |
|
T21 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8807657 |
1 |
|
|
T24 |
257 |
|
T25 |
72349 |
|
T26 |
144 |
| auto[1] |
6734586 |
1 |
|
|
T25 |
65633 |
|
T26 |
157 |
|
T31 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2930220 |
1 |
|
|
T25 |
29559 |
|
T26 |
81 |
|
T31 |
17 |
| auto[1] |
auto[0] |
auto[1] |
425191 |
1 |
|
|
T25 |
4246 |
|
T26 |
5 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2948484 |
1 |
|
|
T25 |
28038 |
|
T26 |
67 |
|
T1 |
7290 |
| auto[1] |
auto[1] |
auto[1] |
430691 |
1 |
|
|
T25 |
3790 |
|
T26 |
4 |
|
T1 |
1145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |