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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 948
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T768 /workspace/coverage/cover_reg_top/35.gpio_intr_test.382947544 Aug 03 04:21:44 PM PDT 24 Aug 03 04:21:44 PM PDT 24 49055733 ps
T46 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.928849562 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:34 PM PDT 24 188648096 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.5293393 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:52 PM PDT 24 15215437 ps
T47 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2387901910 Aug 03 04:20:00 PM PDT 24 Aug 03 04:20:01 PM PDT 24 389658187 ps
T770 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1512195697 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:42 PM PDT 24 119258163 ps
T771 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2315650442 Aug 03 04:20:09 PM PDT 24 Aug 03 04:20:09 PM PDT 24 20143894 ps
T772 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3329221449 Aug 03 04:22:16 PM PDT 24 Aug 03 04:22:17 PM PDT 24 31119804 ps
T104 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3365141021 Aug 03 04:21:05 PM PDT 24 Aug 03 04:21:06 PM PDT 24 21772216 ps
T773 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.560303787 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:17 PM PDT 24 59399035 ps
T84 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2300298869 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 44613827 ps
T774 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3503105084 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:16 PM PDT 24 195907715 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2465547831 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:49 PM PDT 24 61440376 ps
T776 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.340514025 Aug 03 04:21:38 PM PDT 24 Aug 03 04:21:38 PM PDT 24 18579967 ps
T777 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3037866836 Aug 03 04:21:20 PM PDT 24 Aug 03 04:21:21 PM PDT 24 23533204 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1391069632 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:09 PM PDT 24 150413993 ps
T779 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4172173675 Aug 03 04:23:58 PM PDT 24 Aug 03 04:23:59 PM PDT 24 16884462 ps
T105 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2430229099 Aug 03 04:21:58 PM PDT 24 Aug 03 04:21:59 PM PDT 24 30557670 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2692905231 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:03 PM PDT 24 134023734 ps
T781 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3020762713 Aug 03 04:20:33 PM PDT 24 Aug 03 04:20:35 PM PDT 24 71060115 ps
T782 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.372539499 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:52 PM PDT 24 198521562 ps
T783 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2434411835 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:57 PM PDT 24 18287605 ps
T51 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4148301833 Aug 03 04:21:58 PM PDT 24 Aug 03 04:22:00 PM PDT 24 276062773 ps
T53 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.501839822 Aug 03 04:24:14 PM PDT 24 Aug 03 04:24:15 PM PDT 24 1970602684 ps
T48 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4251127855 Aug 03 04:23:21 PM PDT 24 Aug 03 04:23:22 PM PDT 24 137436301 ps
T784 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3357689388 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:16 PM PDT 24 67351586 ps
T85 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.80245946 Aug 03 04:20:11 PM PDT 24 Aug 03 04:20:12 PM PDT 24 25711307 ps
T49 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3120516730 Aug 03 04:21:54 PM PDT 24 Aug 03 04:21:55 PM PDT 24 107261769 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.203876337 Aug 03 04:22:16 PM PDT 24 Aug 03 04:22:19 PM PDT 24 136025545 ps
T50 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1551055091 Aug 03 04:20:12 PM PDT 24 Aug 03 04:20:14 PM PDT 24 124874876 ps
T786 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3605642639 Aug 03 04:23:20 PM PDT 24 Aug 03 04:23:21 PM PDT 24 33366923 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.538862623 Aug 03 04:20:33 PM PDT 24 Aug 03 04:20:34 PM PDT 24 13483848 ps
T788 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3919516307 Aug 03 04:21:59 PM PDT 24 Aug 03 04:21:59 PM PDT 24 16871491 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.905757670 Aug 03 04:20:54 PM PDT 24 Aug 03 04:20:55 PM PDT 24 14107804 ps
T789 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1393751226 Aug 03 04:23:22 PM PDT 24 Aug 03 04:23:23 PM PDT 24 21181800 ps
T790 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1816694038 Aug 03 04:21:14 PM PDT 24 Aug 03 04:21:15 PM PDT 24 23163735 ps
T791 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1150283597 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:04 PM PDT 24 431934654 ps
T792 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2549339326 Aug 03 04:20:48 PM PDT 24 Aug 03 04:20:50 PM PDT 24 392845905 ps
T793 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2157806961 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:09 PM PDT 24 18513229 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3774260240 Aug 03 04:21:38 PM PDT 24 Aug 03 04:21:38 PM PDT 24 16648917 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2880247783 Aug 03 04:21:17 PM PDT 24 Aug 03 04:21:19 PM PDT 24 109135468 ps
T796 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4202368155 Aug 03 04:21:04 PM PDT 24 Aug 03 04:21:05 PM PDT 24 174484982 ps
T797 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1466376803 Aug 03 04:21:31 PM PDT 24 Aug 03 04:21:32 PM PDT 24 19929590 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3909010205 Aug 03 04:22:09 PM PDT 24 Aug 03 04:22:11 PM PDT 24 210878151 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2865489761 Aug 03 04:19:06 PM PDT 24 Aug 03 04:19:07 PM PDT 24 29851787 ps
T800 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2355355094 Aug 03 04:21:42 PM PDT 24 Aug 03 04:21:42 PM PDT 24 16160477 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2331464548 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:52 PM PDT 24 20656851 ps
T802 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1692114811 Aug 03 04:23:57 PM PDT 24 Aug 03 04:23:58 PM PDT 24 78976110 ps
T803 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1607954599 Aug 03 04:21:24 PM PDT 24 Aug 03 04:21:24 PM PDT 24 50922276 ps
T804 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2670966066 Aug 03 04:21:58 PM PDT 24 Aug 03 04:21:59 PM PDT 24 16579784 ps
T805 /workspace/coverage/cover_reg_top/16.gpio_intr_test.801778143 Aug 03 04:21:56 PM PDT 24 Aug 03 04:21:57 PM PDT 24 62389893 ps
T806 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1241873233 Aug 03 04:20:38 PM PDT 24 Aug 03 04:20:39 PM PDT 24 21706968 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.89369977 Aug 03 04:20:25 PM PDT 24 Aug 03 04:20:27 PM PDT 24 273990331 ps
T87 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2117616631 Aug 03 04:20:53 PM PDT 24 Aug 03 04:20:54 PM PDT 24 46581540 ps
T808 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.728952099 Aug 03 04:19:59 PM PDT 24 Aug 03 04:20:00 PM PDT 24 155402233 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1472592062 Aug 03 04:20:12 PM PDT 24 Aug 03 04:20:13 PM PDT 24 31188982 ps
T810 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3475065500 Aug 03 04:20:15 PM PDT 24 Aug 03 04:20:15 PM PDT 24 26551803 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3838540585 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:02 PM PDT 24 42478806 ps
T812 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1468944766 Aug 03 04:20:19 PM PDT 24 Aug 03 04:20:20 PM PDT 24 97984069 ps
T813 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1631651381 Aug 03 04:23:29 PM PDT 24 Aug 03 04:23:30 PM PDT 24 25967430 ps
T114 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1072438480 Aug 03 04:24:29 PM PDT 24 Aug 03 04:24:30 PM PDT 24 700938120 ps
T814 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.978199393 Aug 03 04:21:25 PM PDT 24 Aug 03 04:21:27 PM PDT 24 109324961 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3018630269 Aug 03 04:22:00 PM PDT 24 Aug 03 04:22:03 PM PDT 24 262502631 ps
T816 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2599373844 Aug 03 04:21:31 PM PDT 24 Aug 03 04:21:32 PM PDT 24 262225337 ps
T817 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1200252263 Aug 03 04:22:04 PM PDT 24 Aug 03 04:22:05 PM PDT 24 42882122 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.75446622 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:42 PM PDT 24 30139084 ps
T819 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4091893344 Aug 03 04:22:38 PM PDT 24 Aug 03 04:22:38 PM PDT 24 11789620 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2334435825 Aug 03 04:22:55 PM PDT 24 Aug 03 04:22:56 PM PDT 24 189189537 ps
T821 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2817081408 Aug 03 04:22:45 PM PDT 24 Aug 03 04:22:45 PM PDT 24 11906138 ps
T822 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3123380914 Aug 03 04:21:48 PM PDT 24 Aug 03 04:21:49 PM PDT 24 43840235 ps
T823 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2568325828 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:33 PM PDT 24 84804908 ps
T824 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.50741721 Aug 03 04:20:10 PM PDT 24 Aug 03 04:20:13 PM PDT 24 694157708 ps
T825 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.232890412 Aug 03 04:20:50 PM PDT 24 Aug 03 04:20:51 PM PDT 24 162566735 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.608185574 Aug 03 04:21:37 PM PDT 24 Aug 03 04:21:38 PM PDT 24 93818429 ps
T827 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.411444740 Aug 03 04:21:05 PM PDT 24 Aug 03 04:21:06 PM PDT 24 18806079 ps
T828 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3752525217 Aug 03 04:21:34 PM PDT 24 Aug 03 04:21:35 PM PDT 24 42291826 ps
T829 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2036373721 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:35 PM PDT 24 131872567 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4192113589 Aug 03 04:20:14 PM PDT 24 Aug 03 04:20:15 PM PDT 24 41998131 ps
T831 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1122344474 Aug 03 04:21:25 PM PDT 24 Aug 03 04:21:26 PM PDT 24 247729220 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3181554843 Aug 03 04:21:24 PM PDT 24 Aug 03 04:21:24 PM PDT 24 15409660 ps
T832 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1959020715 Aug 03 04:23:22 PM PDT 24 Aug 03 04:23:23 PM PDT 24 14305632 ps
T833 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4095591359 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 31134486 ps
T89 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2565460328 Aug 03 04:20:48 PM PDT 24 Aug 03 04:20:48 PM PDT 24 53201844 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2459380293 Aug 03 04:20:31 PM PDT 24 Aug 03 04:20:32 PM PDT 24 110257660 ps
T835 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2696156669 Aug 03 04:21:56 PM PDT 24 Aug 03 04:21:57 PM PDT 24 13819258 ps
T836 /workspace/coverage/cover_reg_top/5.gpio_intr_test.90009797 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:52 PM PDT 24 107581843 ps
T837 /workspace/coverage/cover_reg_top/12.gpio_intr_test.4099983873 Aug 03 04:23:20 PM PDT 24 Aug 03 04:23:21 PM PDT 24 15040088 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3094458992 Aug 03 04:21:53 PM PDT 24 Aug 03 04:21:55 PM PDT 24 119332271 ps
T90 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.274989469 Aug 03 04:21:14 PM PDT 24 Aug 03 04:21:15 PM PDT 24 20674337 ps
T839 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.383644658 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 32575362 ps
T840 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3465887241 Aug 03 04:21:06 PM PDT 24 Aug 03 04:21:07 PM PDT 24 33799890 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1687279271 Aug 03 04:21:05 PM PDT 24 Aug 03 04:21:06 PM PDT 24 15204781 ps
T842 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2727626795 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:06 PM PDT 24 1072751971 ps
T843 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3950100542 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:47 PM PDT 24 84487780 ps
T844 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4198888213 Aug 03 04:20:39 PM PDT 24 Aug 03 04:20:40 PM PDT 24 35599636 ps
T845 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.217898620 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:57 PM PDT 24 267621041 ps
T846 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2473096059 Aug 03 04:19:19 PM PDT 24 Aug 03 04:19:20 PM PDT 24 40042428 ps
T847 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2071873136 Aug 03 04:19:52 PM PDT 24 Aug 03 04:19:54 PM PDT 24 399019179 ps
T848 /workspace/coverage/cover_reg_top/20.gpio_intr_test.213864701 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:15 PM PDT 24 14778179 ps
T849 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1555714175 Aug 03 04:20:29 PM PDT 24 Aug 03 04:20:30 PM PDT 24 51194585 ps
T850 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3705377679 Aug 03 04:21:49 PM PDT 24 Aug 03 04:21:51 PM PDT 24 219586750 ps
T851 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4185818000 Aug 03 04:20:45 PM PDT 24 Aug 03 04:20:47 PM PDT 24 84268378 ps
T852 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2951574545 Aug 03 04:20:44 PM PDT 24 Aug 03 04:20:45 PM PDT 24 49214249 ps
T853 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193953962 Aug 03 04:19:32 PM PDT 24 Aug 03 04:19:33 PM PDT 24 69875506 ps
T854 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.258950691 Aug 03 04:20:44 PM PDT 24 Aug 03 04:20:46 PM PDT 24 77198200 ps
T855 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1252861415 Aug 03 04:21:21 PM PDT 24 Aug 03 04:21:24 PM PDT 24 617810760 ps
T856 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3446468557 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:40 PM PDT 24 62066347 ps
T857 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2380874787 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:05 PM PDT 24 249465568 ps
T858 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.186087134 Aug 03 04:22:32 PM PDT 24 Aug 03 04:22:34 PM PDT 24 50909774 ps
T859 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178712300 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:02 PM PDT 24 312547936 ps
T860 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1573854008 Aug 03 04:19:32 PM PDT 24 Aug 03 04:19:33 PM PDT 24 146792056 ps
T861 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1123692977 Aug 03 04:19:12 PM PDT 24 Aug 03 04:19:13 PM PDT 24 56608959 ps
T862 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2490844131 Aug 03 04:21:00 PM PDT 24 Aug 03 04:21:02 PM PDT 24 67549419 ps
T863 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.185089118 Aug 03 04:23:14 PM PDT 24 Aug 03 04:23:15 PM PDT 24 152510611 ps
T864 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1565888210 Aug 03 04:21:36 PM PDT 24 Aug 03 04:21:37 PM PDT 24 363129865 ps
T865 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207721062 Aug 03 04:21:24 PM PDT 24 Aug 03 04:21:25 PM PDT 24 265745240 ps
T866 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2006681911 Aug 03 04:20:59 PM PDT 24 Aug 03 04:21:00 PM PDT 24 94094350 ps
T867 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2419865457 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:48 PM PDT 24 22625129 ps
T868 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2833493987 Aug 03 04:19:13 PM PDT 24 Aug 03 04:19:14 PM PDT 24 140830331 ps
T869 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1058834498 Aug 03 04:19:44 PM PDT 24 Aug 03 04:19:44 PM PDT 24 39834144 ps
T870 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332550493 Aug 03 04:19:19 PM PDT 24 Aug 03 04:19:20 PM PDT 24 124277574 ps
T871 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4265234036 Aug 03 04:19:23 PM PDT 24 Aug 03 04:19:24 PM PDT 24 72407043 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2477601051 Aug 03 04:20:40 PM PDT 24 Aug 03 04:20:41 PM PDT 24 19776159 ps
T873 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322126395 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:42 PM PDT 24 51992110 ps
T874 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3369753388 Aug 03 04:19:20 PM PDT 24 Aug 03 04:19:21 PM PDT 24 138245657 ps
T875 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1573688006 Aug 03 04:22:47 PM PDT 24 Aug 03 04:22:48 PM PDT 24 39517718 ps
T876 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3286571028 Aug 03 04:20:59 PM PDT 24 Aug 03 04:21:00 PM PDT 24 240040831 ps
T877 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.487371743 Aug 03 04:20:40 PM PDT 24 Aug 03 04:20:41 PM PDT 24 130729963 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652618048 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 285326076 ps
T879 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1422823359 Aug 03 04:23:38 PM PDT 24 Aug 03 04:23:40 PM PDT 24 134736569 ps
T880 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2183410456 Aug 03 04:21:40 PM PDT 24 Aug 03 04:21:41 PM PDT 24 33873258 ps
T881 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.262051134 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:03 PM PDT 24 202984143 ps
T882 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.774269754 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:58 PM PDT 24 42051244 ps
T883 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.226307406 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 155450007 ps
T884 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3950199807 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 57850886 ps
T885 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3348144175 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:04 PM PDT 24 108831462 ps
T886 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.133312789 Aug 03 04:21:04 PM PDT 24 Aug 03 04:21:05 PM PDT 24 86284307 ps
T887 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1229905740 Aug 03 04:20:53 PM PDT 24 Aug 03 04:20:54 PM PDT 24 59300018 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3666127625 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:33 PM PDT 24 137590580 ps
T889 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3759100530 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:48 PM PDT 24 162009040 ps
T890 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302485232 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:50 PM PDT 24 89483722 ps
T891 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3959484336 Aug 03 04:21:21 PM PDT 24 Aug 03 04:21:24 PM PDT 24 54116936 ps
T892 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2941484409 Aug 03 04:21:16 PM PDT 24 Aug 03 04:21:16 PM PDT 24 116353709 ps
T893 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538655903 Aug 03 04:21:03 PM PDT 24 Aug 03 04:21:05 PM PDT 24 53966729 ps
T894 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1936669927 Aug 03 04:21:37 PM PDT 24 Aug 03 04:21:38 PM PDT 24 91913822 ps
T895 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3171641359 Aug 03 04:22:06 PM PDT 24 Aug 03 04:22:07 PM PDT 24 49258791 ps
T896 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2906803170 Aug 03 04:19:38 PM PDT 24 Aug 03 04:19:39 PM PDT 24 231336622 ps
T897 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2759488712 Aug 03 04:19:38 PM PDT 24 Aug 03 04:19:39 PM PDT 24 118657539 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3076435668 Aug 03 04:19:34 PM PDT 24 Aug 03 04:19:35 PM PDT 24 113492601 ps
T899 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2756708928 Aug 03 04:19:24 PM PDT 24 Aug 03 04:19:25 PM PDT 24 131290210 ps
T900 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2701766374 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:01 PM PDT 24 70070487 ps
T901 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3180522862 Aug 03 04:21:00 PM PDT 24 Aug 03 04:21:01 PM PDT 24 260714666 ps
T902 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.191879833 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:57 PM PDT 24 81267406 ps
T903 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.669370803 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:37 PM PDT 24 579987645 ps
T904 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2871243532 Aug 03 04:18:39 PM PDT 24 Aug 03 04:18:41 PM PDT 24 86796644 ps
T905 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3867414739 Aug 03 04:22:14 PM PDT 24 Aug 03 04:22:15 PM PDT 24 42856812 ps
T906 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2144103782 Aug 03 04:20:34 PM PDT 24 Aug 03 04:20:35 PM PDT 24 52780418 ps
T907 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.277342312 Aug 03 04:20:43 PM PDT 24 Aug 03 04:20:44 PM PDT 24 52119625 ps
T908 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1559809070 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:16 PM PDT 24 108057051 ps
T909 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3515338649 Aug 03 04:19:20 PM PDT 24 Aug 03 04:19:21 PM PDT 24 37407159 ps
T910 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3295499272 Aug 03 04:21:22 PM PDT 24 Aug 03 04:21:23 PM PDT 24 45519959 ps
T911 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101411421 Aug 03 04:22:11 PM PDT 24 Aug 03 04:22:12 PM PDT 24 51665258 ps
T912 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1409567254 Aug 03 04:20:42 PM PDT 24 Aug 03 04:20:44 PM PDT 24 133814801 ps
T913 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.30986947 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 278554659 ps
T914 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2769434300 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:36 PM PDT 24 38161146 ps
T915 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4074981825 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:53 PM PDT 24 59157299 ps
T916 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2890327104 Aug 03 04:18:43 PM PDT 24 Aug 03 04:18:44 PM PDT 24 45446214 ps
T917 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1858814333 Aug 03 04:20:57 PM PDT 24 Aug 03 04:20:59 PM PDT 24 326624869 ps
T918 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.971316456 Aug 03 04:19:45 PM PDT 24 Aug 03 04:19:46 PM PDT 24 79004950 ps
T919 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639837779 Aug 03 04:21:40 PM PDT 24 Aug 03 04:21:41 PM PDT 24 145661819 ps
T920 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2760158523 Aug 03 04:20:40 PM PDT 24 Aug 03 04:20:42 PM PDT 24 262012367 ps
T921 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.889671256 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:09 PM PDT 24 85036352 ps
T922 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3754799593 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 88135432 ps
T923 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2998087350 Aug 03 04:19:25 PM PDT 24 Aug 03 04:19:26 PM PDT 24 95462903 ps
T924 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272389833 Aug 03 04:20:45 PM PDT 24 Aug 03 04:20:47 PM PDT 24 280926547 ps
T925 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.759631957 Aug 03 04:20:57 PM PDT 24 Aug 03 04:20:58 PM PDT 24 112897771 ps
T926 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.922051327 Aug 03 04:20:58 PM PDT 24 Aug 03 04:21:00 PM PDT 24 504596075 ps
T927 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3729286851 Aug 03 04:21:44 PM PDT 24 Aug 03 04:21:45 PM PDT 24 55634888 ps
T928 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3211020250 Aug 03 04:21:49 PM PDT 24 Aug 03 04:21:50 PM PDT 24 43510379 ps
T929 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698655825 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:58 PM PDT 24 325006946 ps
T930 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.134747112 Aug 03 04:20:59 PM PDT 24 Aug 03 04:21:00 PM PDT 24 100787017 ps
T931 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.479510309 Aug 03 04:20:45 PM PDT 24 Aug 03 04:20:47 PM PDT 24 313412391 ps
T932 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440952798 Aug 03 04:21:10 PM PDT 24 Aug 03 04:21:11 PM PDT 24 43520950 ps
T933 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2827658199 Aug 03 04:23:22 PM PDT 24 Aug 03 04:23:24 PM PDT 24 154976070 ps
T934 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2685842442 Aug 03 04:19:48 PM PDT 24 Aug 03 04:19:50 PM PDT 24 64636190 ps
T935 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3681557429 Aug 03 04:21:16 PM PDT 24 Aug 03 04:21:17 PM PDT 24 67596142 ps
T936 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.163417463 Aug 03 04:21:00 PM PDT 24 Aug 03 04:21:01 PM PDT 24 70083924 ps
T937 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3503493326 Aug 03 04:21:30 PM PDT 24 Aug 03 04:21:31 PM PDT 24 51210268 ps
T938 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990847245 Aug 03 04:19:51 PM PDT 24 Aug 03 04:19:53 PM PDT 24 330613089 ps
T939 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2992189580 Aug 03 04:20:42 PM PDT 24 Aug 03 04:20:44 PM PDT 24 261101793 ps
T940 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3061147288 Aug 03 04:20:42 PM PDT 24 Aug 03 04:20:44 PM PDT 24 185749878 ps
T941 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618924004 Aug 03 04:19:32 PM PDT 24 Aug 03 04:19:33 PM PDT 24 68190418 ps
T942 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187806947 Aug 03 04:18:50 PM PDT 24 Aug 03 04:18:51 PM PDT 24 148775442 ps
T943 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2865303508 Aug 03 04:19:36 PM PDT 24 Aug 03 04:19:38 PM PDT 24 41460190 ps
T944 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3753609940 Aug 03 04:20:45 PM PDT 24 Aug 03 04:20:46 PM PDT 24 102244772 ps
T945 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.774794204 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:09 PM PDT 24 632101578 ps
T946 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132854542 Aug 03 04:21:09 PM PDT 24 Aug 03 04:21:10 PM PDT 24 39995872 ps
T947 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040477637 Aug 03 04:20:58 PM PDT 24 Aug 03 04:20:59 PM PDT 24 341598992 ps
T948 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1329907618 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:10 PM PDT 24 227130545 ps

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3162561369
Short name T25
Test name
Test status
Simulation time 12309862784 ps
CPU time 356.52 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:51:57 PM PDT 24
Peak memory 198852 kb
Host smart-a181fe3f-9d16-4efb-855a-ad675bec79f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3162561369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3162561369
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.946488422
Short name T27
Test name
Test status
Simulation time 171282963 ps
CPU time 1.63 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 197508 kb
Host smart-aac643f4-c375-4cd8-abfd-781b99197bf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946488422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.946488422
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2495512014
Short name T23
Test name
Test status
Simulation time 87671282 ps
CPU time 1.02 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 215416 kb
Host smart-3f3a3881-bcf0-49a0-b35f-75538abcb4e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495512014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2495512014
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3738810295
Short name T75
Test name
Test status
Simulation time 14119582 ps
CPU time 0.58 seconds
Started Aug 03 04:20:33 PM PDT 24
Finished Aug 03 04:20:34 PM PDT 24
Peak memory 194760 kb
Host smart-1659b4c3-ecc9-4ee3-b738-3a1c98460879
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738810295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3738810295
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3556161951
Short name T1
Test name
Test status
Simulation time 20493959557 ps
CPU time 62.39 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 198732 kb
Host smart-14eb890f-ad1b-4692-a047-d007692119fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556161951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3556161951
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.928849562
Short name T46
Test name
Test status
Simulation time 188648096 ps
CPU time 1.5 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:34 PM PDT 24
Peak memory 198224 kb
Host smart-2a17e84f-d635-40b9-b3bd-0b1077a10428
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928849562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.928849562
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.577538391
Short name T212
Test name
Test status
Simulation time 11483471 ps
CPU time 0.6 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 194452 kb
Host smart-a9fdae3f-0042-4b50-a964-3ddb973cd2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577538391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.577538391
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1072438480
Short name T114
Test name
Test status
Simulation time 700938120 ps
CPU time 1.4 seconds
Started Aug 03 04:24:29 PM PDT 24
Finished Aug 03 04:24:30 PM PDT 24
Peak memory 198600 kb
Host smart-7ff13160-f9b9-4605-a4f2-e5d9f568bfeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072438480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1072438480
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1332707636
Short name T83
Test name
Test status
Simulation time 60100600 ps
CPU time 0.8 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:00 PM PDT 24
Peak memory 195628 kb
Host smart-d48db771-20b8-4ad8-bde4-714d8d1682f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332707636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1332707636
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3604533893
Short name T103
Test name
Test status
Simulation time 66438464 ps
CPU time 0.6 seconds
Started Aug 03 04:23:35 PM PDT 24
Finished Aug 03 04:23:35 PM PDT 24
Peak memory 195044 kb
Host smart-3883df46-33e1-4575-ba76-05f88e14203c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604533893 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3604533893
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1648980206
Short name T78
Test name
Test status
Simulation time 1609049675 ps
CPU time 3.44 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:23 PM PDT 24
Peak memory 197780 kb
Host smart-192269a1-9f87-4814-8813-e65611feeab3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648980206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1648980206
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2373134261
Short name T80
Test name
Test status
Simulation time 13564690 ps
CPU time 0.71 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:39 PM PDT 24
Peak memory 195092 kb
Host smart-f8e1936d-e16c-4b56-bd2d-92f40c142e76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373134261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2373134261
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.75446622
Short name T818
Test name
Test status
Simulation time 30139084 ps
CPU time 0.95 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 198380 kb
Host smart-60fb099f-bb27-413b-877c-661008ef4e72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75446622 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.75446622
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2865489761
Short name T799
Test name
Test status
Simulation time 29851787 ps
CPU time 0.64 seconds
Started Aug 03 04:19:06 PM PDT 24
Finished Aug 03 04:19:07 PM PDT 24
Peak memory 193824 kb
Host smart-b89b4977-ecd1-4d79-8505-78c378471825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865489761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2865489761
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.464964171
Short name T761
Test name
Test status
Simulation time 64718710 ps
CPU time 0.75 seconds
Started Aug 03 04:21:43 PM PDT 24
Finished Aug 03 04:21:44 PM PDT 24
Peak memory 194984 kb
Host smart-48323678-1ebc-44c7-a250-96413408efb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464964171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.464964171
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1816694038
Short name T790
Test name
Test status
Simulation time 23163735 ps
CPU time 0.74 seconds
Started Aug 03 04:21:14 PM PDT 24
Finished Aug 03 04:21:15 PM PDT 24
Peak memory 196244 kb
Host smart-2feb2278-73bd-462e-9f34-f1f5d7d7f70a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816694038 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1816694038
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3503105084
Short name T774
Test name
Test status
Simulation time 195907715 ps
CPU time 1.3 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:16 PM PDT 24
Peak memory 198612 kb
Host smart-e4ef7209-ae05-4301-8314-7c082c0bce72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503105084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3503105084
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.243014243
Short name T38
Test name
Test status
Simulation time 162274969 ps
CPU time 1.14 seconds
Started Aug 03 04:21:07 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 198572 kb
Host smart-e5dd2988-530b-4af7-b7b7-f04235dbbe83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243014243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.243014243
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.274989469
Short name T90
Test name
Test status
Simulation time 20674337 ps
CPU time 0.73 seconds
Started Aug 03 04:21:14 PM PDT 24
Finished Aug 03 04:21:15 PM PDT 24
Peak memory 196212 kb
Host smart-e94cd617-edc0-4b28-a058-b18c3fa02fdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274989469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.274989469
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4202368155
Short name T796
Test name
Test status
Simulation time 174484982 ps
CPU time 1.3 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 196868 kb
Host smart-64788b36-8001-4e8f-b07e-82cb6e87e1bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202368155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4202368155
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1466376803
Short name T797
Test name
Test status
Simulation time 19929590 ps
CPU time 0.64 seconds
Started Aug 03 04:21:31 PM PDT 24
Finished Aug 03 04:21:32 PM PDT 24
Peak memory 195164 kb
Host smart-2fc05850-acff-4372-8882-2ff7c9f8e9c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466376803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1466376803
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4098402771
Short name T746
Test name
Test status
Simulation time 36866506 ps
CPU time 0.85 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 198084 kb
Host smart-bde7a3d6-c73c-4ff0-be5b-fa99ba5db6f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098402771 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4098402771
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1417697085
Short name T82
Test name
Test status
Simulation time 16487585 ps
CPU time 0.63 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 194980 kb
Host smart-a720c88c-a28e-4fc9-958f-ee5621ae02c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417697085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1417697085
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2473096059
Short name T846
Test name
Test status
Simulation time 40042428 ps
CPU time 0.62 seconds
Started Aug 03 04:19:19 PM PDT 24
Finished Aug 03 04:19:20 PM PDT 24
Peak memory 194268 kb
Host smart-6ad425c5-f1d5-4ee4-8232-517f40a5849e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473096059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2473096059
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3475065500
Short name T810
Test name
Test status
Simulation time 26551803 ps
CPU time 0.79 seconds
Started Aug 03 04:20:15 PM PDT 24
Finished Aug 03 04:20:15 PM PDT 24
Peak memory 196588 kb
Host smart-63724e40-d4ea-4376-97ee-deebc5b1f8e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475065500 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3475065500
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.169027301
Short name T739
Test name
Test status
Simulation time 98540617 ps
CPU time 2.13 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:27 PM PDT 24
Peak memory 197548 kb
Host smart-40c4e8e2-41cf-4649-a806-d65018103b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169027301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.169027301
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.501839822
Short name T53
Test name
Test status
Simulation time 1970602684 ps
CPU time 1.09 seconds
Started Aug 03 04:24:14 PM PDT 24
Finished Aug 03 04:24:15 PM PDT 24
Peak memory 198552 kb
Host smart-7cd837f1-0faf-4f08-9428-a44586dc2988
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501839822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.501839822
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3020762713
Short name T781
Test name
Test status
Simulation time 71060115 ps
CPU time 0.67 seconds
Started Aug 03 04:20:33 PM PDT 24
Finished Aug 03 04:20:35 PM PDT 24
Peak memory 197284 kb
Host smart-61f381e5-9d5c-4e17-bfd4-aa809f1813ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020762713 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3020762713
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1769982803
Short name T736
Test name
Test status
Simulation time 36989846 ps
CPU time 0.57 seconds
Started Aug 03 04:20:30 PM PDT 24
Finished Aug 03 04:20:30 PM PDT 24
Peak memory 194244 kb
Host smart-4ba83c32-0b04-4c97-b635-dfc1c8b6b58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769982803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1769982803
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2599373844
Short name T816
Test name
Test status
Simulation time 262225337 ps
CPU time 0.92 seconds
Started Aug 03 04:21:31 PM PDT 24
Finished Aug 03 04:21:32 PM PDT 24
Peak memory 198416 kb
Host smart-9fad18e7-83bb-46a9-8954-7867ec0b2eb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599373844 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2599373844
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1150283597
Short name T791
Test name
Test status
Simulation time 431934654 ps
CPU time 1.97 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 198628 kb
Host smart-816ba5da-8ceb-4c64-8256-e9d293b6bb10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150283597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1150283597
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2387901910
Short name T47
Test name
Test status
Simulation time 389658187 ps
CPU time 1.31 seconds
Started Aug 03 04:20:00 PM PDT 24
Finished Aug 03 04:20:01 PM PDT 24
Peak memory 198504 kb
Host smart-159f1f4d-f148-4ad9-ad5a-d2095dbad42a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387901910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2387901910
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3453539414
Short name T740
Test name
Test status
Simulation time 99549982 ps
CPU time 0.9 seconds
Started Aug 03 04:21:09 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 198408 kb
Host smart-f45e332a-0c14-47a6-8279-aacf12d280fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453539414 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3453539414
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4172173675
Short name T779
Test name
Test status
Simulation time 16884462 ps
CPU time 0.62 seconds
Started Aug 03 04:23:58 PM PDT 24
Finished Aug 03 04:23:59 PM PDT 24
Peak memory 195396 kb
Host smart-a9b1d427-94d5-4e90-be2f-7c922002b5c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172173675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4172173675
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1607954599
Short name T803
Test name
Test status
Simulation time 50922276 ps
CPU time 0.59 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 194384 kb
Host smart-03dba00f-86cc-4f85-ba7f-6a4652809a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607954599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1607954599
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.538862623
Short name T787
Test name
Test status
Simulation time 13483848 ps
CPU time 0.66 seconds
Started Aug 03 04:20:33 PM PDT 24
Finished Aug 03 04:20:34 PM PDT 24
Peak memory 196056 kb
Host smart-a2490906-fa6e-4054-8ef5-9ee2b61be467
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538862623 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.538862623
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3137573723
Short name T763
Test name
Test status
Simulation time 1147482503 ps
CPU time 3.34 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:41 PM PDT 24
Peak memory 198572 kb
Host smart-d791ef43-1fa4-4fc8-ac7f-2e05d1b071fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137573723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3137573723
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.608185574
Short name T826
Test name
Test status
Simulation time 93818429 ps
CPU time 0.87 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:38 PM PDT 24
Peak memory 198356 kb
Host smart-75fa5b68-c6db-4db8-b7cf-9be646cfcf04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608185574 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.608185574
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.728952099
Short name T808
Test name
Test status
Simulation time 155402233 ps
CPU time 0.62 seconds
Started Aug 03 04:19:59 PM PDT 24
Finished Aug 03 04:20:00 PM PDT 24
Peak memory 195840 kb
Host smart-413f55c4-445c-4b6e-8d12-5c779f6dc070
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728952099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.728952099
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.4099983873
Short name T837
Test name
Test status
Simulation time 15040088 ps
CPU time 0.67 seconds
Started Aug 03 04:23:20 PM PDT 24
Finished Aug 03 04:23:21 PM PDT 24
Peak memory 193572 kb
Host smart-f7ceac09-b942-4300-b5dc-6af7845e6830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099983873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.4099983873
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3357689388
Short name T784
Test name
Test status
Simulation time 67351586 ps
CPU time 0.89 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:16 PM PDT 24
Peak memory 196636 kb
Host smart-814eeb52-9d14-45a5-b8ec-ff10bbfd7317
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357689388 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3357689388
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.560303787
Short name T773
Test name
Test status
Simulation time 59399035 ps
CPU time 1.54 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:17 PM PDT 24
Peak memory 198580 kb
Host smart-6f7346cc-5f6a-4fad-a9bf-e5a3cae0e282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560303787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.560303787
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1096074087
Short name T39
Test name
Test status
Simulation time 437622795 ps
CPU time 1.12 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:25 PM PDT 24
Peak memory 198492 kb
Host smart-1be3cee6-1a06-4138-896b-2ae5e9366559
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096074087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1096074087
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1461619237
Short name T735
Test name
Test status
Simulation time 118825694 ps
CPU time 0.94 seconds
Started Aug 03 04:23:20 PM PDT 24
Finished Aug 03 04:23:22 PM PDT 24
Peak memory 196944 kb
Host smart-ebb10e3f-db9a-41a4-8037-3cfa33d0b6c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461619237 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1461619237
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.80245946
Short name T85
Test name
Test status
Simulation time 25711307 ps
CPU time 0.69 seconds
Started Aug 03 04:20:11 PM PDT 24
Finished Aug 03 04:20:12 PM PDT 24
Peak memory 195360 kb
Host smart-de9c3732-2e75-4765-ae9d-587349e09502
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80245946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_
csr_rw.80245946
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1680207349
Short name T745
Test name
Test status
Simulation time 124969393 ps
CPU time 0.6 seconds
Started Aug 03 04:20:04 PM PDT 24
Finished Aug 03 04:20:05 PM PDT 24
Peak memory 194280 kb
Host smart-76dd27f9-991b-420c-b372-8c916f822487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680207349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1680207349
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3605642639
Short name T786
Test name
Test status
Simulation time 33366923 ps
CPU time 0.79 seconds
Started Aug 03 04:23:20 PM PDT 24
Finished Aug 03 04:23:21 PM PDT 24
Peak memory 195736 kb
Host smart-21723a2e-9021-48cf-95ff-e37716821fa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605642639 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3605642639
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.50741721
Short name T824
Test name
Test status
Simulation time 694157708 ps
CPU time 2.96 seconds
Started Aug 03 04:20:10 PM PDT 24
Finished Aug 03 04:20:13 PM PDT 24
Peak memory 198584 kb
Host smart-533bf909-6ea5-4064-9962-9e974757e53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50741721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.50741721
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4251127855
Short name T48
Test name
Test status
Simulation time 137436301 ps
CPU time 1.32 seconds
Started Aug 03 04:23:21 PM PDT 24
Finished Aug 03 04:23:22 PM PDT 24
Peak memory 198232 kb
Host smart-14971ee7-3607-4338-9d3b-71ea72b6a68d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251127855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4251127855
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.411444740
Short name T827
Test name
Test status
Simulation time 18806079 ps
CPU time 0.71 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 197820 kb
Host smart-c5f52122-a78c-4271-8e6e-366063e9609b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411444740 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.411444740
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2315650442
Short name T771
Test name
Test status
Simulation time 20143894 ps
CPU time 0.69 seconds
Started Aug 03 04:20:09 PM PDT 24
Finished Aug 03 04:20:09 PM PDT 24
Peak memory 195312 kb
Host smart-7ccc4b04-ae93-417a-afbe-64cf25842069
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315650442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2315650442
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1200252263
Short name T817
Test name
Test status
Simulation time 42882122 ps
CPU time 0.57 seconds
Started Aug 03 04:22:04 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 194252 kb
Host smart-7cce48ff-1850-4239-853a-40386c5558a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200252263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1200252263
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1468944766
Short name T812
Test name
Test status
Simulation time 97984069 ps
CPU time 1.23 seconds
Started Aug 03 04:20:19 PM PDT 24
Finished Aug 03 04:20:20 PM PDT 24
Peak memory 198696 kb
Host smart-494570d3-e5be-45ff-9290-755dcde0f151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468944766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1468944766
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2334435825
Short name T820
Test name
Test status
Simulation time 189189537 ps
CPU time 1.35 seconds
Started Aug 03 04:22:55 PM PDT 24
Finished Aug 03 04:22:56 PM PDT 24
Peak memory 198612 kb
Host smart-2a3594c4-3df7-48d0-b5fb-10fcce573915
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334435825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2334435825
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1472592062
Short name T809
Test name
Test status
Simulation time 31188982 ps
CPU time 0.93 seconds
Started Aug 03 04:20:12 PM PDT 24
Finished Aug 03 04:20:13 PM PDT 24
Peak memory 198476 kb
Host smart-b9d6d043-b4b7-44d9-bb28-034bf240db65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472592062 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1472592062
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3329221449
Short name T772
Test name
Test status
Simulation time 31119804 ps
CPU time 0.6 seconds
Started Aug 03 04:22:16 PM PDT 24
Finished Aug 03 04:22:17 PM PDT 24
Peak memory 195064 kb
Host smart-a5738eab-f744-4ffb-8c69-c53d8048a27b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329221449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3329221449
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4192113589
Short name T830
Test name
Test status
Simulation time 41998131 ps
CPU time 0.63 seconds
Started Aug 03 04:20:14 PM PDT 24
Finished Aug 03 04:20:15 PM PDT 24
Peak memory 194936 kb
Host smart-c623339f-52ba-4f54-b58c-2da309920cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192113589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4192113589
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.383644658
Short name T839
Test name
Test status
Simulation time 32575362 ps
CPU time 0.7 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 195400 kb
Host smart-f73c3fa8-ef2e-47dd-8c05-3698152a1f96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383644658 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.383644658
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.203876337
Short name T785
Test name
Test status
Simulation time 136025545 ps
CPU time 2.63 seconds
Started Aug 03 04:22:16 PM PDT 24
Finished Aug 03 04:22:19 PM PDT 24
Peak memory 198620 kb
Host smart-3ed35330-0220-4c2d-859d-ee1c7d777f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203876337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.203876337
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1551055091
Short name T50
Test name
Test status
Simulation time 124874876 ps
CPU time 1.5 seconds
Started Aug 03 04:20:12 PM PDT 24
Finished Aug 03 04:20:14 PM PDT 24
Peak memory 198520 kb
Host smart-795a6dc3-bc81-467e-9a31-d05e44f41a1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551055091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1551055091
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2459380293
Short name T834
Test name
Test status
Simulation time 110257660 ps
CPU time 0.9 seconds
Started Aug 03 04:20:31 PM PDT 24
Finished Aug 03 04:20:32 PM PDT 24
Peak memory 198428 kb
Host smart-d21c96b9-b225-4251-938e-21617201189c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459380293 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2459380293
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2300298869
Short name T84
Test name
Test status
Simulation time 44613827 ps
CPU time 0.56 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 193888 kb
Host smart-ba5dcb19-25c5-4e8f-a30c-8f5728aaf714
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300298869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2300298869
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.801778143
Short name T805
Test name
Test status
Simulation time 62389893 ps
CPU time 0.6 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:21:57 PM PDT 24
Peak memory 194288 kb
Host smart-14a0a7db-7898-41fa-8b91-11d1162a5a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801778143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.801778143
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4095591359
Short name T833
Test name
Test status
Simulation time 31134486 ps
CPU time 0.83 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 197524 kb
Host smart-8a79808c-aed0-43aa-a1b4-e1b981f8d380
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095591359 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4095591359
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2036373721
Short name T829
Test name
Test status
Simulation time 131872567 ps
CPU time 2.55 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:35 PM PDT 24
Peak memory 198608 kb
Host smart-db575377-fac6-45f2-b2ef-50b10a1f50ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036373721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2036373721
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1122344474
Short name T831
Test name
Test status
Simulation time 247729220 ps
CPU time 1.09 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:26 PM PDT 24
Peak memory 198552 kb
Host smart-4843e286-83f7-44fc-9475-7b82f2ba961b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122344474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1122344474
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2696156669
Short name T835
Test name
Test status
Simulation time 13819258 ps
CPU time 0.69 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:21:57 PM PDT 24
Peak memory 197348 kb
Host smart-3ffb5258-bfb6-4415-bd73-1077495f49e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696156669 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2696156669
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2117616631
Short name T87
Test name
Test status
Simulation time 46581540 ps
CPU time 0.67 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 195476 kb
Host smart-b9dc6378-4bdc-4138-ae45-4b706b59f7dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117616631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2117616631
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2670966066
Short name T804
Test name
Test status
Simulation time 16579784 ps
CPU time 0.6 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 194388 kb
Host smart-43340f09-2e77-44a5-ad52-f27d2c3de188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670966066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2670966066
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3268475662
Short name T79
Test name
Test status
Simulation time 13628633 ps
CPU time 0.63 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:52 PM PDT 24
Peak memory 195464 kb
Host smart-8a69f1a1-69bb-402b-9826-4ec2a0463380
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268475662 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3268475662
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.89369977
Short name T807
Test name
Test status
Simulation time 273990331 ps
CPU time 1.69 seconds
Started Aug 03 04:20:25 PM PDT 24
Finished Aug 03 04:20:27 PM PDT 24
Peak memory 198560 kb
Host smart-3243f270-c6a8-49b8-a503-cb3c59ccc2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89369977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.89369977
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3120516730
Short name T49
Test name
Test status
Simulation time 107261769 ps
CPU time 1.37 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 198492 kb
Host smart-3946a653-c1d4-405c-8ae1-dd6f0013b6ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120516730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3120516730
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1332766333
Short name T724
Test name
Test status
Simulation time 14430107 ps
CPU time 0.71 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:33 PM PDT 24
Peak memory 197564 kb
Host smart-c2ad6599-17b7-4544-97df-559fc4844265
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332766333 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1332766333
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2058775933
Short name T733
Test name
Test status
Simulation time 21228047 ps
CPU time 0.6 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 193844 kb
Host smart-d74f03ed-2785-4616-baa0-b92015778b86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058775933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2058775933
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3758835289
Short name T751
Test name
Test status
Simulation time 17047411 ps
CPU time 0.64 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 194400 kb
Host smart-8294a686-4aa2-4b7a-a040-e36f7632dad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758835289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3758835289
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2430229099
Short name T105
Test name
Test status
Simulation time 30557670 ps
CPU time 0.7 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 196748 kb
Host smart-223d4cdb-1e4c-4feb-b527-0136ffb89c93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430229099 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2430229099
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3909010205
Short name T798
Test name
Test status
Simulation time 210878151 ps
CPU time 1.21 seconds
Started Aug 03 04:22:09 PM PDT 24
Finished Aug 03 04:22:11 PM PDT 24
Peak memory 198580 kb
Host smart-a877b996-0508-4bac-aa19-30d263a771d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909010205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3909010205
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4019516017
Short name T752
Test name
Test status
Simulation time 85214564 ps
CPU time 0.8 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 198408 kb
Host smart-df96c6a6-6510-45fd-a66c-59d99d8ac55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019516017 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4019516017
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1621244386
Short name T743
Test name
Test status
Simulation time 15219538 ps
CPU time 0.7 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:26 PM PDT 24
Peak memory 196244 kb
Host smart-1c647e97-b1f2-422b-b736-ff78cdbc62b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621244386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1621244386
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2568325828
Short name T823
Test name
Test status
Simulation time 84804908 ps
CPU time 0.61 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:33 PM PDT 24
Peak memory 194880 kb
Host smart-682ee2f7-cec5-4e42-8050-2772246e3f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568325828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2568325828
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3635920774
Short name T77
Test name
Test status
Simulation time 61573899 ps
CPU time 0.77 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:52 PM PDT 24
Peak memory 196592 kb
Host smart-6f01dfa3-2d02-4f91-8a37-ae107edd52c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635920774 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3635920774
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3359991387
Short name T726
Test name
Test status
Simulation time 40477686 ps
CPU time 1.9 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:21:54 PM PDT 24
Peak memory 198624 kb
Host smart-626a9b51-7966-4fb2-bc5a-8502cf211965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359991387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3359991387
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4148301833
Short name T51
Test name
Test status
Simulation time 276062773 ps
CPU time 1.02 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 198556 kb
Host smart-96dee90c-447a-46d7-b843-211190a71819
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148301833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4148301833
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.340514025
Short name T776
Test name
Test status
Simulation time 18579967 ps
CPU time 0.7 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:38 PM PDT 24
Peak memory 194844 kb
Host smart-8c8c870e-978c-4e03-8270-ba5d8325adbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340514025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.340514025
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3018630269
Short name T815
Test name
Test status
Simulation time 262502631 ps
CPU time 2.48 seconds
Started Aug 03 04:22:00 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 197024 kb
Host smart-ce9a883d-83dc-4b20-a9b1-ce88a72c6adf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018630269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3018630269
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1182511583
Short name T767
Test name
Test status
Simulation time 37167996 ps
CPU time 0.7 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:46 PM PDT 24
Peak memory 193444 kb
Host smart-730aa6e6-c468-4a25-9248-e42f8a9c543e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182511583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1182511583
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3774260240
Short name T794
Test name
Test status
Simulation time 16648917 ps
CPU time 0.71 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:38 PM PDT 24
Peak memory 197176 kb
Host smart-8f1937ad-eeb1-4aa5-89e4-ff5af3581e49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774260240 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3774260240
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3181554843
Short name T88
Test name
Test status
Simulation time 15409660 ps
CPU time 0.62 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 195424 kb
Host smart-6e1f4ee4-7ab3-4927-9ac7-2f2a4d6b617a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181554843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3181554843
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3976414682
Short name T729
Test name
Test status
Simulation time 46279709 ps
CPU time 0.58 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:41 PM PDT 24
Peak memory 194836 kb
Host smart-f4e23ece-96c1-437f-8570-3d9c0133d777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976414682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3976414682
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.412159040
Short name T100
Test name
Test status
Simulation time 53334990 ps
CPU time 0.68 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:41 PM PDT 24
Peak memory 195984 kb
Host smart-f7529380-ffb7-4d5b-acef-218a0990f70a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412159040 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.412159040
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2880247783
Short name T795
Test name
Test status
Simulation time 109135468 ps
CPU time 1.51 seconds
Started Aug 03 04:21:17 PM PDT 24
Finished Aug 03 04:21:19 PM PDT 24
Peak memory 198656 kb
Host smart-a77768f7-3ead-4349-af39-a343e7e00ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880247783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2880247783
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.978199393
Short name T814
Test name
Test status
Simulation time 109324961 ps
CPU time 1.4 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:27 PM PDT 24
Peak memory 197404 kb
Host smart-809c6bb1-98b3-4464-a5ba-04c861215ee3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978199393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.978199393
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.213864701
Short name T848
Test name
Test status
Simulation time 14778179 ps
CPU time 0.64 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:15 PM PDT 24
Peak memory 194940 kb
Host smart-e0428a6d-dac4-4e3f-a191-c661efd976bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213864701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.213864701
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2443162521
Short name T759
Test name
Test status
Simulation time 58368716 ps
CPU time 0.58 seconds
Started Aug 03 04:21:59 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 194884 kb
Host smart-fa8554e5-dfcb-4ac5-8afe-4a7c09bb8911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443162521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2443162521
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2355355094
Short name T800
Test name
Test status
Simulation time 16160477 ps
CPU time 0.61 seconds
Started Aug 03 04:21:42 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 194964 kb
Host smart-8fc87153-e63c-4eaf-b41d-7c96bab77f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355355094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2355355094
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1559865697
Short name T721
Test name
Test status
Simulation time 21277815 ps
CPU time 0.66 seconds
Started Aug 03 04:21:35 PM PDT 24
Finished Aug 03 04:21:36 PM PDT 24
Peak memory 194948 kb
Host smart-f9421fe2-b949-4330-8abb-dfbe0774cb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559865697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1559865697
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3752525217
Short name T828
Test name
Test status
Simulation time 42291826 ps
CPU time 0.62 seconds
Started Aug 03 04:21:34 PM PDT 24
Finished Aug 03 04:21:35 PM PDT 24
Peak memory 194352 kb
Host smart-fc535ed4-0f8c-4da8-8e0b-f68a98f77361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752525217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3752525217
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.397390114
Short name T762
Test name
Test status
Simulation time 42311889 ps
CPU time 0.59 seconds
Started Aug 03 04:21:29 PM PDT 24
Finished Aug 03 04:21:30 PM PDT 24
Peak memory 194288 kb
Host smart-4725d47f-3784-4d83-97f2-19d9987c332c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397390114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.397390114
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.119907721
Short name T764
Test name
Test status
Simulation time 19649929 ps
CPU time 0.61 seconds
Started Aug 03 04:21:48 PM PDT 24
Finished Aug 03 04:21:49 PM PDT 24
Peak memory 195020 kb
Host smart-de8976d5-b86e-47a0-b4d8-698d94bdbd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119907721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.119907721
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2283305619
Short name T730
Test name
Test status
Simulation time 82354277 ps
CPU time 0.62 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 194376 kb
Host smart-d0cd7af1-6384-44aa-b763-e238765444cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283305619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2283305619
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2890431546
Short name T727
Test name
Test status
Simulation time 21561588 ps
CPU time 0.59 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 194248 kb
Host smart-dc59dc7e-2c85-4889-ba42-c6bd87da2284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890431546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2890431546
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3037866836
Short name T777
Test name
Test status
Simulation time 23533204 ps
CPU time 0.58 seconds
Started Aug 03 04:21:20 PM PDT 24
Finished Aug 03 04:21:21 PM PDT 24
Peak memory 194856 kb
Host smart-c9c8df48-4535-460f-a210-e3ad632b66b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037866836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3037866836
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2870933836
Short name T81
Test name
Test status
Simulation time 18685033 ps
CPU time 0.85 seconds
Started Aug 03 04:20:48 PM PDT 24
Finished Aug 03 04:20:49 PM PDT 24
Peak memory 195364 kb
Host smart-00603657-9791-4f9d-a157-60a0d2ca7c0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870933836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2870933836
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2727626795
Short name T842
Test name
Test status
Simulation time 1072751971 ps
CPU time 2.93 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 198484 kb
Host smart-9d05798a-0f40-4156-b782-fa5a0237d491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727626795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2727626795
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.905757670
Short name T86
Test name
Test status
Simulation time 14107804 ps
CPU time 0.6 seconds
Started Aug 03 04:20:54 PM PDT 24
Finished Aug 03 04:20:55 PM PDT 24
Peak memory 195204 kb
Host smart-8ab20839-ce5c-478f-9cf1-d6b05f214124
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905757670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.905757670
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1491193057
Short name T747
Test name
Test status
Simulation time 78311836 ps
CPU time 1.07 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:57 PM PDT 24
Peak memory 198632 kb
Host smart-605482de-790c-4996-9a53-986caec429fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491193057 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1491193057
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2572534541
Short name T757
Test name
Test status
Simulation time 15374903 ps
CPU time 0.71 seconds
Started Aug 03 04:19:38 PM PDT 24
Finished Aug 03 04:19:38 PM PDT 24
Peak memory 195980 kb
Host smart-4782ea08-7853-441d-bc96-d8084a999629
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572534541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2572534541
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1687279271
Short name T841
Test name
Test status
Simulation time 15204781 ps
CPU time 0.6 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 194200 kb
Host smart-05bc3a74-0c50-4eaf-ac28-995eca2c8dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687279271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1687279271
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3099388470
Short name T101
Test name
Test status
Simulation time 59441413 ps
CPU time 0.87 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 196728 kb
Host smart-6514ea64-8905-4649-b093-a6948c31625c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099388470 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3099388470
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2549339326
Short name T792
Test name
Test status
Simulation time 392845905 ps
CPU time 2.09 seconds
Started Aug 03 04:20:48 PM PDT 24
Finished Aug 03 04:20:50 PM PDT 24
Peak memory 198284 kb
Host smart-502432c9-aec7-4451-abdc-036549382724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549339326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2549339326
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.217898620
Short name T845
Test name
Test status
Simulation time 267621041 ps
CPU time 1.07 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:57 PM PDT 24
Peak memory 198492 kb
Host smart-bd616d9f-f474-4391-bf35-b04f727c781b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217898620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.217898620
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1032991202
Short name T742
Test name
Test status
Simulation time 122327929 ps
CPU time 0.59 seconds
Started Aug 03 04:20:30 PM PDT 24
Finished Aug 03 04:20:31 PM PDT 24
Peak memory 194284 kb
Host smart-5a4fce15-7b53-4940-bc7a-d778eea97276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032991202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1032991202
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3485173776
Short name T737
Test name
Test status
Simulation time 53602939 ps
CPU time 0.62 seconds
Started Aug 03 04:21:48 PM PDT 24
Finished Aug 03 04:21:49 PM PDT 24
Peak memory 194308 kb
Host smart-ec2576dc-f1fe-4f9f-84d6-91b5ca30a9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485173776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3485173776
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1512195697
Short name T770
Test name
Test status
Simulation time 119258163 ps
CPU time 0.63 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 194352 kb
Host smart-e047e5f7-f051-412c-8324-81b3b9346d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512195697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1512195697
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.662546240
Short name T732
Test name
Test status
Simulation time 40254729 ps
CPU time 0.71 seconds
Started Aug 03 04:21:44 PM PDT 24
Finished Aug 03 04:21:44 PM PDT 24
Peak memory 194236 kb
Host smart-a2d3fae8-3d68-4eb1-87c6-880d622b27ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662546240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.662546240
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3919516307
Short name T788
Test name
Test status
Simulation time 16871491 ps
CPU time 0.58 seconds
Started Aug 03 04:21:59 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 194272 kb
Host smart-3451a1d5-29f6-4d17-89a2-58f292a95b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919516307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3919516307
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.382947544
Short name T768
Test name
Test status
Simulation time 49055733 ps
CPU time 0.81 seconds
Started Aug 03 04:21:44 PM PDT 24
Finished Aug 03 04:21:44 PM PDT 24
Peak memory 194908 kb
Host smart-d2b809ec-8403-434b-9f09-46329565e640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382947544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.382947544
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2111880995
Short name T760
Test name
Test status
Simulation time 14402386 ps
CPU time 0.63 seconds
Started Aug 03 04:20:37 PM PDT 24
Finished Aug 03 04:20:37 PM PDT 24
Peak memory 194320 kb
Host smart-8e69ff89-1ace-42cd-b48c-b194ed337562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111880995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2111880995
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1441622776
Short name T744
Test name
Test status
Simulation time 22005101 ps
CPU time 0.59 seconds
Started Aug 03 04:21:57 PM PDT 24
Finished Aug 03 04:21:58 PM PDT 24
Peak memory 194260 kb
Host smart-59536bd6-4e49-47d8-8fb1-c5004b1935f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441622776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1441622776
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3079450645
Short name T765
Test name
Test status
Simulation time 40574962 ps
CPU time 0.6 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:20:42 PM PDT 24
Peak memory 194324 kb
Host smart-c9f10389-4b14-4a9c-ad6e-52bce8dca0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079450645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3079450645
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2817081408
Short name T821
Test name
Test status
Simulation time 11906138 ps
CPU time 0.6 seconds
Started Aug 03 04:22:45 PM PDT 24
Finished Aug 03 04:22:45 PM PDT 24
Peak memory 194980 kb
Host smart-34dd1f50-1c5b-4c5c-881c-6ba275e1de72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817081408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2817081408
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2565460328
Short name T89
Test name
Test status
Simulation time 53201844 ps
CPU time 0.65 seconds
Started Aug 03 04:20:48 PM PDT 24
Finished Aug 03 04:20:48 PM PDT 24
Peak memory 193832 kb
Host smart-e9150196-e829-4947-8c22-949a3b45cfda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565460328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2565460328
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2692905231
Short name T780
Test name
Test status
Simulation time 134023734 ps
CPU time 1.55 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:03 PM PDT 24
Peak memory 195180 kb
Host smart-9abb06bc-90ab-4479-b800-8a5920192cb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692905231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2692905231
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1209097702
Short name T738
Test name
Test status
Simulation time 16932396 ps
CPU time 0.67 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:20:41 PM PDT 24
Peak memory 193820 kb
Host smart-69635250-c56e-4ae4-bef9-c794140e8011
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209097702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1209097702
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3632906565
Short name T741
Test name
Test status
Simulation time 16797187 ps
CPU time 0.82 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:03 PM PDT 24
Peak memory 198416 kb
Host smart-d582a0b7-830d-48e4-b0d2-d54b58aad97e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632906565 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3632906565
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1658529765
Short name T750
Test name
Test status
Simulation time 42673429 ps
CPU time 0.63 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:56 PM PDT 24
Peak memory 195996 kb
Host smart-dcd84742-1c35-4710-aac3-6f517f00321f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658529765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1658529765
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1277021781
Short name T728
Test name
Test status
Simulation time 15280266 ps
CPU time 0.58 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 194180 kb
Host smart-8d6e6d77-6b54-4f9d-8a69-657400034e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277021781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1277021781
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2434411835
Short name T783
Test name
Test status
Simulation time 18287605 ps
CPU time 0.59 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:57 PM PDT 24
Peak memory 194648 kb
Host smart-1cd1cd43-891d-4a11-9036-ff70a33d37ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434411835 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2434411835
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3999706807
Short name T749
Test name
Test status
Simulation time 49479443 ps
CPU time 1.39 seconds
Started Aug 03 04:21:02 PM PDT 24
Finished Aug 03 04:21:04 PM PDT 24
Peak memory 198576 kb
Host smart-4b566484-5731-4a0b-876c-c8f5eb0a3c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999706807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3999706807
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2537357252
Short name T36
Test name
Test status
Simulation time 55066642 ps
CPU time 0.83 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:57 PM PDT 24
Peak memory 197380 kb
Host smart-4300f330-323d-4ed1-ba8a-8e592f48af48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537357252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2537357252
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3123380914
Short name T822
Test name
Test status
Simulation time 43840235 ps
CPU time 0.59 seconds
Started Aug 03 04:21:48 PM PDT 24
Finished Aug 03 04:21:49 PM PDT 24
Peak memory 194248 kb
Host smart-9f326903-c5b3-42cb-ba64-21d80fe311cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123380914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3123380914
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1393751226
Short name T789
Test name
Test status
Simulation time 21181800 ps
CPU time 0.71 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:23:23 PM PDT 24
Peak memory 193372 kb
Host smart-aecb0621-4207-4aab-aebc-03eee9b4c471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393751226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1393751226
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1241873233
Short name T806
Test name
Test status
Simulation time 21706968 ps
CPU time 0.63 seconds
Started Aug 03 04:20:38 PM PDT 24
Finished Aug 03 04:20:39 PM PDT 24
Peak memory 194252 kb
Host smart-30e1d7a5-911b-42a7-9045-354178e09a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241873233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1241873233
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3950100542
Short name T843
Test name
Test status
Simulation time 84487780 ps
CPU time 0.63 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:47 PM PDT 24
Peak memory 194268 kb
Host smart-73a72cea-92be-4d83-8094-c4128fcea0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950100542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3950100542
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4091893344
Short name T819
Test name
Test status
Simulation time 11789620 ps
CPU time 0.6 seconds
Started Aug 03 04:22:38 PM PDT 24
Finished Aug 03 04:22:38 PM PDT 24
Peak memory 194304 kb
Host smart-c437db8c-d373-49e7-98f4-9876c295329b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091893344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4091893344
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2174217528
Short name T766
Test name
Test status
Simulation time 13098015 ps
CPU time 0.62 seconds
Started Aug 03 04:20:36 PM PDT 24
Finished Aug 03 04:20:37 PM PDT 24
Peak memory 194632 kb
Host smart-27867bbe-4bfd-4ff0-bf1f-c75080bac8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174217528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2174217528
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2617055488
Short name T753
Test name
Test status
Simulation time 14086395 ps
CPU time 0.6 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 194288 kb
Host smart-776153dd-5a63-4290-a59f-33b3c79624b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617055488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2617055488
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4198888213
Short name T844
Test name
Test status
Simulation time 35599636 ps
CPU time 0.62 seconds
Started Aug 03 04:20:39 PM PDT 24
Finished Aug 03 04:20:40 PM PDT 24
Peak memory 194336 kb
Host smart-edab4be8-3f3c-4d3f-823a-8fcd39b5b8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198888213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4198888213
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3324423168
Short name T722
Test name
Test status
Simulation time 13084635 ps
CPU time 0.59 seconds
Started Aug 03 04:20:38 PM PDT 24
Finished Aug 03 04:20:39 PM PDT 24
Peak memory 194268 kb
Host smart-32ae9cfa-f0dd-4d81-9b2b-a3d3d4f1cd3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324423168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3324423168
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1959020715
Short name T832
Test name
Test status
Simulation time 14305632 ps
CPU time 0.59 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:23:23 PM PDT 24
Peak memory 193144 kb
Host smart-2aa0830e-dc82-4fdd-b030-1fe70ef93dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959020715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1959020715
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2331464548
Short name T801
Test name
Test status
Simulation time 20656851 ps
CPU time 1.06 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 198276 kb
Host smart-a2bb065c-9e7b-4e46-915c-6288fd43f5d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331464548 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2331464548
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3932499191
Short name T734
Test name
Test status
Simulation time 13477869 ps
CPU time 0.57 seconds
Started Aug 03 04:24:17 PM PDT 24
Finished Aug 03 04:24:18 PM PDT 24
Peak memory 194992 kb
Host smart-9016b6e7-dc8c-43cd-b2d4-e95e7cedd333
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932499191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3932499191
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.90009797
Short name T836
Test name
Test status
Simulation time 107581843 ps
CPU time 0.59 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 193868 kb
Host smart-72811f8f-800f-4bdc-bed6-7ad66477418b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90009797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.90009797
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2799656423
Short name T102
Test name
Test status
Simulation time 58185629 ps
CPU time 0.82 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 197412 kb
Host smart-5b8204dc-2f39-482b-9ae3-1d1aeb66ed35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799656423 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2799656423
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.372539499
Short name T782
Test name
Test status
Simulation time 198521562 ps
CPU time 1.22 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 198468 kb
Host smart-f6d30d29-fe2d-4d75-8d68-8ee5692f6b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372539499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.372539499
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2535849264
Short name T52
Test name
Test status
Simulation time 150551727 ps
CPU time 0.84 seconds
Started Aug 03 04:22:34 PM PDT 24
Finished Aug 03 04:22:35 PM PDT 24
Peak memory 197580 kb
Host smart-a94a1388-e3ee-4864-9b31-9e73d7093ade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535849264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2535849264
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2657161617
Short name T748
Test name
Test status
Simulation time 20488038 ps
CPU time 0.72 seconds
Started Aug 03 04:20:50 PM PDT 24
Finished Aug 03 04:20:51 PM PDT 24
Peak memory 198264 kb
Host smart-1ed2e07b-4fba-43c7-9fce-3665aa82671e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657161617 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2657161617
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2157806961
Short name T793
Test name
Test status
Simulation time 18513229 ps
CPU time 0.6 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 195028 kb
Host smart-61766aa1-5fe1-4c58-b7de-eb6d6ef5b4bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157806961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2157806961
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1391069632
Short name T778
Test name
Test status
Simulation time 150413993 ps
CPU time 0.56 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 194288 kb
Host smart-810dc6bb-7b16-475f-ab67-10d5d276e522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391069632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1391069632
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3365141021
Short name T104
Test name
Test status
Simulation time 21772216 ps
CPU time 0.78 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 197416 kb
Host smart-ff3a8877-74ca-4943-bfb7-7aae0510548f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365141021 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3365141021
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2465547831
Short name T775
Test name
Test status
Simulation time 61440376 ps
CPU time 0.9 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:49 PM PDT 24
Peak memory 198420 kb
Host smart-0648e473-c508-42c1-9684-7d3ad902a673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465547831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2465547831
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3094458992
Short name T838
Test name
Test status
Simulation time 119332271 ps
CPU time 1.39 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 198532 kb
Host smart-fbb270b7-0175-4df5-9d1c-30007e5332e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094458992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3094458992
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.232890412
Short name T825
Test name
Test status
Simulation time 162566735 ps
CPU time 0.85 seconds
Started Aug 03 04:20:50 PM PDT 24
Finished Aug 03 04:20:51 PM PDT 24
Peak memory 197608 kb
Host smart-5d4ca9e9-f021-4370-b327-01ef0ed85936
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232890412 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.232890412
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1314203476
Short name T755
Test name
Test status
Simulation time 38819533 ps
CPU time 0.56 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 194492 kb
Host smart-7efec437-e173-4c50-a951-387544eea446
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314203476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1314203476
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3074482485
Short name T723
Test name
Test status
Simulation time 70179882 ps
CPU time 0.59 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 192144 kb
Host smart-d79e64a5-dd36-48e0-9ed7-6c4b5e5ea223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074482485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3074482485
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3838540585
Short name T811
Test name
Test status
Simulation time 42478806 ps
CPU time 0.98 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 194968 kb
Host smart-bcdf035e-bf26-4223-977e-6bb7ddc4fc67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838540585 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3838540585
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3796060974
Short name T731
Test name
Test status
Simulation time 105211515 ps
CPU time 1.33 seconds
Started Aug 03 04:20:50 PM PDT 24
Finished Aug 03 04:20:51 PM PDT 24
Peak memory 197796 kb
Host smart-a151376a-798a-44e1-9290-cef086d4afc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796060974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3796060974
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3009875021
Short name T37
Test name
Test status
Simulation time 146082288 ps
CPU time 0.85 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:21:57 PM PDT 24
Peak memory 197384 kb
Host smart-adf91695-32de-4ba3-ba37-fb747b3890dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009875021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3009875021
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.362814115
Short name T754
Test name
Test status
Simulation time 115062689 ps
CPU time 0.69 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 197884 kb
Host smart-231e67f2-e133-40c6-a216-47e902a2b0cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362814115 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.362814115
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.5293393
Short name T769
Test name
Test status
Simulation time 15215437 ps
CPU time 0.59 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:52 PM PDT 24
Peak memory 194964 kb
Host smart-dca63d02-0745-4edb-a63b-0cc012aa04e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5293393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ
=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_cs
r_rw.5293393
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.278620066
Short name T725
Test name
Test status
Simulation time 11728581 ps
CPU time 0.56 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 194908 kb
Host smart-483a0a2a-66ae-4302-945c-c6ff5fbba4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278620066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.278620066
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4043860871
Short name T74
Test name
Test status
Simulation time 176792424 ps
CPU time 0.6 seconds
Started Aug 03 04:21:05 PM PDT 24
Finished Aug 03 04:21:06 PM PDT 24
Peak memory 194728 kb
Host smart-131bf63b-64c3-4e08-9feb-a4bfb1d996c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043860871 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4043860871
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3465887241
Short name T840
Test name
Test status
Simulation time 33799890 ps
CPU time 1.6 seconds
Started Aug 03 04:21:06 PM PDT 24
Finished Aug 03 04:21:07 PM PDT 24
Peak memory 198528 kb
Host smart-cbc3407e-88ab-4f0e-9428-4f20e3774997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465887241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3465887241
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2120318907
Short name T45
Test name
Test status
Simulation time 202217696 ps
CPU time 1.13 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 198500 kb
Host smart-9cde6211-9d92-4ce5-8b12-0654612a5700
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120318907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2120318907
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1631651381
Short name T813
Test name
Test status
Simulation time 25967430 ps
CPU time 0.87 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 198364 kb
Host smart-c9dbffb1-58a8-47f4-9b95-b53a3961b070
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631651381 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1631651381
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.348145696
Short name T758
Test name
Test status
Simulation time 13851236 ps
CPU time 0.59 seconds
Started Aug 03 04:20:29 PM PDT 24
Finished Aug 03 04:20:30 PM PDT 24
Peak memory 195092 kb
Host smart-6e34a16b-b1d8-4732-b122-dc43bc741db0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348145696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.348145696
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1692114811
Short name T802
Test name
Test status
Simulation time 78976110 ps
CPU time 0.59 seconds
Started Aug 03 04:23:57 PM PDT 24
Finished Aug 03 04:23:58 PM PDT 24
Peak memory 194412 kb
Host smart-8cd58de8-8bde-43c4-92fd-7b435e972c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692114811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1692114811
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2835718186
Short name T76
Test name
Test status
Simulation time 225422879 ps
CPU time 0.71 seconds
Started Aug 03 04:20:33 PM PDT 24
Finished Aug 03 04:20:34 PM PDT 24
Peak memory 196544 kb
Host smart-b26459b8-6b91-4627-80fe-e59017e9b3d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835718186 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2835718186
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3559540978
Short name T756
Test name
Test status
Simulation time 53872253 ps
CPU time 1.92 seconds
Started Aug 03 04:20:24 PM PDT 24
Finished Aug 03 04:20:26 PM PDT 24
Peak memory 198652 kb
Host smart-535d3484-fbc4-4947-b6d9-93b377e865c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559540978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3559540978
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2071873136
Short name T847
Test name
Test status
Simulation time 399019179 ps
CPU time 1.42 seconds
Started Aug 03 04:19:52 PM PDT 24
Finished Aug 03 04:19:54 PM PDT 24
Peak memory 198616 kb
Host smart-da5afd40-320f-4498-89f4-5fe4fa3deae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071873136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2071873136
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1677873516
Short name T63
Test name
Test status
Simulation time 35507592 ps
CPU time 0.57 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 194480 kb
Host smart-c869efc0-d42a-40d6-b7bc-bcefe4e64ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677873516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1677873516
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3939229863
Short name T164
Test name
Test status
Simulation time 41605644 ps
CPU time 0.92 seconds
Started Aug 03 04:44:22 PM PDT 24
Finished Aug 03 04:44:23 PM PDT 24
Peak memory 196520 kb
Host smart-16a0c5b1-d795-4bc4-9454-45fac5e1d638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939229863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3939229863
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3959746138
Short name T537
Test name
Test status
Simulation time 2475588498 ps
CPU time 20.24 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:44 PM PDT 24
Peak memory 197048 kb
Host smart-ece62d6f-ab53-4196-b9ec-172a0805f72f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959746138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3959746138
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2324665822
Short name T134
Test name
Test status
Simulation time 281385784 ps
CPU time 0.87 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 196472 kb
Host smart-98686bda-74a4-4114-a9b5-d93f38db260b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324665822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2324665822
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.981921233
Short name T197
Test name
Test status
Simulation time 324042496 ps
CPU time 1.4 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 196348 kb
Host smart-be1512a8-e940-4a12-ac90-41e7d964a4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981921233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.981921233
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2855967887
Short name T319
Test name
Test status
Simulation time 63558619 ps
CPU time 2.52 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 198588 kb
Host smart-9750ab68-5f3d-4561-9794-78141f3b32ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855967887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2855967887
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3708469080
Short name T667
Test name
Test status
Simulation time 348337323 ps
CPU time 3.16 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 197656 kb
Host smart-f2722ad8-5b7b-485f-b020-27aaaa06f3fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708469080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3708469080
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1007816966
Short name T619
Test name
Test status
Simulation time 62716500 ps
CPU time 0.69 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 194892 kb
Host smart-e5bd995c-2c16-444a-9655-b5397fc00c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007816966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1007816966
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1166302825
Short name T218
Test name
Test status
Simulation time 46091539 ps
CPU time 0.74 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:24 PM PDT 24
Peak memory 195824 kb
Host smart-558a5c6d-af36-44f9-8de2-071c4f2d8b6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166302825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1166302825
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3210956255
Short name T247
Test name
Test status
Simulation time 1291112414 ps
CPU time 5.66 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 198528 kb
Host smart-1a288c6a-c870-44fa-a78b-569195a1c667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210956255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3210956255
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2757597409
Short name T55
Test name
Test status
Simulation time 324537485 ps
CPU time 0.96 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:24 PM PDT 24
Peak memory 215400 kb
Host smart-fde79905-1ca2-4e22-a15d-98f3752b67f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757597409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2757597409
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.855845862
Short name T182
Test name
Test status
Simulation time 120546545 ps
CPU time 1.02 seconds
Started Aug 03 04:44:27 PM PDT 24
Finished Aug 03 04:44:28 PM PDT 24
Peak memory 196348 kb
Host smart-b1dadb6b-6198-40e5-9785-b2230293d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855845862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.855845862
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2099062468
Short name T686
Test name
Test status
Simulation time 319177425 ps
CPU time 1.24 seconds
Started Aug 03 04:44:29 PM PDT 24
Finished Aug 03 04:44:30 PM PDT 24
Peak memory 197028 kb
Host smart-a83c8e27-0a44-4d82-8a90-d25144152fb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099062468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2099062468
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3986087609
Short name T672
Test name
Test status
Simulation time 28229716566 ps
CPU time 121.8 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:46:25 PM PDT 24
Peak memory 198720 kb
Host smart-663822b8-426c-4422-80fb-98cd647d4235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986087609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3986087609
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3053006579
Short name T571
Test name
Test status
Simulation time 96634256 ps
CPU time 0.77 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 195660 kb
Host smart-3b775b0f-a8dc-488e-9510-b015db4d3875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053006579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3053006579
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1073834933
Short name T701
Test name
Test status
Simulation time 1171829998 ps
CPU time 4.71 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 196380 kb
Host smart-7f687403-7127-4597-9228-ec51c9e59be4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073834933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1073834933
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.538294566
Short name T521
Test name
Test status
Simulation time 287342583 ps
CPU time 1.04 seconds
Started Aug 03 04:44:27 PM PDT 24
Finished Aug 03 04:44:28 PM PDT 24
Peak memory 196912 kb
Host smart-38c0ec70-c64b-4962-876f-63008d87ecb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538294566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.538294566
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2034594114
Short name T351
Test name
Test status
Simulation time 17081703 ps
CPU time 0.68 seconds
Started Aug 03 04:44:27 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 194752 kb
Host smart-3659fa38-0abb-4e99-ba5a-65621e31062c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034594114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2034594114
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1370073630
Short name T334
Test name
Test status
Simulation time 70157511 ps
CPU time 2.58 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 196836 kb
Host smart-c5616087-47ec-41cc-b129-84911549df1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370073630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1370073630
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3776357434
Short name T203
Test name
Test status
Simulation time 319678556 ps
CPU time 1.8 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:28 PM PDT 24
Peak memory 196680 kb
Host smart-46b1ebac-ba3a-4744-bd4b-4dd475701887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776357434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3776357434
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.46944098
Short name T235
Test name
Test status
Simulation time 120873592 ps
CPU time 0.97 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 196396 kb
Host smart-1f2b5505-668c-4f06-8641-de3e6a0da1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46944098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.46944098
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1440024408
Short name T410
Test name
Test status
Simulation time 38548024 ps
CPU time 1.42 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 196404 kb
Host smart-ce6948d7-92ff-43dd-b2fc-4ca7ab0d4fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440024408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1440024408
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1604529909
Short name T268
Test name
Test status
Simulation time 863511572 ps
CPU time 3.79 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:30 PM PDT 24
Peak memory 198544 kb
Host smart-3f9294e1-f1be-499d-a056-70de1c349094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604529909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1604529909
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3164524937
Short name T339
Test name
Test status
Simulation time 145741633 ps
CPU time 1.17 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 196256 kb
Host smart-59dc31bf-4517-4531-8c85-7ad1726189e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164524937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3164524937
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.177955522
Short name T562
Test name
Test status
Simulation time 359937980 ps
CPU time 1.36 seconds
Started Aug 03 04:44:23 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 196100 kb
Host smart-bc52628f-bfd9-4e5d-9e47-1b5be1de8a46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177955522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.177955522
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.834215237
Short name T494
Test name
Test status
Simulation time 10185971756 ps
CPU time 137 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:46:43 PM PDT 24
Peak memory 198656 kb
Host smart-a703ba41-19bb-46d0-88c6-0e4c1295e2e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834215237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.834215237
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3412819744
Short name T518
Test name
Test status
Simulation time 148936435907 ps
CPU time 594.11 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:54:20 PM PDT 24
Peak memory 198880 kb
Host smart-a9cd729f-64ed-468f-bb2b-48592f0bd7fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3412819744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3412819744
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.362410975
Short name T585
Test name
Test status
Simulation time 64448837 ps
CPU time 0.6 seconds
Started Aug 03 04:44:45 PM PDT 24
Finished Aug 03 04:44:46 PM PDT 24
Peak memory 195168 kb
Host smart-24291fb9-6da7-4f82-b55f-48e14f48a0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362410975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.362410975
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2075378541
Short name T615
Test name
Test status
Simulation time 36521327 ps
CPU time 0.71 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:44:47 PM PDT 24
Peak memory 194704 kb
Host smart-8dc89276-3020-4c78-ab82-adc2222cf72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075378541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2075378541
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.714365226
Short name T120
Test name
Test status
Simulation time 6269752782 ps
CPU time 21.06 seconds
Started Aug 03 04:44:42 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 197896 kb
Host smart-f20052ad-7506-4b22-9f12-d6fa65fbb079
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714365226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.714365226
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.983830096
Short name T12
Test name
Test status
Simulation time 169833682 ps
CPU time 0.98 seconds
Started Aug 03 04:44:40 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 197188 kb
Host smart-b2d94d93-0180-492f-8071-8734ed3f1d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983830096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.983830096
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3066980971
Short name T473
Test name
Test status
Simulation time 83169072 ps
CPU time 1.38 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 197452 kb
Host smart-2de60b6c-0d16-4ffe-9e31-e3508038ffc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066980971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3066980971
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3502353335
Short name T557
Test name
Test status
Simulation time 71346991 ps
CPU time 2.83 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 197076 kb
Host smart-563e2c87-82e2-40d2-8ace-77f8226d0d62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502353335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3502353335
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2272906932
Short name T457
Test name
Test status
Simulation time 397692405 ps
CPU time 2.92 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 197536 kb
Host smart-256ab5d6-6f6a-4574-8445-923a828cc013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272906932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2272906932
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1719445787
Short name T501
Test name
Test status
Simulation time 61964478 ps
CPU time 1.37 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 196428 kb
Host smart-fdb04ba1-1de9-48d9-bc92-08d149e072a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719445787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1719445787
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1663059847
Short name T605
Test name
Test status
Simulation time 56348753 ps
CPU time 1.23 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 197400 kb
Host smart-31a734e5-835b-4696-8afc-7492a6821aa0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663059847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1663059847
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1687151056
Short name T281
Test name
Test status
Simulation time 134751437 ps
CPU time 1.89 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:46 PM PDT 24
Peak memory 198448 kb
Host smart-e3ed891a-79b1-426a-aeb7-1a9cb7714206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687151056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1687151056
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1505476784
Short name T201
Test name
Test status
Simulation time 38296380 ps
CPU time 1.16 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 196136 kb
Host smart-8622edbd-a89d-4a68-be36-4d4c5166cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505476784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1505476784
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3219249937
Short name T517
Test name
Test status
Simulation time 520669064 ps
CPU time 1.2 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 196300 kb
Host smart-c46144aa-1377-402a-a5e9-a6c9afcde1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219249937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3219249937
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.958782325
Short name T402
Test name
Test status
Simulation time 8325984058 ps
CPU time 62.43 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 198732 kb
Host smart-8f99f0f5-0162-4457-855f-a479b8722078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958782325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.958782325
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1759369793
Short name T59
Test name
Test status
Simulation time 262603138254 ps
CPU time 1905.5 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 05:16:23 PM PDT 24
Peak memory 198792 kb
Host smart-ffaff52f-2673-4691-9d72-340d90aa7bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1759369793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1759369793
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1735420295
Short name T71
Test name
Test status
Simulation time 12969855 ps
CPU time 0.59 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 194636 kb
Host smart-fa23a345-2905-473d-9c6f-5c35f3e13c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735420295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1735420295
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.220049673
Short name T567
Test name
Test status
Simulation time 29188820 ps
CPU time 0.88 seconds
Started Aug 03 04:44:40 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 196500 kb
Host smart-c5432434-7261-406d-b4c9-f0641d75a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220049673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.220049673
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2375094811
Short name T606
Test name
Test status
Simulation time 202106025 ps
CPU time 9.94 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:48 PM PDT 24
Peak memory 198576 kb
Host smart-079536b3-28ea-4467-bfc5-37670dafde6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375094811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2375094811
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.768168380
Short name T621
Test name
Test status
Simulation time 326692495 ps
CPU time 0.77 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 195956 kb
Host smart-cc9d7e92-7ed4-4fee-a577-056c54146b8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768168380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.768168380
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3830022367
Short name T541
Test name
Test status
Simulation time 52136922 ps
CPU time 0.92 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 197312 kb
Host smart-1ad30e8f-7256-4b6f-8618-0bc93aa4014e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830022367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3830022367
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4093202483
Short name T449
Test name
Test status
Simulation time 962619401 ps
CPU time 2.48 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 198444 kb
Host smart-7159007a-d1e1-4168-8462-dd0342c44beb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093202483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4093202483
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3476525496
Short name T288
Test name
Test status
Simulation time 308306411 ps
CPU time 2.93 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:47 PM PDT 24
Peak memory 197552 kb
Host smart-dacdcdff-711f-48bb-9a25-b438c6e5da12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476525496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3476525496
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1727970654
Short name T302
Test name
Test status
Simulation time 37288417 ps
CPU time 0.9 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 196064 kb
Host smart-cd28fe0a-26b1-49bc-b3ee-9b5464461c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727970654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1727970654
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3964938046
Short name T148
Test name
Test status
Simulation time 102786117 ps
CPU time 0.81 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 196916 kb
Host smart-db49122c-065f-487c-abd6-c9bef056e9b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964938046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3964938046
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1262564483
Short name T422
Test name
Test status
Simulation time 468255002 ps
CPU time 1.8 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 198496 kb
Host smart-73a45342-1497-4a00-9a1c-4bf94954bbf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262564483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1262564483
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3634943576
Short name T669
Test name
Test status
Simulation time 300973304 ps
CPU time 1.23 seconds
Started Aug 03 04:44:50 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 196360 kb
Host smart-6bf75014-931e-44c7-bdae-791173058a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634943576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3634943576
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2107329108
Short name T505
Test name
Test status
Simulation time 52382513 ps
CPU time 1.04 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 196168 kb
Host smart-83debb7a-019a-446c-ae39-a1862a29a902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107329108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2107329108
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.123726299
Short name T359
Test name
Test status
Simulation time 9790050407 ps
CPU time 102.06 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:46:21 PM PDT 24
Peak memory 192588 kb
Host smart-05285b66-db99-4f21-9e97-6b92311e19f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123726299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.123726299
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3311677733
Short name T35
Test name
Test status
Simulation time 14905112601 ps
CPU time 259.76 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:48:59 PM PDT 24
Peak memory 198832 kb
Host smart-cdd02d58-5249-4c5c-a640-3618d83b1157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3311677733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3311677733
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1485038147
Short name T477
Test name
Test status
Simulation time 58952458 ps
CPU time 0.62 seconds
Started Aug 03 04:44:55 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 195144 kb
Host smart-ce16f1f9-5230-412f-829f-f54d8a121614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485038147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1485038147
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4252241112
Short name T568
Test name
Test status
Simulation time 21631355 ps
CPU time 0.79 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 195776 kb
Host smart-fa4b8151-bd95-4d26-9f87-d648a976606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252241112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4252241112
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2392241471
Short name T94
Test name
Test status
Simulation time 4014931749 ps
CPU time 17.77 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 197592 kb
Host smart-d155b4a4-0eb8-4ad9-ade8-aaa38434e8c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392241471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2392241471
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4142259947
Short name T570
Test name
Test status
Simulation time 52976769 ps
CPU time 0.84 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 196284 kb
Host smart-130be946-f0ce-4a8d-8227-fb13d74706c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142259947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4142259947
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3912454913
Short name T266
Test name
Test status
Simulation time 19460492 ps
CPU time 0.69 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:48 PM PDT 24
Peak memory 194864 kb
Host smart-ff1bd81c-90cc-4ea6-b0f6-041144f4ca42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912454913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3912454913
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4278361369
Short name T543
Test name
Test status
Simulation time 237424195 ps
CPU time 0.97 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 196920 kb
Host smart-95ece2f8-011f-4b17-b8ed-bf0b27ddb80e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278361369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4278361369
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.996262981
Short name T535
Test name
Test status
Simulation time 345101529 ps
CPU time 2.94 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:44:49 PM PDT 24
Peak memory 198656 kb
Host smart-e128b98d-6c61-4d29-beea-66316639cab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996262981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
996262981
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2717009833
Short name T286
Test name
Test status
Simulation time 204201129 ps
CPU time 1.07 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 197108 kb
Host smart-f8e80955-c745-49a8-a81e-ddb94d7f1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717009833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2717009833
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.575244251
Short name T580
Test name
Test status
Simulation time 223443319 ps
CPU time 1.11 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 196280 kb
Host smart-eefde89f-8277-4cdc-badc-739aeb90d325
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575244251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.575244251
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2149479070
Short name T671
Test name
Test status
Simulation time 453864993 ps
CPU time 2.81 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:44:48 PM PDT 24
Peak memory 198504 kb
Host smart-e9710c8c-2a23-4140-acb5-700ef6861fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149479070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2149479070
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3832484505
Short name T421
Test name
Test status
Simulation time 32380189 ps
CPU time 1.05 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 196348 kb
Host smart-ad7b878b-570f-4952-8a40-0be9985552a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832484505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3832484505
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2911045451
Short name T416
Test name
Test status
Simulation time 120191901 ps
CPU time 1.54 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 197176 kb
Host smart-6be62866-0288-4a30-a2ff-987d61bdeaa5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911045451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2911045451
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.58220654
Short name T72
Test name
Test status
Simulation time 68499918034 ps
CPU time 513.62 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:53:21 PM PDT 24
Peak memory 198860 kb
Host smart-f021af36-984e-4931-a991-0608fc1f08c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=58220654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.58220654
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.810255143
Short name T616
Test name
Test status
Simulation time 24120228 ps
CPU time 0.64 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:48 PM PDT 24
Peak memory 195192 kb
Host smart-9ad9f664-9460-4515-b41f-a4aaa789e6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810255143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.810255143
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.935549868
Short name T18
Test name
Test status
Simulation time 37884691 ps
CPU time 0.89 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 197628 kb
Host smart-53c54960-fcff-4ead-9cda-5c70c4919662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935549868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.935549868
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3699269126
Short name T243
Test name
Test status
Simulation time 192279255 ps
CPU time 9.47 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:44:56 PM PDT 24
Peak memory 196056 kb
Host smart-3f649a6b-24c9-4216-8140-feee8ef04961
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699269126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3699269126
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1153215900
Short name T147
Test name
Test status
Simulation time 106884954 ps
CPU time 0.73 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 195300 kb
Host smart-c77d4d75-26d3-42bf-920c-9d97d590e6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153215900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1153215900
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2790215031
Short name T347
Test name
Test status
Simulation time 151343217 ps
CPU time 1.28 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 196348 kb
Host smart-937f7629-75fb-49f3-9a24-35216cdeb56e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790215031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2790215031
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1721375443
Short name T564
Test name
Test status
Simulation time 106277220 ps
CPU time 2.3 seconds
Started Aug 03 04:44:48 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 197060 kb
Host smart-b72c0006-19ab-48fe-8308-a2417ccd4aa6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721375443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1721375443
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3720671856
Short name T412
Test name
Test status
Simulation time 112811775 ps
CPU time 1.09 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 196196 kb
Host smart-0bea1573-ae9f-4a23-b861-bbf9aff5cabf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720671856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3720671856
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2190295518
Short name T357
Test name
Test status
Simulation time 52541868 ps
CPU time 1.14 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 197396 kb
Host smart-324aa7f8-857b-440f-9f8d-9ac8cc246f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190295518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2190295518
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1980041253
Short name T337
Test name
Test status
Simulation time 16724999 ps
CPU time 0.7 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 195904 kb
Host smart-3c5574b7-071f-42a8-adae-c5f5cc3c5627
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980041253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1980041253
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1064960532
Short name T515
Test name
Test status
Simulation time 82524658 ps
CPU time 1.24 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 198236 kb
Host smart-87ec6f7a-5e58-4bf0-a6dc-f6ecc6a60008
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064960532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1064960532
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1985265303
Short name T252
Test name
Test status
Simulation time 64234419 ps
CPU time 1.03 seconds
Started Aug 03 04:44:50 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 196120 kb
Host smart-55880988-ab27-4912-877f-0635f9ab2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985265303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1985265303
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1623448992
Short name T198
Test name
Test status
Simulation time 286083655 ps
CPU time 1.33 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 196064 kb
Host smart-8403e66a-987b-4d3f-b616-091ef519fcd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623448992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1623448992
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.798020179
Short name T411
Test name
Test status
Simulation time 8181544448 ps
CPU time 116.31 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:46:53 PM PDT 24
Peak memory 198724 kb
Host smart-6c70c083-3bf8-4369-9a1e-39bf470fd495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798020179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.798020179
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1121521632
Short name T155
Test name
Test status
Simulation time 115258032 ps
CPU time 0.59 seconds
Started Aug 03 04:44:48 PM PDT 24
Finished Aug 03 04:44:49 PM PDT 24
Peak memory 194496 kb
Host smart-49c93722-7ce0-43aa-a6d7-dd5519de4ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121521632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1121521632
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2731292642
Short name T608
Test name
Test status
Simulation time 24047049 ps
CPU time 0.65 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 195272 kb
Host smart-02c5172f-aaff-45ce-a8c3-84deedacb54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731292642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2731292642
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2825700389
Short name T611
Test name
Test status
Simulation time 316263678 ps
CPU time 15.92 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 197156 kb
Host smart-0ba3a09b-d43f-45b8-b2a6-c6875028152f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825700389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2825700389
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.860778129
Short name T146
Test name
Test status
Simulation time 83957956 ps
CPU time 0.79 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 197088 kb
Host smart-5918887b-41e1-4cf4-9f40-f996acc2db5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860778129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.860778129
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2316531088
Short name T677
Test name
Test status
Simulation time 121924755 ps
CPU time 1.18 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:48 PM PDT 24
Peak memory 197008 kb
Host smart-8ff65bb0-2ff3-4650-822a-c4262757044d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316531088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2316531088
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.6692610
Short name T595
Test name
Test status
Simulation time 33166778 ps
CPU time 1.43 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 198524 kb
Host smart-6b84ecf6-5bb0-4589-91ae-80db778186fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6692610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_intr_with_filter_rand_intr_event.6692610
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.772588018
Short name T463
Test name
Test status
Simulation time 2070986388 ps
CPU time 2.43 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 196404 kb
Host smart-2b1e5704-c79b-4f13-96cb-be0ced591511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772588018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
772588018
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3638774409
Short name T137
Test name
Test status
Simulation time 51213360 ps
CPU time 1.1 seconds
Started Aug 03 04:44:45 PM PDT 24
Finished Aug 03 04:44:46 PM PDT 24
Peak memory 197132 kb
Host smart-799ed866-ac76-4ffa-84a0-ad21fcab44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638774409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3638774409
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.683000894
Short name T530
Test name
Test status
Simulation time 43373345 ps
CPU time 1.04 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 197228 kb
Host smart-0cc0756e-5856-4e4d-8928-31659dc95519
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683000894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.683000894
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1784711656
Short name T260
Test name
Test status
Simulation time 323505324 ps
CPU time 5.49 seconds
Started Aug 03 04:45:00 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 198484 kb
Host smart-a2565353-18ba-49f8-930b-b3343813fa43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784711656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1784711656
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1850790900
Short name T588
Test name
Test status
Simulation time 271000564 ps
CPU time 1.34 seconds
Started Aug 03 04:44:55 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 197164 kb
Host smart-7fa6b887-34be-4933-9a90-b21980693908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850790900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1850790900
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.667252641
Short name T216
Test name
Test status
Simulation time 348992220 ps
CPU time 1.41 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 197316 kb
Host smart-a05473bf-5786-4991-99ad-d8ed261d1039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667252641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.667252641
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2603131404
Short name T376
Test name
Test status
Simulation time 2163746970 ps
CPU time 51.3 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 198784 kb
Host smart-665d659e-fcb1-49a6-98ed-624d805ad551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603131404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2603131404
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3193350352
Short name T454
Test name
Test status
Simulation time 14468544 ps
CPU time 0.6 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 194404 kb
Host smart-d1906c04-88f3-4390-95cb-657de8e95e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193350352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3193350352
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2244957597
Short name T602
Test name
Test status
Simulation time 107095884 ps
CPU time 0.97 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 196560 kb
Host smart-9428e5fb-36c5-4e60-a5d1-5879459dd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244957597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2244957597
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4011770498
Short name T112
Test name
Test status
Simulation time 1998020732 ps
CPU time 16.77 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 196080 kb
Host smart-7073517e-af47-4160-b9f7-01b6cc984856
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011770498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4011770498
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.51521475
Short name T333
Test name
Test status
Simulation time 122978913 ps
CPU time 0.7 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 195088 kb
Host smart-7f0b7690-fd3d-4062-91d7-8617f616e594
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51521475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.51521475
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3117653939
Short name T478
Test name
Test status
Simulation time 240847133 ps
CPU time 1.15 seconds
Started Aug 03 04:44:55 PM PDT 24
Finished Aug 03 04:44:56 PM PDT 24
Peak memory 197320 kb
Host smart-cf18b7fb-b0a9-4783-a15a-8e165f5d5294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117653939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3117653939
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.30899348
Short name T142
Test name
Test status
Simulation time 69354991 ps
CPU time 2.75 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 198708 kb
Host smart-0c36b3f1-85f8-4453-ad32-35896144f8b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30899348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.gpio_intr_with_filter_rand_intr_event.30899348
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.44076275
Short name T361
Test name
Test status
Simulation time 700510215 ps
CPU time 3.18 seconds
Started Aug 03 04:44:45 PM PDT 24
Finished Aug 03 04:44:49 PM PDT 24
Peak memory 198532 kb
Host smart-77f5a0d5-fec0-46ec-b394-e13d1e9661cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44076275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.44076275
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4127314204
Short name T397
Test name
Test status
Simulation time 405537519 ps
CPU time 1.16 seconds
Started Aug 03 04:44:55 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 196260 kb
Host smart-ba8abf33-70a9-4ed6-84b8-efd9b1cba6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127314204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4127314204
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.523817281
Short name T563
Test name
Test status
Simulation time 46186420 ps
CPU time 1.01 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 197288 kb
Host smart-ae40e063-21e3-4b6a-b389-8315f6295f73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523817281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.523817281
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2198003364
Short name T264
Test name
Test status
Simulation time 91688210 ps
CPU time 3.86 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 198540 kb
Host smart-493a740f-9650-418e-ba4e-0f67626a4b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198003364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2198003364
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3868077204
Short name T712
Test name
Test status
Simulation time 41398630 ps
CPU time 0.87 seconds
Started Aug 03 04:44:49 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 195852 kb
Host smart-f62d51bd-0f36-48b6-9d46-0346ced8f2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868077204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3868077204
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3741083323
Short name T310
Test name
Test status
Simulation time 134269441 ps
CPU time 1.02 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:49 PM PDT 24
Peak memory 196996 kb
Host smart-ef0d34f7-0fb7-4f5b-9110-835b6e6f3083
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741083323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3741083323
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2904122333
Short name T703
Test name
Test status
Simulation time 22211801127 ps
CPU time 55.35 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 198716 kb
Host smart-20cf84f1-abd4-4aed-998e-288489027ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904122333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2904122333
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1422164994
Short name T485
Test name
Test status
Simulation time 59528077597 ps
CPU time 1338.6 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 05:07:10 PM PDT 24
Peak memory 198860 kb
Host smart-8e645cc1-78c0-4ede-b7dd-38dbe549f148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1422164994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1422164994
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3819895946
Short name T538
Test name
Test status
Simulation time 28937659 ps
CPU time 0.57 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:51 PM PDT 24
Peak memory 195172 kb
Host smart-9ab7bc5f-bc0b-48f8-a3c8-2a3ab80df623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819895946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3819895946
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1724074491
Short name T438
Test name
Test status
Simulation time 150467921 ps
CPU time 0.89 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 196944 kb
Host smart-e8819dc1-a2fd-41da-8805-60a3c409b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724074491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1724074491
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1711482959
Short name T195
Test name
Test status
Simulation time 2698895626 ps
CPU time 26.46 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 197328 kb
Host smart-73d40821-1273-455c-a06f-18474ef7589e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711482959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1711482959
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3485472609
Short name T131
Test name
Test status
Simulation time 67322524 ps
CPU time 0.78 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 196468 kb
Host smart-26ad0634-7bf6-4d36-9b5f-655cde070c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485472609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3485472609
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.534105077
Short name T153
Test name
Test status
Simulation time 90034232 ps
CPU time 1.21 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:45:04 PM PDT 24
Peak memory 196456 kb
Host smart-6ff376f2-0be3-4ec1-aaa2-f4aa1c5e1d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534105077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.534105077
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2856377850
Short name T659
Test name
Test status
Simulation time 36697634 ps
CPU time 1.55 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 197048 kb
Host smart-256941ee-1ff5-4222-a264-c04d4e760509
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856377850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2856377850
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2228649617
Short name T240
Test name
Test status
Simulation time 615193020 ps
CPU time 3.41 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 198672 kb
Host smart-5eef36f4-b76a-46d1-b7b2-e2f7de38213f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228649617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2228649617
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3137774472
Short name T573
Test name
Test status
Simulation time 55704082 ps
CPU time 1.22 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 196396 kb
Host smart-2872b6ba-7117-4efe-8e0a-1f647973b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137774472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3137774472
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.729533437
Short name T626
Test name
Test status
Simulation time 191837958 ps
CPU time 1.18 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 197860 kb
Host smart-84aef273-f563-4554-a565-71c110490ce8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729533437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.729533437
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.159752214
Short name T231
Test name
Test status
Simulation time 1728210341 ps
CPU time 4.46 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 196796 kb
Host smart-887b1b7d-687b-4121-8ea5-bf6b1c93472d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159752214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.159752214
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.853411843
Short name T13
Test name
Test status
Simulation time 65074080 ps
CPU time 1.08 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 196396 kb
Host smart-1b649851-e9fa-46c7-8ee1-2ab087b75418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853411843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.853411843
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1678138832
Short name T327
Test name
Test status
Simulation time 75089250 ps
CPU time 1.32 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 196108 kb
Host smart-020342c9-bce0-4835-ba37-b7954892e1dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678138832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1678138832
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1882694392
Short name T4
Test name
Test status
Simulation time 21706706056 ps
CPU time 211.29 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:48:33 PM PDT 24
Peak memory 198700 kb
Host smart-4c7b1af5-f157-4aa2-b728-aaec6eef74cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882694392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1882694392
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1545007260
Short name T426
Test name
Test status
Simulation time 23773959 ps
CPU time 0.62 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 194660 kb
Host smart-d67962d9-d983-4ffd-ba44-f9d030b0f04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545007260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1545007260
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1757647208
Short name T569
Test name
Test status
Simulation time 52118320 ps
CPU time 0.78 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 195868 kb
Host smart-6fee2dd6-8bb8-4ff4-9c1a-4b1ee62deba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757647208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1757647208
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.689188066
Short name T508
Test name
Test status
Simulation time 592852975 ps
CPU time 21.44 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 198516 kb
Host smart-56f1890f-8fde-4ffe-a1f8-36fdb8d27b29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689188066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.689188066
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2601133107
Short name T680
Test name
Test status
Simulation time 22058392 ps
CPU time 0.69 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 194968 kb
Host smart-59d0e357-afb6-47a5-9cf9-da0e979d1556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601133107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2601133107
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.262111096
Short name T547
Test name
Test status
Simulation time 47014792 ps
CPU time 1.28 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:54 PM PDT 24
Peak memory 197592 kb
Host smart-c0e6099a-ab52-4d9b-a436-2825e6b0fb43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262111096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.262111096
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4027458740
Short name T618
Test name
Test status
Simulation time 64168662 ps
CPU time 2.68 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 198624 kb
Host smart-7713b254-33a4-4de2-b37f-4846c0949197
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027458740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4027458740
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.456192412
Short name T645
Test name
Test status
Simulation time 178286196 ps
CPU time 2.71 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 196412 kb
Host smart-81a9cce3-68a2-44c0-a05b-079bd9723df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456192412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
456192412
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2323652449
Short name T173
Test name
Test status
Simulation time 39744351 ps
CPU time 1.14 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 197372 kb
Host smart-8e972b9b-450e-4300-a36c-7560c8b7b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323652449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2323652449
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2434934000
Short name T275
Test name
Test status
Simulation time 25937299 ps
CPU time 0.83 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 196008 kb
Host smart-2fb92315-ff9f-4c3f-98a4-b02ade015050
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434934000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2434934000
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3341514900
Short name T246
Test name
Test status
Simulation time 91101630 ps
CPU time 4.15 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 198440 kb
Host smart-ee128d28-0a0a-4116-8276-24c58469d7aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341514900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3341514900
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.199040051
Short name T68
Test name
Test status
Simulation time 44766449 ps
CPU time 1.22 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 197356 kb
Host smart-29920be8-c039-4bf6-a312-00bd6e1a4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199040051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.199040051
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2283851433
Short name T129
Test name
Test status
Simulation time 104318818 ps
CPU time 0.99 seconds
Started Aug 03 04:44:50 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 196392 kb
Host smart-6b6d293d-31ab-4d8c-a7d2-dcc41f67cc25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283851433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2283851433
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1932957318
Short name T434
Test name
Test status
Simulation time 4415860626 ps
CPU time 30.7 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:45:24 PM PDT 24
Peak memory 198704 kb
Host smart-f54dfd4c-5a95-44f9-8c06-f997708b516b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932957318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1932957318
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.343699605
Short name T709
Test name
Test status
Simulation time 12783710 ps
CPU time 0.59 seconds
Started Aug 03 04:44:55 PM PDT 24
Finished Aug 03 04:44:56 PM PDT 24
Peak memory 194460 kb
Host smart-81109543-f8b0-4404-aefb-162e8edca27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343699605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.343699605
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2274990896
Short name T121
Test name
Test status
Simulation time 98320783 ps
CPU time 0.74 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 196548 kb
Host smart-d9b8d336-1cd7-482b-b39f-ba9024c030f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274990896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2274990896
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.19180776
Short name T524
Test name
Test status
Simulation time 1192514717 ps
CPU time 24.16 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 196796 kb
Host smart-d64a778b-7ee6-4124-8c94-c3095c62ba8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stress
.19180776
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.512551651
Short name T336
Test name
Test status
Simulation time 45122588 ps
CPU time 0.76 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 196252 kb
Host smart-50f01260-5e83-414c-94e1-25e84710eb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512551651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.512551651
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2941624315
Short name T226
Test name
Test status
Simulation time 26769948 ps
CPU time 0.76 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 196140 kb
Host smart-04d5aa4c-9d81-4a82-aea8-06259e3e4f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941624315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2941624315
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3797797970
Short name T179
Test name
Test status
Simulation time 158164294 ps
CPU time 0.94 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 196556 kb
Host smart-a518d76f-90ca-4431-be82-98cfeda4960e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797797970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3797797970
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3070271582
Short name T91
Test name
Test status
Simulation time 109499272 ps
CPU time 0.92 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 194876 kb
Host smart-8b1c8650-e315-48e4-bb62-f6f3d37a4ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070271582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3070271582
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2478467502
Short name T149
Test name
Test status
Simulation time 82126804 ps
CPU time 0.79 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 195900 kb
Host smart-51e982b2-b8ab-4438-9367-a0ee23cffa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478467502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2478467502
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.347455243
Short name T506
Test name
Test status
Simulation time 14391995 ps
CPU time 0.67 seconds
Started Aug 03 04:44:51 PM PDT 24
Finished Aug 03 04:44:52 PM PDT 24
Peak memory 195484 kb
Host smart-69040836-444c-42d9-b72c-69ec5e7d9026
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347455243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.347455243
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3560118093
Short name T548
Test name
Test status
Simulation time 380843918 ps
CPU time 4.4 seconds
Started Aug 03 04:44:50 PM PDT 24
Finished Aug 03 04:44:54 PM PDT 24
Peak memory 198512 kb
Host smart-af2ccb11-2dd0-4425-9f4b-c88d5941bad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560118093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3560118093
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3265595027
Short name T309
Test name
Test status
Simulation time 268513596 ps
CPU time 1.32 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 196960 kb
Host smart-b360be5d-a207-45f4-a060-5b60c168ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265595027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3265595027
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1010644284
Short name T561
Test name
Test status
Simulation time 49521080 ps
CPU time 1.23 seconds
Started Aug 03 04:44:52 PM PDT 24
Finished Aug 03 04:44:53 PM PDT 24
Peak memory 196120 kb
Host smart-bc2b361b-e287-4d63-896f-06c817e03d75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010644284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1010644284
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4000914994
Short name T358
Test name
Test status
Simulation time 18241861910 ps
CPU time 78.23 seconds
Started Aug 03 04:44:56 PM PDT 24
Finished Aug 03 04:46:15 PM PDT 24
Peak memory 198744 kb
Host smart-f7b6ee6e-aa29-4795-b7b0-7dc43807726d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000914994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4000914994
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.995352222
Short name T220
Test name
Test status
Simulation time 51848907 ps
CPU time 0.56 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 194448 kb
Host smart-de83b1d3-5748-47f2-92f6-240e0fcd3106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995352222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.995352222
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.346963561
Short name T33
Test name
Test status
Simulation time 103580779 ps
CPU time 0.76 seconds
Started Aug 03 04:45:02 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 196344 kb
Host smart-dd5841b6-ccf4-4bba-9a96-8f7b5e51facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346963561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.346963561
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1584853458
Short name T630
Test name
Test status
Simulation time 736113057 ps
CPU time 9.8 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:45:08 PM PDT 24
Peak memory 197460 kb
Host smart-1a30569e-70eb-45c8-a6ed-2b7ce09afc78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584853458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1584853458
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2959361565
Short name T21
Test name
Test status
Simulation time 328595550 ps
CPU time 0.67 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 195096 kb
Host smart-57099989-edb9-4318-9ea6-b730cdc2e419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959361565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2959361565
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.25870419
Short name T446
Test name
Test status
Simulation time 583550570 ps
CPU time 1.09 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 197348 kb
Host smart-9067b252-7de3-4c8b-9915-99c29e3fd298
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.25870419
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.671818189
Short name T110
Test name
Test status
Simulation time 216276229 ps
CPU time 1.8 seconds
Started Aug 03 04:45:03 PM PDT 24
Finished Aug 03 04:45:05 PM PDT 24
Peak memory 197244 kb
Host smart-e4ea19d2-8923-411f-b146-e5e4d9bb971c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671818189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.671818189
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.770618430
Short name T487
Test name
Test status
Simulation time 349288675 ps
CPU time 1.96 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 196452 kb
Host smart-e976fb5c-51a3-42ed-8a70-314bc0d92d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770618430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
770618430
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4281370336
Short name T430
Test name
Test status
Simulation time 50440655 ps
CPU time 0.89 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 196756 kb
Host smart-40707338-ce1f-4f0e-b58e-5e3334166b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281370336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4281370336
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.820944016
Short name T307
Test name
Test status
Simulation time 123575019 ps
CPU time 0.96 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 197256 kb
Host smart-c5b223e2-9859-4694-8dc9-799fb961eff8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820944016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.820944016
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.471120310
Short name T577
Test name
Test status
Simulation time 250133476 ps
CPU time 4.32 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 198524 kb
Host smart-dba84300-63c7-4a3b-8aea-25a93ce5c167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471120310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.471120310
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2278319872
Short name T196
Test name
Test status
Simulation time 41165980 ps
CPU time 1.2 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 196856 kb
Host smart-429c7974-b57b-4c21-bd3a-7d03ce021ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278319872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2278319872
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2700489501
Short name T623
Test name
Test status
Simulation time 57683074 ps
CPU time 0.91 seconds
Started Aug 03 04:44:54 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 197464 kb
Host smart-fa649ecc-df4a-438f-95a9-b6b043ffe321
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700489501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2700489501
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3835502356
Short name T651
Test name
Test status
Simulation time 6246747337 ps
CPU time 91.76 seconds
Started Aug 03 04:45:00 PM PDT 24
Finished Aug 03 04:46:32 PM PDT 24
Peak memory 198784 kb
Host smart-bf92f5b2-b964-494b-8d96-23c274fa95f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835502356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3835502356
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1398246263
Short name T331
Test name
Test status
Simulation time 22892155 ps
CPU time 0.6 seconds
Started Aug 03 04:44:36 PM PDT 24
Finished Aug 03 04:44:37 PM PDT 24
Peak memory 194464 kb
Host smart-4cf6229f-c667-4bfa-ba59-d5510acc6464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398246263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1398246263
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2110893126
Short name T329
Test name
Test status
Simulation time 29303930 ps
CPU time 0.94 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 197744 kb
Host smart-fb52d479-95c0-44e1-9d06-b2b8d678b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110893126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2110893126
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3943322666
Short name T646
Test name
Test status
Simulation time 888117063 ps
CPU time 23.16 seconds
Started Aug 03 04:44:27 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 197632 kb
Host smart-d2021287-762e-4876-b6de-14abc476eb0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943322666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3943322666
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1157175864
Short name T377
Test name
Test status
Simulation time 109374507 ps
CPU time 0.77 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197120 kb
Host smart-34c6729d-ed42-4788-92e9-37fbe0095a82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157175864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1157175864
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4282837839
Short name T367
Test name
Test status
Simulation time 108168436 ps
CPU time 1.23 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 197344 kb
Host smart-81a2b0c6-5d9a-4b00-8195-f974432d8559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282837839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4282837839
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.855137714
Short name T130
Test name
Test status
Simulation time 102402725 ps
CPU time 1.2 seconds
Started Aug 03 04:44:26 PM PDT 24
Finished Aug 03 04:44:27 PM PDT 24
Peak memory 197168 kb
Host smart-8dbd7706-ffe5-4e87-8005-f07e1f6f2fe6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855137714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.855137714
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.423381667
Short name T239
Test name
Test status
Simulation time 309315812 ps
CPU time 1.25 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 196144 kb
Host smart-ee334871-e3fd-4a81-949a-386b8f676fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423381667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.423381667
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1908620481
Short name T69
Test name
Test status
Simulation time 25347444 ps
CPU time 0.74 seconds
Started Aug 03 04:44:30 PM PDT 24
Finished Aug 03 04:44:30 PM PDT 24
Peak memory 195912 kb
Host smart-fab076fa-4b30-4641-9027-7e14302afbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908620481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1908620481
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2163539670
Short name T354
Test name
Test status
Simulation time 86680264 ps
CPU time 1.05 seconds
Started Aug 03 04:44:25 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 196564 kb
Host smart-620215b1-76d5-4e53-8bb5-311ed99e04d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163539670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2163539670
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4276520905
Short name T636
Test name
Test status
Simulation time 47106443 ps
CPU time 2.26 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 198476 kb
Host smart-52b3c3a0-60d3-4918-8bd9-221a770e49e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276520905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4276520905
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.851921465
Short name T41
Test name
Test status
Simulation time 426631386 ps
CPU time 0.89 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 215260 kb
Host smart-c272b73f-a4ea-4e1a-bc70-5c7e465e1e14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851921465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.851921465
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.270590262
Short name T704
Test name
Test status
Simulation time 31727269 ps
CPU time 1.02 seconds
Started Aug 03 04:44:24 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 197008 kb
Host smart-7556a992-7059-4041-80ff-f44132393f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270590262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.270590262
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.215522189
Short name T169
Test name
Test status
Simulation time 263414287 ps
CPU time 1.31 seconds
Started Aug 03 04:44:27 PM PDT 24
Finished Aug 03 04:44:29 PM PDT 24
Peak memory 197416 kb
Host smart-2459304a-6d83-4569-be84-cbe848874d78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215522189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.215522189
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3615201077
Short name T14
Test name
Test status
Simulation time 23508694830 ps
CPU time 146.18 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:46:59 PM PDT 24
Peak memory 198760 kb
Host smart-1224d8ac-e8cd-4400-8535-89b1ccf5ccd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615201077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3615201077
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.144181163
Short name T584
Test name
Test status
Simulation time 11448741 ps
CPU time 0.58 seconds
Started Aug 03 04:45:06 PM PDT 24
Finished Aug 03 04:45:07 PM PDT 24
Peak memory 194484 kb
Host smart-e67b4cfc-5e35-45c7-a1f7-60ef8cbcb306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144181163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.144181163
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1679335372
Short name T325
Test name
Test status
Simulation time 107813247 ps
CPU time 0.76 seconds
Started Aug 03 04:45:07 PM PDT 24
Finished Aug 03 04:45:08 PM PDT 24
Peak memory 195900 kb
Host smart-e61ecb91-e4a7-487e-8a4d-e01d7cde7394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679335372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1679335372
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.800666846
Short name T171
Test name
Test status
Simulation time 909159042 ps
CPU time 25.87 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:45:24 PM PDT 24
Peak memory 197236 kb
Host smart-94a01da7-f625-47e2-9c93-74afc654a7f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800666846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.800666846
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2759682523
Short name T128
Test name
Test status
Simulation time 109248426 ps
CPU time 0.94 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 197116 kb
Host smart-f5fa62bb-1612-4476-9de6-04c3d7feaf1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759682523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2759682523
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1584306929
Short name T253
Test name
Test status
Simulation time 36861290 ps
CPU time 1.16 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 196644 kb
Host smart-cfd28115-5092-4ada-ac49-2bc3d7f29176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584306929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1584306929
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4181012341
Short name T383
Test name
Test status
Simulation time 25543345 ps
CPU time 1.15 seconds
Started Aug 03 04:45:03 PM PDT 24
Finished Aug 03 04:45:04 PM PDT 24
Peak memory 197684 kb
Host smart-273bd640-8c74-479c-b743-e6a069873f76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181012341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4181012341
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.361314033
Short name T163
Test name
Test status
Simulation time 46505990 ps
CPU time 1.49 seconds
Started Aug 03 04:45:00 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 196728 kb
Host smart-fcd9576c-28d5-4d64-8852-8a67ebf24674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361314033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
361314033
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1532910485
Short name T355
Test name
Test status
Simulation time 166748918 ps
CPU time 1.2 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 197592 kb
Host smart-dd073bc7-884e-481e-9a5f-84d9269e7815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532910485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1532910485
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3470884376
Short name T559
Test name
Test status
Simulation time 117024960 ps
CPU time 1.15 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 196424 kb
Host smart-09ae7e53-c5d4-41ce-85cf-16d746e9274c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470884376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3470884376
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1755278866
Short name T470
Test name
Test status
Simulation time 1101374697 ps
CPU time 6.73 seconds
Started Aug 03 04:45:05 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 198460 kb
Host smart-5a387afb-3e8d-48b5-a6ca-5702c349326f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755278866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1755278866
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2044227622
Short name T282
Test name
Test status
Simulation time 146243394 ps
CPU time 1.39 seconds
Started Aug 03 04:45:04 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 198616 kb
Host smart-4051c67f-67f8-4f1e-87bf-06f4566b2fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044227622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2044227622
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4158519786
Short name T16
Test name
Test status
Simulation time 45205145 ps
CPU time 1.32 seconds
Started Aug 03 04:45:01 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 196224 kb
Host smart-c9f42b91-d0f9-491d-b8b3-f12ca12987b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158519786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4158519786
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1283005738
Short name T167
Test name
Test status
Simulation time 1157149413 ps
CPU time 10.99 seconds
Started Aug 03 04:45:05 PM PDT 24
Finished Aug 03 04:45:16 PM PDT 24
Peak memory 198628 kb
Host smart-a10e313c-a662-47ce-afdf-addbdd0dd9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283005738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1283005738
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2162821676
Short name T350
Test name
Test status
Simulation time 16394719 ps
CPU time 0.58 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 194464 kb
Host smart-5b088783-17a1-49c7-9a9d-6bb7db747e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162821676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2162821676
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1616836135
Short name T210
Test name
Test status
Simulation time 171688839 ps
CPU time 0.78 seconds
Started Aug 03 04:45:00 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 195844 kb
Host smart-285cc7c4-cf9d-44c6-b14d-23c39c4f48ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616836135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1616836135
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.845305494
Short name T326
Test name
Test status
Simulation time 1244267246 ps
CPU time 15.46 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:45:13 PM PDT 24
Peak memory 198600 kb
Host smart-65a91a35-7726-455f-84d0-f189f732c616
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845305494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.845305494
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3815617572
Short name T168
Test name
Test status
Simulation time 72377905 ps
CPU time 0.66 seconds
Started Aug 03 04:45:09 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 195120 kb
Host smart-e4c53a33-3d7e-4bfd-a622-da3c8de59823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815617572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3815617572
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.918998977
Short name T688
Test name
Test status
Simulation time 411343886 ps
CPU time 1.01 seconds
Started Aug 03 04:44:57 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 197388 kb
Host smart-64b629cc-3d06-4af6-a20a-c0d379ca6c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918998977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.918998977
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2520502086
Short name T387
Test name
Test status
Simulation time 69012980 ps
CPU time 2.6 seconds
Started Aug 03 04:45:03 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 196880 kb
Host smart-c8a3b8b9-3681-420d-bb76-acf6a06f10ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520502086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2520502086
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.509405062
Short name T199
Test name
Test status
Simulation time 200614542 ps
CPU time 1.52 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 196484 kb
Host smart-337acce3-8e7b-46cd-a0eb-eb5b77b4a529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509405062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
509405062
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3614216219
Short name T227
Test name
Test status
Simulation time 65778906 ps
CPU time 0.64 seconds
Started Aug 03 04:45:00 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 195476 kb
Host smart-2758b1d9-1623-40ad-8eff-67cd79046420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614216219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3614216219
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2778317190
Short name T447
Test name
Test status
Simulation time 103442349 ps
CPU time 0.88 seconds
Started Aug 03 04:45:03 PM PDT 24
Finished Aug 03 04:45:04 PM PDT 24
Peak memory 196964 kb
Host smart-5b2d43a7-09b2-4118-a98c-366d25f28ad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778317190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2778317190
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2734504157
Short name T224
Test name
Test status
Simulation time 480352593 ps
CPU time 1.96 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 198580 kb
Host smart-c95d5801-71d9-4e99-a1f9-f60b52b5d63e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734504157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2734504157
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2585598573
Short name T664
Test name
Test status
Simulation time 27860480 ps
CPU time 0.78 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 195744 kb
Host smart-937024bf-917c-4f24-81cb-d13cf7284900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585598573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2585598573
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.673774217
Short name T386
Test name
Test status
Simulation time 169744884 ps
CPU time 0.96 seconds
Started Aug 03 04:44:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 196756 kb
Host smart-3d4fb565-e02d-4b46-822b-ff4a214664cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673774217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.673774217
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3816136308
Short name T650
Test name
Test status
Simulation time 10168045268 ps
CPU time 115.69 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:47:04 PM PDT 24
Peak memory 198764 kb
Host smart-877ba608-f768-40d6-8f38-9c6ed0fadec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816136308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3816136308
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2471019788
Short name T62
Test name
Test status
Simulation time 214321583592 ps
CPU time 1502.48 seconds
Started Aug 03 04:44:58 PM PDT 24
Finished Aug 03 05:10:00 PM PDT 24
Peak memory 198824 kb
Host smart-82df45bf-3134-444a-9fb8-c93e9c5468ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2471019788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2471019788
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.62056787
Short name T187
Test name
Test status
Simulation time 15407436 ps
CPU time 0.59 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 194624 kb
Host smart-467cc05b-a9d2-45fa-9a0a-629bbd4bff5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62056787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.62056787
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.255080356
Short name T353
Test name
Test status
Simulation time 22603303 ps
CPU time 0.74 seconds
Started Aug 03 04:45:09 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 195700 kb
Host smart-a04cd907-3817-49f1-804e-9950005cfdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255080356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.255080356
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3304564521
Short name T375
Test name
Test status
Simulation time 793215426 ps
CPU time 22.69 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:42 PM PDT 24
Peak memory 197016 kb
Host smart-72ba3020-01f3-4d9f-b5b7-dfc42ed7d32d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304564521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3304564521
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.889319992
Short name T206
Test name
Test status
Simulation time 54700683 ps
CPU time 0.89 seconds
Started Aug 03 04:45:09 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 197100 kb
Host smart-fee700c5-2972-4b25-ba2b-14e0f0728fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889319992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.889319992
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2167694899
Short name T443
Test name
Test status
Simulation time 55399893 ps
CPU time 1.02 seconds
Started Aug 03 04:45:04 PM PDT 24
Finished Aug 03 04:45:05 PM PDT 24
Peak memory 196456 kb
Host smart-6392e003-f062-47ef-b702-b69f79e02744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167694899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2167694899
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2871508467
Short name T371
Test name
Test status
Simulation time 97817868 ps
CPU time 1.22 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 197556 kb
Host smart-96d287b1-9d5c-47d1-8935-db3b1501a84b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871508467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2871508467
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.637893273
Short name T604
Test name
Test status
Simulation time 555123599 ps
CPU time 2.12 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 196364 kb
Host smart-9737da5c-23ee-4aab-af77-a38a9f0d07d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637893273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
637893273
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2384522007
Short name T668
Test name
Test status
Simulation time 63980463 ps
CPU time 0.89 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 196480 kb
Host smart-72e4d9ee-f3eb-440d-8214-9a563197d18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384522007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2384522007
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2047930678
Short name T244
Test name
Test status
Simulation time 243681214 ps
CPU time 1.01 seconds
Started Aug 03 04:45:07 PM PDT 24
Finished Aug 03 04:45:08 PM PDT 24
Peak memory 197284 kb
Host smart-95bcb9d0-3aee-44bd-94c5-e27463e94c1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047930678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2047930678
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1739599697
Short name T9
Test name
Test status
Simulation time 158921962 ps
CPU time 2.37 seconds
Started Aug 03 04:45:09 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 198596 kb
Host smart-26205d20-2292-41b2-a8ac-cd1347397e63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739599697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1739599697
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2196423881
Short name T500
Test name
Test status
Simulation time 238724442 ps
CPU time 1.21 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 197296 kb
Host smart-88a7ebaf-9dfd-473c-933b-7e3e8b812559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196423881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2196423881
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3437346883
Short name T19
Test name
Test status
Simulation time 24658174 ps
CPU time 0.76 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 195780 kb
Host smart-97f6497f-0d48-4eb7-9833-78993c2e0879
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437346883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3437346883
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.884329294
Short name T184
Test name
Test status
Simulation time 17458308279 ps
CPU time 59.42 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:46:35 PM PDT 24
Peak memory 198644 kb
Host smart-8812eb86-d65f-4ff8-a0f0-d0041eb6284e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884329294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.884329294
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1311789838
Short name T58
Test name
Test status
Simulation time 657748632266 ps
CPU time 1038.1 seconds
Started Aug 03 04:45:06 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 198876 kb
Host smart-39d1f189-0bd3-48b9-bfb8-59cbeed1cf74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1311789838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1311789838
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.83780431
Short name T720
Test name
Test status
Simulation time 44427826 ps
CPU time 0.55 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 194392 kb
Host smart-91de25a3-7394-4e17-a0e6-20a922b1ef83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83780431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.83780431
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1273093336
Short name T698
Test name
Test status
Simulation time 34134645 ps
CPU time 0.81 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 195748 kb
Host smart-392d7099-64f1-415f-87c9-e9b368d28f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273093336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1273093336
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2102304071
Short name T682
Test name
Test status
Simulation time 507711293 ps
CPU time 26.26 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 197556 kb
Host smart-9e8e2f44-4084-482e-b1a9-5b9e02a77f4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102304071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2102304071
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1343659625
Short name T639
Test name
Test status
Simulation time 102581266 ps
CPU time 1.03 seconds
Started Aug 03 04:45:23 PM PDT 24
Finished Aug 03 04:45:24 PM PDT 24
Peak memory 197148 kb
Host smart-13f990ce-57cf-49d2-ac9c-b830e4b7d15f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343659625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1343659625
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2534326633
Short name T406
Test name
Test status
Simulation time 300879665 ps
CPU time 1.41 seconds
Started Aug 03 04:45:04 PM PDT 24
Finished Aug 03 04:45:05 PM PDT 24
Peak memory 196668 kb
Host smart-b32ba5d2-893e-4d98-8d01-64442c821d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534326633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2534326633
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.4001537141
Short name T107
Test name
Test status
Simulation time 446786814 ps
CPU time 2.54 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:16 PM PDT 24
Peak memory 198708 kb
Host smart-063478be-fc89-45c6-bd08-38ff2b7780ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001537141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.4001537141
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.11065667
Short name T181
Test name
Test status
Simulation time 353302297 ps
CPU time 1.83 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 197300 kb
Host smart-738a2084-65ac-484e-ab6f-f2bf9ee77993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11065667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.11065667
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.527905317
Short name T529
Test name
Test status
Simulation time 146004273 ps
CPU time 0.87 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:09 PM PDT 24
Peak memory 196948 kb
Host smart-85770038-a655-4d39-b6dc-50f1b87aa044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527905317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.527905317
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.162851872
Short name T713
Test name
Test status
Simulation time 48834861 ps
CPU time 1.15 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 196592 kb
Host smart-3ddb0231-0963-476f-a246-67849ce14bb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162851872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.162851872
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3063481954
Short name T598
Test name
Test status
Simulation time 250110952 ps
CPU time 2.68 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 198532 kb
Host smart-579c0d42-c618-4a0e-a8ca-e394e8df6c8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063481954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3063481954
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3279732753
Short name T510
Test name
Test status
Simulation time 265999016 ps
CPU time 1.18 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:09 PM PDT 24
Peak memory 196340 kb
Host smart-1f4094bc-7173-48a9-aa8e-48aed0ae2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279732753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3279732753
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3887440951
Short name T208
Test name
Test status
Simulation time 86501052 ps
CPU time 0.78 seconds
Started Aug 03 04:45:06 PM PDT 24
Finished Aug 03 04:45:07 PM PDT 24
Peak memory 195700 kb
Host smart-18a11914-d1a5-44ae-a5e6-671610b7b930
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887440951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3887440951
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.370438072
Short name T230
Test name
Test status
Simulation time 44069894759 ps
CPU time 168.23 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:47:56 PM PDT 24
Peak memory 198716 kb
Host smart-5038ecab-ad07-44d6-be48-c5c35828f2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370438072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.370438072
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3311260796
Short name T43
Test name
Test status
Simulation time 21599980 ps
CPU time 0.6 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 194472 kb
Host smart-48892bde-5809-4022-968c-5b17d276ff5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311260796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3311260796
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1223808077
Short name T158
Test name
Test status
Simulation time 259549804 ps
CPU time 0.85 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:13 PM PDT 24
Peak memory 196472 kb
Host smart-a12f4f7c-261a-47aa-b729-962fdde35bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223808077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1223808077
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3068622388
Short name T160
Test name
Test status
Simulation time 317101070 ps
CPU time 5.69 seconds
Started Aug 03 04:45:15 PM PDT 24
Finished Aug 03 04:45:21 PM PDT 24
Peak memory 197316 kb
Host smart-45dee07c-330d-4a6a-a5d5-ce2343989daa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068622388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3068622388
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1418930450
Short name T495
Test name
Test status
Simulation time 220133362 ps
CPU time 0.8 seconds
Started Aug 03 04:45:07 PM PDT 24
Finished Aug 03 04:45:08 PM PDT 24
Peak memory 196584 kb
Host smart-eb3d4591-f68c-4624-a3df-21e381a5c7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418930450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1418930450
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2688285325
Short name T719
Test name
Test status
Simulation time 19328901 ps
CPU time 0.67 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 195560 kb
Host smart-d230be11-c2ca-4270-8821-597afde77083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688285325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2688285325
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.38613567
Short name T96
Test name
Test status
Simulation time 110866879 ps
CPU time 2.36 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 198700 kb
Host smart-c842142e-23f0-4257-93ce-b51724779b96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38613567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_intr_with_filter_rand_intr_event.38613567
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1152372055
Short name T583
Test name
Test status
Simulation time 45986058 ps
CPU time 1.58 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:09 PM PDT 24
Peak memory 197012 kb
Host smart-a36d4b0d-474c-4f3a-b0b0-f2d46922df47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152372055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1152372055
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4221371253
Short name T450
Test name
Test status
Simulation time 53788421 ps
CPU time 1.23 seconds
Started Aug 03 04:45:03 PM PDT 24
Finished Aug 03 04:45:04 PM PDT 24
Peak memory 197696 kb
Host smart-2197e531-7440-4885-8357-cc61dfd8f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221371253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4221371253
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4028515601
Short name T575
Test name
Test status
Simulation time 29180888 ps
CPU time 1 seconds
Started Aug 03 04:45:15 PM PDT 24
Finished Aug 03 04:45:16 PM PDT 24
Peak memory 197304 kb
Host smart-b47dfd16-3e7b-40c2-9a9a-84d16fdcb50b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028515601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4028515601
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1453996263
Short name T3
Test name
Test status
Simulation time 300570259 ps
CPU time 3.97 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 198512 kb
Host smart-813d0409-2f03-4893-9f2a-b84b2e2fa6e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453996263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1453996263
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3452146045
Short name T649
Test name
Test status
Simulation time 182657905 ps
CPU time 0.94 seconds
Started Aug 03 04:45:05 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 196896 kb
Host smart-e60738c1-e512-4508-b097-80db6db3e25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452146045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3452146045
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.994602746
Short name T293
Test name
Test status
Simulation time 48552138 ps
CPU time 1.25 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 197516 kb
Host smart-27348329-0f68-48b0-970b-0cc9e6d81a1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994602746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.994602746
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1867720170
Short name T609
Test name
Test status
Simulation time 35699159568 ps
CPU time 182.59 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:48:11 PM PDT 24
Peak memory 198908 kb
Host smart-71e9b302-200c-4b9a-8c16-6d57a6aa264b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867720170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1867720170
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.483587700
Short name T388
Test name
Test status
Simulation time 21414399 ps
CPU time 0.55 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 195112 kb
Host smart-5e7d27da-db1d-4dfe-ad5a-1d7e51fc0fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483587700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.483587700
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4126829791
Short name T322
Test name
Test status
Simulation time 21477947 ps
CPU time 0.66 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 194552 kb
Host smart-c4be0f14-3add-428a-bdbd-5dfb9dcf121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126829791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4126829791
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1069277568
Short name T436
Test name
Test status
Simulation time 418218056 ps
CPU time 22.22 seconds
Started Aug 03 04:45:21 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 197540 kb
Host smart-70786133-a10e-47d6-be35-2d237f50c687
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069277568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1069277568
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.81235808
Short name T301
Test name
Test status
Simulation time 103577206 ps
CPU time 0.65 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 195792 kb
Host smart-80b80990-990a-4eba-8b45-9513b195035d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81235808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.81235808
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2732247678
Short name T257
Test name
Test status
Simulation time 290227695 ps
CPU time 0.82 seconds
Started Aug 03 04:45:16 PM PDT 24
Finished Aug 03 04:45:17 PM PDT 24
Peak memory 196052 kb
Host smart-17d48905-c9b0-48b7-9faf-24504dcc3f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732247678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2732247678
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2135307041
Short name T291
Test name
Test status
Simulation time 372722591 ps
CPU time 2.96 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 198576 kb
Host smart-ace1affc-17cc-44ec-8c73-85227b841bd4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135307041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2135307041
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.978270180
Short name T270
Test name
Test status
Simulation time 240445277 ps
CPU time 2.05 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:21 PM PDT 24
Peak memory 198544 kb
Host smart-829821aa-48a2-490a-a850-6f14c5f626ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978270180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
978270180
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1376399423
Short name T490
Test name
Test status
Simulation time 32507906 ps
CPU time 0.93 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 197316 kb
Host smart-1f0ab8de-0789-42f2-aef2-3fd86c4b6be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376399423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1376399423
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2952449993
Short name T634
Test name
Test status
Simulation time 34901242 ps
CPU time 1.24 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 197524 kb
Host smart-264b20fa-09ee-4b2d-998a-edc48495dd44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952449993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2952449993
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1751501916
Short name T6
Test name
Test status
Simulation time 282338799 ps
CPU time 3.76 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 04:45:21 PM PDT 24
Peak memory 198536 kb
Host smart-f49735ef-0033-4e1d-9e3e-73497ae3b930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751501916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1751501916
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3708260059
Short name T248
Test name
Test status
Simulation time 71174769 ps
CPU time 1.07 seconds
Started Aug 03 04:45:08 PM PDT 24
Finished Aug 03 04:45:09 PM PDT 24
Peak memory 196932 kb
Host smart-f5502b76-5d7e-4356-8d06-4b2f2f9758b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708260059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3708260059
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1593145465
Short name T364
Test name
Test status
Simulation time 145402658 ps
CPU time 1.22 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 197244 kb
Host smart-8b60b64b-efff-4219-beee-3f2a9daeef1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593145465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1593145465
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3158111501
Short name T338
Test name
Test status
Simulation time 9070912193 ps
CPU time 51.57 seconds
Started Aug 03 04:45:16 PM PDT 24
Finished Aug 03 04:46:08 PM PDT 24
Peak memory 198760 kb
Host smart-c129a54e-0bf6-48b3-899d-a77917000263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158111501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3158111501
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1512810044
Short name T520
Test name
Test status
Simulation time 35837913683 ps
CPU time 517.15 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:53:55 PM PDT 24
Peak memory 198832 kb
Host smart-efa9ad84-c634-41f1-8e74-915d87fb3582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1512810044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1512810044
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1614567018
Short name T214
Test name
Test status
Simulation time 32532566 ps
CPU time 0.54 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 194416 kb
Host smart-33d4ddd2-546b-4c2f-bd06-816042432c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614567018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1614567018
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.334712695
Short name T654
Test name
Test status
Simulation time 24710126 ps
CPU time 0.77 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:30 PM PDT 24
Peak memory 195928 kb
Host smart-04c160cd-5417-47d3-bfd5-f500aa6e1425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334712695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.334712695
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1661766606
Short name T587
Test name
Test status
Simulation time 822318324 ps
CPU time 9.39 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:23 PM PDT 24
Peak memory 196088 kb
Host smart-898610da-c195-48d2-92ac-b186c9766637
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661766606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1661766606
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3470069088
Short name T138
Test name
Test status
Simulation time 55294679 ps
CPU time 0.89 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 196576 kb
Host smart-71b97a5e-48da-437e-bfb2-68bc01da1dbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470069088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3470069088
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3414891467
Short name T178
Test name
Test status
Simulation time 43332837 ps
CPU time 1.26 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 197452 kb
Host smart-9f2f5525-b4fc-48cb-9a8e-45c0c960c7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414891467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3414891467
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.489600240
Short name T162
Test name
Test status
Simulation time 66428664 ps
CPU time 0.96 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 196760 kb
Host smart-2f914dde-a2a8-4a4c-a78a-01fdb485fcf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489600240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.489600240
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1424441673
Short name T116
Test name
Test status
Simulation time 210366993 ps
CPU time 2.56 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:16 PM PDT 24
Peak memory 197580 kb
Host smart-ee9ac7ef-508e-4537-9197-43122c3f0f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424441673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1424441673
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2268474992
Short name T279
Test name
Test status
Simulation time 31938575 ps
CPU time 0.79 seconds
Started Aug 03 04:45:11 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 195916 kb
Host smart-5057daa1-3425-4f66-978e-a5819a2d125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268474992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2268474992
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3230879428
Short name T409
Test name
Test status
Simulation time 59938920 ps
CPU time 0.92 seconds
Started Aug 03 04:45:24 PM PDT 24
Finished Aug 03 04:45:25 PM PDT 24
Peak memory 196436 kb
Host smart-1acdce3c-7e49-4cb2-a0c7-d2df0d6592ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230879428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3230879428
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3546521229
Short name T460
Test name
Test status
Simulation time 1311614340 ps
CPU time 7.01 seconds
Started Aug 03 04:45:13 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 198396 kb
Host smart-643619b2-98d6-44a0-8c07-a48fc21f3f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546521229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3546521229
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3449088900
Short name T589
Test name
Test status
Simulation time 191454934 ps
CPU time 1.36 seconds
Started Aug 03 04:45:10 PM PDT 24
Finished Aug 03 04:45:11 PM PDT 24
Peak memory 197392 kb
Host smart-3ea1e78d-eb22-487b-b553-b57fa0bb91c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449088900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3449088900
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3368871867
Short name T528
Test name
Test status
Simulation time 113733112 ps
CPU time 1.08 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:13 PM PDT 24
Peak memory 196056 kb
Host smart-829aaf07-780e-42a8-9a69-db6655805a5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368871867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3368871867
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3412407679
Short name T320
Test name
Test status
Simulation time 34349935097 ps
CPU time 181.19 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:48:20 PM PDT 24
Peak memory 198732 kb
Host smart-ceaecf36-6e3d-47ab-9943-46ff95020e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412407679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3412407679
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3899573096
Short name T560
Test name
Test status
Simulation time 24328694527 ps
CPU time 541.54 seconds
Started Aug 03 04:45:21 PM PDT 24
Finished Aug 03 04:54:23 PM PDT 24
Peak memory 198840 kb
Host smart-bc05464c-7c79-408a-aee0-ad79653d2dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3899573096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3899573096
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1096072275
Short name T471
Test name
Test status
Simulation time 11784627 ps
CPU time 0.56 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 194476 kb
Host smart-caf411a4-4be9-4f19-a52e-4450703320dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096072275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1096072275
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2993194163
Short name T143
Test name
Test status
Simulation time 58362717 ps
CPU time 0.98 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 196252 kb
Host smart-c7809558-f68d-4623-96df-d6bca5c4269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993194163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2993194163
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3810073856
Short name T151
Test name
Test status
Simulation time 97683696 ps
CPU time 5.47 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 198564 kb
Host smart-aa2afdfb-18eb-4fbc-9706-adbfe65bd7f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810073856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3810073856
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3647832406
Short name T404
Test name
Test status
Simulation time 24220361 ps
CPU time 0.63 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 195016 kb
Host smart-ba672855-533d-4f62-b1d4-48eb7a2ef8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647832406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3647832406
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.207283014
Short name T429
Test name
Test status
Simulation time 154050518 ps
CPU time 1.29 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:16 PM PDT 24
Peak memory 197576 kb
Host smart-5e4ce11b-c5c5-4e03-8b13-00019e7d3cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207283014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.207283014
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2351001907
Short name T488
Test name
Test status
Simulation time 46217448 ps
CPU time 1.03 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 196496 kb
Host smart-b29ce51d-d335-4d28-a13d-12a2c5acc7e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351001907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2351001907
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1762281496
Short name T229
Test name
Test status
Simulation time 118345081 ps
CPU time 2.58 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:21 PM PDT 24
Peak memory 197580 kb
Host smart-fa6465ee-54c6-4e62-9a67-ee46e7a47906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762281496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1762281496
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2767817184
Short name T632
Test name
Test status
Simulation time 779436080 ps
CPU time 1.31 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 198532 kb
Host smart-8196c7e9-9355-4fea-b388-6db5a0e37211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767817184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2767817184
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4131995680
Short name T702
Test name
Test status
Simulation time 988338085 ps
CPU time 1.17 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:13 PM PDT 24
Peak memory 197044 kb
Host smart-7f94957b-1948-4e47-9577-d48abf84a9af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131995680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4131995680
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.372314166
Short name T399
Test name
Test status
Simulation time 1142589224 ps
CPU time 4.07 seconds
Started Aug 03 04:45:23 PM PDT 24
Finished Aug 03 04:45:28 PM PDT 24
Peak memory 198532 kb
Host smart-4239f098-aab5-4cc1-80dc-c3135595dddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372314166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.372314166
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3997832508
Short name T280
Test name
Test status
Simulation time 60311225 ps
CPU time 1.03 seconds
Started Aug 03 04:45:26 PM PDT 24
Finished Aug 03 04:45:27 PM PDT 24
Peak memory 196328 kb
Host smart-43269612-fc8e-40a9-879d-750d9d472242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997832508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3997832508
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3787247010
Short name T259
Test name
Test status
Simulation time 75648425 ps
CPU time 1.33 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 196796 kb
Host smart-94559b05-01a9-4069-a58e-eb6995f7621e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787247010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3787247010
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2923341940
Short name T633
Test name
Test status
Simulation time 5282564872 ps
CPU time 136.53 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:47:30 PM PDT 24
Peak memory 198772 kb
Host smart-f7c3093f-ea4f-4186-9c9d-2f6b8d34a878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923341940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2923341940
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2006583643
Short name T73
Test name
Test status
Simulation time 178378107467 ps
CPU time 996.07 seconds
Started Aug 03 04:45:32 PM PDT 24
Finished Aug 03 05:02:08 PM PDT 24
Peak memory 198852 kb
Host smart-2acede21-dbbd-4ada-8f77-007772b1c170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2006583643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2006583643
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1727499194
Short name T625
Test name
Test status
Simulation time 13628072 ps
CPU time 0.55 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:42 PM PDT 24
Peak memory 193224 kb
Host smart-6cf7b997-cbfb-4f33-85d5-df949601023e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727499194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1727499194
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.949456579
Short name T99
Test name
Test status
Simulation time 76412011 ps
CPU time 0.93 seconds
Started Aug 03 04:45:12 PM PDT 24
Finished Aug 03 04:45:13 PM PDT 24
Peak memory 196284 kb
Host smart-1eab47d1-f712-4b9a-8994-66267cc98635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949456579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.949456579
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.929796682
Short name T205
Test name
Test status
Simulation time 684625333 ps
CPU time 20.42 seconds
Started Aug 03 04:45:24 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 197152 kb
Host smart-2ee16524-94df-4977-bc56-45fc0fb21107
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929796682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.929796682
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.288659501
Short name T172
Test name
Test status
Simulation time 57933004 ps
CPU time 0.85 seconds
Started Aug 03 04:45:25 PM PDT 24
Finished Aug 03 04:45:26 PM PDT 24
Peak memory 197132 kb
Host smart-eb7ff688-50f0-49a0-9797-1a8528471991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288659501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.288659501
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.649841600
Short name T295
Test name
Test status
Simulation time 50236925 ps
CPU time 0.91 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 197380 kb
Host smart-2a02b867-3605-4e87-8b6a-5131514db046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649841600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.649841600
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3418320683
Short name T718
Test name
Test status
Simulation time 48207378 ps
CPU time 1.83 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 197060 kb
Host smart-8e060531-7124-46d9-9faa-859226e7b4f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418320683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3418320683
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.498564076
Short name T11
Test name
Test status
Simulation time 40845582 ps
CPU time 1.26 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 196560 kb
Host smart-031c0869-eb30-4028-a7d5-3f17259c7147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498564076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
498564076
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1727874262
Short name T65
Test name
Test status
Simulation time 37170992 ps
CPU time 0.66 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 195516 kb
Host smart-2fb5d3e3-f660-49ee-bb45-d9bc34a5389a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727874262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1727874262
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.457299044
Short name T612
Test name
Test status
Simulation time 20091455 ps
CPU time 0.61 seconds
Started Aug 03 04:45:14 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 194744 kb
Host smart-8948a0b8-f5c1-4805-aa1c-4f72262b89ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457299044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.457299044
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2434899387
Short name T462
Test name
Test status
Simulation time 2283381667 ps
CPU time 6.36 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 198672 kb
Host smart-ea520803-c954-4f85-97f0-74120e1580fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434899387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2434899387
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1654126451
Short name T17
Test name
Test status
Simulation time 174489126 ps
CPU time 1.27 seconds
Started Aug 03 04:45:25 PM PDT 24
Finished Aug 03 04:45:26 PM PDT 24
Peak memory 196092 kb
Host smart-db43d8b1-3c50-47f4-9959-3c9d313bf5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654126451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1654126451
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1101608898
Short name T544
Test name
Test status
Simulation time 153332533 ps
CPU time 1.12 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:19 PM PDT 24
Peak memory 196076 kb
Host smart-04e5cd61-69f7-4a18-b999-e8c95e0252c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101608898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1101608898
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2774277259
Short name T242
Test name
Test status
Simulation time 72014541784 ps
CPU time 111.62 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:47:27 PM PDT 24
Peak memory 198760 kb
Host smart-86813e34-3915-45c5-a2b8-cd98d80fc4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774277259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2774277259
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.522111529
Short name T166
Test name
Test status
Simulation time 14794720 ps
CPU time 0.59 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 194476 kb
Host smart-2db9d673-9cec-4bd4-a7bd-7ce10f3effa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522111529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.522111529
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3996547513
Short name T545
Test name
Test status
Simulation time 82168028 ps
CPU time 0.81 seconds
Started Aug 03 04:45:30 PM PDT 24
Finished Aug 03 04:45:31 PM PDT 24
Peak memory 195784 kb
Host smart-100f0730-ffe0-4380-aba4-d246401c7afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996547513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3996547513
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3970738981
Short name T599
Test name
Test status
Simulation time 488046333 ps
CPU time 24.68 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 197000 kb
Host smart-183efe04-adcd-4ede-b145-488099213250
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970738981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3970738981
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2871215031
Short name T552
Test name
Test status
Simulation time 68510365 ps
CPU time 0.94 seconds
Started Aug 03 04:45:27 PM PDT 24
Finished Aug 03 04:45:28 PM PDT 24
Peak memory 197048 kb
Host smart-3bc0e74e-2ad4-4b6a-b62d-61024fe61a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871215031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2871215031
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2977687957
Short name T363
Test name
Test status
Simulation time 75903670 ps
CPU time 0.93 seconds
Started Aug 03 04:45:25 PM PDT 24
Finished Aug 03 04:45:26 PM PDT 24
Peak memory 197028 kb
Host smart-ae272d25-5df4-4062-b6ac-633326355df3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977687957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2977687957
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1729566284
Short name T554
Test name
Test status
Simulation time 59240830 ps
CPU time 2.28 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 04:45:33 PM PDT 24
Peak memory 198632 kb
Host smart-2b28abe7-b7aa-444f-9ace-dec4ba079fcb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729566284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1729566284
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1968190030
Short name T395
Test name
Test status
Simulation time 266968338 ps
CPU time 3.2 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 197572 kb
Host smart-475cbcce-2331-4908-848c-6feeec6c81ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968190030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1968190030
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3163267390
Short name T550
Test name
Test status
Simulation time 52528866 ps
CPU time 1.13 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:45:37 PM PDT 24
Peak memory 196492 kb
Host smart-258e89b6-4a4f-4101-bf7e-7e26d0acd505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163267390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3163267390
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1005835519
Short name T519
Test name
Test status
Simulation time 59779475 ps
CPU time 1.11 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:31 PM PDT 24
Peak memory 196396 kb
Host smart-ff08c9b2-20d1-4514-b871-dba9e0ab58e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005835519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1005835519
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.403995998
Short name T572
Test name
Test status
Simulation time 116199500 ps
CPU time 5.49 seconds
Started Aug 03 04:45:30 PM PDT 24
Finished Aug 03 04:45:36 PM PDT 24
Peak memory 198572 kb
Host smart-9a72f6cf-3b6d-43a5-8b74-b274d08f2813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403995998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.403995998
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3761740508
Short name T236
Test name
Test status
Simulation time 65190130 ps
CPU time 0.94 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 197048 kb
Host smart-e3dda4b7-0b41-49b9-ab83-5a80de834d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761740508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3761740508
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4009544573
Short name T156
Test name
Test status
Simulation time 49919060 ps
CPU time 1.29 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 197016 kb
Host smart-3f49329c-e87e-4c7e-acd5-3559709edd67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009544573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4009544573
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1575679747
Short name T693
Test name
Test status
Simulation time 1250844694 ps
CPU time 35.09 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:46:08 PM PDT 24
Peak memory 198628 kb
Host smart-88fedd3c-8b05-4fc0-a092-66ae45c699df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575679747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1575679747
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2178458695
Short name T684
Test name
Test status
Simulation time 29432864 ps
CPU time 0.59 seconds
Started Aug 03 04:44:36 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 195396 kb
Host smart-d1360e37-3192-43fc-8159-0f853fe5bcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178458695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2178458695
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2911418396
Short name T241
Test name
Test status
Simulation time 73483822 ps
CPU time 0.83 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 196836 kb
Host smart-243ae8c7-69c3-4e70-8de5-22d089b2601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911418396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2911418396
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4209939424
Short name T424
Test name
Test status
Simulation time 909236324 ps
CPU time 7.22 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 197332 kb
Host smart-3fe98f58-6ed7-46aa-a4cc-1159925a9e62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209939424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.4209939424
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2669471243
Short name T341
Test name
Test status
Simulation time 76984934 ps
CPU time 0.79 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 196460 kb
Host smart-fb9c04d6-ae11-495f-8f4a-4ca9d6b9a9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669471243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2669471243
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3960639352
Short name T343
Test name
Test status
Simulation time 240340371 ps
CPU time 1.01 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197240 kb
Host smart-e18a3958-f413-426b-b1c2-7614cf3ba191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960639352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3960639352
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4212359557
Short name T665
Test name
Test status
Simulation time 269298370 ps
CPU time 2.32 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 198516 kb
Host smart-fdbc60d8-4274-477a-9c2b-5974803b0f79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212359557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4212359557
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.93259563
Short name T66
Test name
Test status
Simulation time 172066738 ps
CPU time 1.94 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 197740 kb
Host smart-97013899-d974-43b4-892a-ebefa5034132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93259563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.93259563
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3371049912
Short name T617
Test name
Test status
Simulation time 38253344 ps
CPU time 1 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196408 kb
Host smart-f63bf1ab-d910-41c9-a657-d72801622e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371049912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3371049912
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3325603400
Short name T578
Test name
Test status
Simulation time 56899195 ps
CPU time 0.86 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 195908 kb
Host smart-d19229f4-d604-4630-8ec5-64548ecf8748
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325603400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3325603400
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4020226362
Short name T292
Test name
Test status
Simulation time 70832689 ps
CPU time 3.14 seconds
Started Aug 03 04:44:36 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 198568 kb
Host smart-8072266e-5f3a-40df-b3d0-f8d237621d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020226362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4020226362
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.68033780
Short name T40
Test name
Test status
Simulation time 115925764 ps
CPU time 0.98 seconds
Started Aug 03 04:44:29 PM PDT 24
Finished Aug 03 04:44:30 PM PDT 24
Peak memory 215532 kb
Host smart-b0539cd4-acca-49ec-a226-a04978f69332
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68033780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.68033780
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2271319426
Short name T233
Test name
Test status
Simulation time 857462021 ps
CPU time 1.37 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 197244 kb
Host smart-b3417df0-8680-4538-9d87-9b9234e09bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271319426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2271319426
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1611491408
Short name T159
Test name
Test status
Simulation time 137848211 ps
CPU time 1.36 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197292 kb
Host smart-c0695fd2-9537-4aa1-9f97-a84bf45b7e1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611491408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1611491408
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.32457427
Short name T657
Test name
Test status
Simulation time 27860534825 ps
CPU time 128.32 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 198700 kb
Host smart-771538f2-b262-49d5-993e-438fa38236ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpi
o_stress_all.32457427
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1852892633
Short name T464
Test name
Test status
Simulation time 38019902556 ps
CPU time 325.47 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:49:59 PM PDT 24
Peak memory 198828 kb
Host smart-9d20d8e6-9836-44d9-93ea-14e3ece5bb71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1852892633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1852892633
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3721878912
Short name T629
Test name
Test status
Simulation time 15385332 ps
CPU time 0.56 seconds
Started Aug 03 04:45:28 PM PDT 24
Finished Aug 03 04:45:29 PM PDT 24
Peak memory 194476 kb
Host smart-18f558c5-b37b-4853-a426-055fa432bd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721878912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3721878912
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.241186555
Short name T504
Test name
Test status
Simulation time 25519305 ps
CPU time 0.88 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 04:45:32 PM PDT 24
Peak memory 195920 kb
Host smart-89214257-318e-47a8-8b31-2816de32561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241186555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.241186555
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3574615803
Short name T141
Test name
Test status
Simulation time 315180314 ps
CPU time 16.43 seconds
Started Aug 03 04:45:38 PM PDT 24
Finished Aug 03 04:45:54 PM PDT 24
Peak memory 197456 kb
Host smart-04d4a036-c4c8-45a7-999b-507d6ed1f043
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574615803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3574615803
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1103289889
Short name T681
Test name
Test status
Simulation time 76603695 ps
CPU time 0.99 seconds
Started Aug 03 04:45:28 PM PDT 24
Finished Aug 03 04:45:29 PM PDT 24
Peak memory 196928 kb
Host smart-eaff333d-899f-47a0-b886-11e7860cc61e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103289889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1103289889
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3622306401
Short name T647
Test name
Test status
Simulation time 34755087 ps
CPU time 0.8 seconds
Started Aug 03 04:45:23 PM PDT 24
Finished Aug 03 04:45:24 PM PDT 24
Peak memory 196552 kb
Host smart-6cd83210-f86e-4f57-b3d4-613256e0df7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622306401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3622306401
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.57773953
Short name T628
Test name
Test status
Simulation time 490524634 ps
CPU time 2.24 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:31 PM PDT 24
Peak memory 198516 kb
Host smart-6eb2478f-87d2-4f5a-9e87-47b988b86091
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57773953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.gpio_intr_with_filter_rand_intr_event.57773953
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.719131781
Short name T297
Test name
Test status
Simulation time 133283807 ps
CPU time 1.24 seconds
Started Aug 03 04:45:25 PM PDT 24
Finished Aug 03 04:45:26 PM PDT 24
Peak memory 196060 kb
Host smart-3ad035a6-0899-4010-82d3-370aaa23bb03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719131781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
719131781
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.402717666
Short name T408
Test name
Test status
Simulation time 141830172 ps
CPU time 1.08 seconds
Started Aug 03 04:45:30 PM PDT 24
Finished Aug 03 04:45:31 PM PDT 24
Peak memory 196640 kb
Host smart-faaab92d-b876-4d96-aea4-5f367c29ccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402717666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.402717666
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2606824725
Short name T126
Test name
Test status
Simulation time 36779163 ps
CPU time 1.07 seconds
Started Aug 03 04:45:25 PM PDT 24
Finished Aug 03 04:45:26 PM PDT 24
Peak memory 196636 kb
Host smart-9b5a24ad-ead0-467d-b242-efa82b03ec5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606824725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2606824725
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2989116020
Short name T711
Test name
Test status
Simulation time 197417914 ps
CPU time 4.43 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:45:37 PM PDT 24
Peak memory 198496 kb
Host smart-7534b0f4-e5e7-47fe-a35e-4cdc09d083bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989116020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2989116020
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2756184343
Short name T715
Test name
Test status
Simulation time 82092382 ps
CPU time 0.78 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:45:37 PM PDT 24
Peak memory 195824 kb
Host smart-eb93565e-00fa-4a05-902f-b7c7a4e5aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756184343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2756184343
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.74158599
Short name T315
Test name
Test status
Simulation time 280551945 ps
CPU time 0.76 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:45:34 PM PDT 24
Peak memory 195632 kb
Host smart-50eaa6e0-9551-41a6-8333-cdd9c5c17e35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74158599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.74158599
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2813789820
Short name T193
Test name
Test status
Simulation time 6770382975 ps
CPU time 50.55 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 04:46:22 PM PDT 24
Peak memory 198760 kb
Host smart-b1f7a4a2-5b24-4db6-bdc2-a25dc1bd45bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813789820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2813789820
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.444903377
Short name T277
Test name
Test status
Simulation time 274821989335 ps
CPU time 909.06 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 05:00:27 PM PDT 24
Peak memory 198804 kb
Host smart-20e35416-12d2-4ac5-ad6e-ba024d9797fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=444903377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.444903377
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3709805223
Short name T44
Test name
Test status
Simulation time 14252796 ps
CPU time 0.54 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 195168 kb
Host smart-be0bdc71-5bef-439d-848c-9355fec1d651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709805223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3709805223
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1140042508
Short name T465
Test name
Test status
Simulation time 344448921 ps
CPU time 0.81 seconds
Started Aug 03 04:45:43 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 195736 kb
Host smart-d23184b9-c028-462a-b73c-2866c6771507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140042508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1140042508
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1033718702
Short name T553
Test name
Test status
Simulation time 667423169 ps
CPU time 18.77 seconds
Started Aug 03 04:45:18 PM PDT 24
Finished Aug 03 04:45:37 PM PDT 24
Peak memory 196096 kb
Host smart-f5cbbb33-cf51-491a-b876-99f1cf271871
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033718702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1033718702
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3308648805
Short name T234
Test name
Test status
Simulation time 288478064 ps
CPU time 1.04 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 196888 kb
Host smart-89893d36-0ea9-48c2-b6f2-77c3258ff4d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308648805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3308648805
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3608970174
Short name T123
Test name
Test status
Simulation time 31923957 ps
CPU time 0.71 seconds
Started Aug 03 04:45:23 PM PDT 24
Finished Aug 03 04:45:23 PM PDT 24
Peak memory 194908 kb
Host smart-e123422f-a115-42cb-8ab7-a45560a6ff7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608970174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3608970174
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2067443418
Short name T481
Test name
Test status
Simulation time 1236066390 ps
CPU time 2.69 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 198580 kb
Host smart-5b44f531-9ac2-4085-9750-6c5734d763b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067443418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2067443418
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.469556819
Short name T374
Test name
Test status
Simulation time 95117145 ps
CPU time 1.99 seconds
Started Aug 03 04:45:28 PM PDT 24
Finished Aug 03 04:45:30 PM PDT 24
Peak memory 197388 kb
Host smart-26214a33-c654-4ca1-9406-655aad7d103d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469556819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
469556819
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2288485449
Short name T381
Test name
Test status
Simulation time 184794935 ps
CPU time 1.09 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:30 PM PDT 24
Peak memory 196484 kb
Host smart-fb846405-cc4f-4002-887a-8ca77edd4160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288485449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2288485449
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3556394892
Short name T389
Test name
Test status
Simulation time 32032814 ps
CPU time 0.78 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:30 PM PDT 24
Peak memory 195868 kb
Host smart-d7b4f07e-11b8-40a4-b7a1-a909a6b7b155
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556394892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3556394892
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3669193904
Short name T566
Test name
Test status
Simulation time 643506576 ps
CPU time 2.57 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:37 PM PDT 24
Peak memory 198552 kb
Host smart-5ef25724-bbf6-4d0b-a14b-055a4bf31933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669193904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3669193904
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1329368028
Short name T513
Test name
Test status
Simulation time 103924272 ps
CPU time 1.21 seconds
Started Aug 03 04:45:26 PM PDT 24
Finished Aug 03 04:45:27 PM PDT 24
Peak memory 196244 kb
Host smart-5716c59b-369c-48a6-b66c-b13b02134388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329368028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1329368028
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2023885838
Short name T180
Test name
Test status
Simulation time 48429798 ps
CPU time 0.95 seconds
Started Aug 03 04:45:27 PM PDT 24
Finished Aug 03 04:45:28 PM PDT 24
Peak memory 197520 kb
Host smart-2f09049c-5666-41a2-8e3a-44b5f48d76fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023885838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2023885838
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.571311735
Short name T92
Test name
Test status
Simulation time 3483202080 ps
CPU time 41.39 seconds
Started Aug 03 04:45:23 PM PDT 24
Finished Aug 03 04:46:04 PM PDT 24
Peak memory 198696 kb
Host smart-9c631bc6-3e4c-4c0b-9d3d-9eb1b467a5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571311735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.571311735
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2664566352
Short name T346
Test name
Test status
Simulation time 1336780780925 ps
CPU time 2593.5 seconds
Started Aug 03 04:45:19 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 199056 kb
Host smart-a35d164e-f3e9-428b-9c29-10ad2ff4014e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2664566352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2664566352
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1539745430
Short name T440
Test name
Test status
Simulation time 110748572 ps
CPU time 0.56 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:39 PM PDT 24
Peak memory 194692 kb
Host smart-37a2625e-744e-4d3b-954a-94e73e444493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539745430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1539745430
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3189171696
Short name T492
Test name
Test status
Simulation time 114946892 ps
CPU time 0.82 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:45:36 PM PDT 24
Peak memory 195900 kb
Host smart-d34f7cea-5677-4d86-b987-0b35387818f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189171696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3189171696
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.250164494
Short name T692
Test name
Test status
Simulation time 670092252 ps
CPU time 17.23 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 196020 kb
Host smart-24ea5929-7d4e-4ef2-9581-2b597c5ceea9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250164494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.250164494
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1415939317
Short name T255
Test name
Test status
Simulation time 32199088 ps
CPU time 0.69 seconds
Started Aug 03 04:45:32 PM PDT 24
Finished Aug 03 04:45:33 PM PDT 24
Peak memory 195076 kb
Host smart-a6901f3f-5298-4fd4-909b-edc7a0f82098
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415939317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1415939317
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.419693768
Short name T152
Test name
Test status
Simulation time 48440071 ps
CPU time 1.32 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 197556 kb
Host smart-c0fec9b8-fa9f-415d-b17d-781956368a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419693768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.419693768
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2010500782
Short name T448
Test name
Test status
Simulation time 356415737 ps
CPU time 3.71 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 198600 kb
Host smart-24c5e48a-9386-4857-8bb3-58329490ee1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010500782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2010500782
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4254380014
Short name T324
Test name
Test status
Simulation time 37316581 ps
CPU time 1.06 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 195916 kb
Host smart-31e958a9-806f-4026-9eb4-a3b839756ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254380014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4254380014
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.908829876
Short name T273
Test name
Test status
Simulation time 15356422 ps
CPU time 0.73 seconds
Started Aug 03 04:45:17 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 195812 kb
Host smart-7a338583-a6e0-42f8-bda9-ad50fe68dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908829876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.908829876
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.293902834
Short name T136
Test name
Test status
Simulation time 219908783 ps
CPU time 1.1 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 04:45:32 PM PDT 24
Peak memory 196568 kb
Host smart-f9900303-e4ce-4095-8f51-fd57c28603b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293902834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.293902834
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2005168528
Short name T631
Test name
Test status
Simulation time 1139786301 ps
CPU time 3.69 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 198564 kb
Host smart-2a50851a-0021-49dc-bfc8-98280d84aba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005168528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2005168528
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3523541605
Short name T267
Test name
Test status
Simulation time 40735368 ps
CPU time 1.01 seconds
Started Aug 03 04:45:27 PM PDT 24
Finished Aug 03 04:45:28 PM PDT 24
Peak memory 196992 kb
Host smart-e28adbda-ca23-4662-8714-ae9c0f77bef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523541605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3523541605
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1731546084
Short name T384
Test name
Test status
Simulation time 209583027 ps
CPU time 1.08 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 196124 kb
Host smart-371155a0-84b7-4702-b7ce-f4b15cac291a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731546084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1731546084
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.175134779
Short name T188
Test name
Test status
Simulation time 42900515553 ps
CPU time 142.67 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:48:09 PM PDT 24
Peak memory 198716 kb
Host smart-1f363867-2f4c-47f5-b68e-e86959ed92fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175134779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.175134779
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2792882854
Short name T503
Test name
Test status
Simulation time 22537700 ps
CPU time 0.6 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 194648 kb
Host smart-574af0f7-09d9-4eac-bbfc-8d1f88601311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792882854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2792882854
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1741655716
Short name T127
Test name
Test status
Simulation time 105618097 ps
CPU time 0.83 seconds
Started Aug 03 04:45:32 PM PDT 24
Finished Aug 03 04:45:33 PM PDT 24
Peak memory 195816 kb
Host smart-0d66daa1-c42c-4575-b2c4-bcc40b8472ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741655716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1741655716
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3939242320
Short name T391
Test name
Test status
Simulation time 677145431 ps
CPU time 16.98 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 197228 kb
Host smart-21c74716-bf0c-47cd-a256-a25d0ca9ec62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939242320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3939242320
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.138274580
Short name T370
Test name
Test status
Simulation time 75743324 ps
CPU time 0.99 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 198452 kb
Host smart-a7331d2a-a2d9-4ebb-bbef-478ff585dc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138274580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.138274580
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1496504347
Short name T380
Test name
Test status
Simulation time 396754587 ps
CPU time 1.45 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 197732 kb
Host smart-2237919d-29c3-4fb0-b095-3324a7144af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496504347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1496504347
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2194598602
Short name T622
Test name
Test status
Simulation time 306453123 ps
CPU time 3.05 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 198584 kb
Host smart-a4002814-9666-4800-b13c-1ae7df568210
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194598602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2194598602
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2246805265
Short name T716
Test name
Test status
Simulation time 169772524 ps
CPU time 2.07 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 197316 kb
Host smart-cfb843bd-47bc-47ab-843c-26113a9e5e5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246805265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2246805265
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2929002095
Short name T420
Test name
Test status
Simulation time 20416407 ps
CPU time 0.77 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 195852 kb
Host smart-5fc55a66-2d96-4f53-9793-4b59ebfef58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929002095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2929002095
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.705096313
Short name T423
Test name
Test status
Simulation time 120122573 ps
CPU time 1.14 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:46 PM PDT 24
Peak memory 197116 kb
Host smart-807826cd-cb19-4492-a0a1-4ec4c756bddf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705096313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.705096313
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.140436825
Short name T317
Test name
Test status
Simulation time 230413902 ps
CPU time 5.57 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 198608 kb
Host smart-89f93044-fe8c-4f3a-84e5-e492de0ec7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140436825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.140436825
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2812943527
Short name T265
Test name
Test status
Simulation time 83251378 ps
CPU time 0.97 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 195840 kb
Host smart-ce60b9cf-07c4-41a2-8f41-4d4f6df91d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812943527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2812943527
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2498962789
Short name T461
Test name
Test status
Simulation time 76308327 ps
CPU time 1.32 seconds
Started Aug 03 04:45:33 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 196304 kb
Host smart-535d0cf3-892c-45e0-8391-ce855fcb6dd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498962789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2498962789
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3984291502
Short name T313
Test name
Test status
Simulation time 11742304109 ps
CPU time 76.94 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:46:58 PM PDT 24
Peak memory 198692 kb
Host smart-f6fc4a4e-9e56-4eb5-a64c-b126945d62e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984291502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3984291502
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2851605321
Short name T335
Test name
Test status
Simulation time 171505977379 ps
CPU time 1507.72 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 05:10:39 PM PDT 24
Peak memory 198824 kb
Host smart-5b87096c-078f-4322-a5fb-5dc5aad51ee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2851605321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2851605321
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3875417662
Short name T217
Test name
Test status
Simulation time 20279324 ps
CPU time 0.59 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 194692 kb
Host smart-0849311c-6c80-4b8d-b310-c62faf08ecb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875417662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3875417662
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3158589880
Short name T219
Test name
Test status
Simulation time 108209971 ps
CPU time 0.9 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 196948 kb
Host smart-033a0578-a441-4ccd-aa28-a9ff9b32a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158589880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3158589880
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3778844
Short name T674
Test name
Test status
Simulation time 1445676022 ps
CPU time 6.87 seconds
Started Aug 03 04:45:43 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197516 kb
Host smart-9242d014-2f0e-4c84-9d32-5b22487bea12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stress.3778844
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.147668630
Short name T228
Test name
Test status
Simulation time 84067573 ps
CPU time 1.14 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:40 PM PDT 24
Peak memory 196872 kb
Host smart-ea7c5f19-bbbf-4e14-88b3-3625f155467a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147668630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.147668630
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2850647318
Short name T26
Test name
Test status
Simulation time 528199843 ps
CPU time 1.23 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 196772 kb
Host smart-253c3c2c-45aa-4716-897d-b89fb9dbf66d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850647318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2850647318
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2616819196
Short name T425
Test name
Test status
Simulation time 72068544 ps
CPU time 2.82 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 196884 kb
Host smart-78b72f63-ea55-46f2-b91d-7355b7006977
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616819196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2616819196
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.114243391
Short name T207
Test name
Test status
Simulation time 290244941 ps
CPU time 1.7 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 196588 kb
Host smart-1f2c0376-ea3d-4454-980f-37b2a431b97a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114243391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
114243391
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.449653257
Short name T249
Test name
Test status
Simulation time 482104985 ps
CPU time 1.18 seconds
Started Aug 03 04:45:31 PM PDT 24
Finished Aug 03 04:45:32 PM PDT 24
Peak memory 197528 kb
Host smart-4c3e6160-e2f7-4209-b061-79c901042920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449653257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.449653257
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2812216501
Short name T433
Test name
Test status
Simulation time 91175389 ps
CPU time 0.77 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:40 PM PDT 24
Peak memory 195912 kb
Host smart-98d5de60-ab7f-4401-a98b-c897ddfd304a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812216501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2812216501
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2235708750
Short name T594
Test name
Test status
Simulation time 138070584 ps
CPU time 2.59 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 198532 kb
Host smart-38617e3b-a2e4-41a2-8361-2fd5df29b5a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235708750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2235708750
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1031975159
Short name T551
Test name
Test status
Simulation time 211310774 ps
CPU time 1.03 seconds
Started Aug 03 04:45:29 PM PDT 24
Finished Aug 03 04:45:30 PM PDT 24
Peak memory 196364 kb
Host smart-badbdfec-d01c-46dc-8723-6eb520ecc369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031975159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1031975159
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3793341353
Short name T486
Test name
Test status
Simulation time 68755380 ps
CPU time 0.78 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 196464 kb
Host smart-cf084de7-8eb8-45e7-ba91-ea7229942acb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793341353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3793341353
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2065395872
Short name T250
Test name
Test status
Simulation time 11999331699 ps
CPU time 168.09 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:48:24 PM PDT 24
Peak memory 198760 kb
Host smart-c6b40ea4-e4ef-4fa8-99bc-36bdbb60d873
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065395872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2065395872
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2485405566
Short name T204
Test name
Test status
Simulation time 28848487 ps
CPU time 0.57 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:42 PM PDT 24
Peak memory 194464 kb
Host smart-bbf45a75-0589-4a1e-a056-3fce73d9a08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485405566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2485405566
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1909791521
Short name T586
Test name
Test status
Simulation time 19026095 ps
CPU time 0.76 seconds
Started Aug 03 04:45:43 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 194744 kb
Host smart-b2b465b0-d740-4e37-8878-e9d35956e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909791521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1909791521
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3537051267
Short name T556
Test name
Test status
Simulation time 3560955258 ps
CPU time 27.52 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:46:04 PM PDT 24
Peak memory 198664 kb
Host smart-5dcbcec6-077d-4193-bedb-8e78e3a16ccc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537051267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3537051267
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2684297499
Short name T482
Test name
Test status
Simulation time 47845234 ps
CPU time 0.8 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 197048 kb
Host smart-7a34ed66-6b75-410f-a3de-ee6150cef1b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684297499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2684297499
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1092956336
Short name T455
Test name
Test status
Simulation time 98215856 ps
CPU time 0.8 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 196792 kb
Host smart-6fdd979c-5498-447d-973d-3727d11eddee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092956336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1092956336
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3641660285
Short name T480
Test name
Test status
Simulation time 185644952 ps
CPU time 1.89 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:39 PM PDT 24
Peak memory 198604 kb
Host smart-b3a5d3ed-3085-4134-af13-87fbd8e4cbf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641660285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3641660285
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.988219825
Short name T394
Test name
Test status
Simulation time 74238602 ps
CPU time 1.52 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:46 PM PDT 24
Peak memory 196592 kb
Host smart-9212fa57-a536-47ff-9532-a9b7b3b554da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988219825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
988219825
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1648660370
Short name T378
Test name
Test status
Simulation time 18965541 ps
CPU time 0.66 seconds
Started Aug 03 04:45:27 PM PDT 24
Finished Aug 03 04:45:27 PM PDT 24
Peak memory 195488 kb
Host smart-97188467-b655-482d-bfd3-fb98b00f6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648660370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1648660370
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2452606409
Short name T119
Test name
Test status
Simulation time 35257333 ps
CPU time 1.48 seconds
Started Aug 03 04:45:36 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 197552 kb
Host smart-b801a44e-b351-48fe-ac34-4500d1d041cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452606409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2452606409
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3957852953
Short name T254
Test name
Test status
Simulation time 496035968 ps
CPU time 6.11 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 198560 kb
Host smart-81779634-a99f-4aed-ba03-aff258bcc412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957852953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3957852953
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.552572289
Short name T70
Test name
Test status
Simulation time 53523974 ps
CPU time 1.05 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 196128 kb
Host smart-3c75e037-d102-4d4e-bd03-a001c20c7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552572289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.552572289
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2867398214
Short name T491
Test name
Test status
Simulation time 321012002 ps
CPU time 1.26 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 196864 kb
Host smart-6a2ab585-8815-49a4-9b54-e568b1518a77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867398214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2867398214
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3357204265
Short name T185
Test name
Test status
Simulation time 2625646642 ps
CPU time 67.38 seconds
Started Aug 03 04:45:53 PM PDT 24
Finished Aug 03 04:47:01 PM PDT 24
Peak memory 198704 kb
Host smart-32424f10-455f-4991-8aff-8672ff3aff4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357204265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3357204265
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1485846860
Short name T192
Test name
Test status
Simulation time 12912238 ps
CPU time 0.57 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:49 PM PDT 24
Peak memory 195192 kb
Host smart-4581732b-7794-47d2-93fe-1f3f87bd3a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485846860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1485846860
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1682177371
Short name T419
Test name
Test status
Simulation time 27829169 ps
CPU time 0.91 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197140 kb
Host smart-b06fdb3a-0943-4b72-9ad0-4792a0908149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682177371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1682177371
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3267135432
Short name T345
Test name
Test status
Simulation time 644846155 ps
CPU time 17.05 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196808 kb
Host smart-1d76a70c-3d5e-4789-8a2a-ba6d24196579
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267135432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3267135432
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2052472059
Short name T175
Test name
Test status
Simulation time 27104861 ps
CPU time 0.73 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 195196 kb
Host smart-0dec4809-ac64-41cd-8ced-265e5e1b5aca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052472059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2052472059
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4003005733
Short name T189
Test name
Test status
Simulation time 166576417 ps
CPU time 1.39 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 197100 kb
Host smart-eb162331-0478-48d1-903d-67464a49b149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003005733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4003005733
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2536127248
Short name T133
Test name
Test status
Simulation time 125038250 ps
CPU time 1.46 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:46 PM PDT 24
Peak memory 196832 kb
Host smart-8b014256-08ff-47a8-8b4f-ecce5fed8f88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536127248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2536127248
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3397157755
Short name T516
Test name
Test status
Simulation time 41892555 ps
CPU time 1.35 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 196364 kb
Host smart-3f5355b3-a438-467a-884e-3e4405c3ba7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397157755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3397157755
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1656512278
Short name T558
Test name
Test status
Simulation time 26932344 ps
CPU time 0.92 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:46 PM PDT 24
Peak memory 196492 kb
Host smart-262b6eec-b48c-4f3f-89ef-fd196ccecc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656512278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1656512278
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2626790367
Short name T474
Test name
Test status
Simulation time 132236951 ps
CPU time 1.23 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 196480 kb
Host smart-5e7fbf4d-37df-4f42-9306-23a27e54f0a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626790367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2626790367
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2249964732
Short name T368
Test name
Test status
Simulation time 119985434 ps
CPU time 2.21 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 198488 kb
Host smart-e3a481c9-a8a5-4a83-9ba7-a5040d934544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249964732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2249964732
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4214546633
Short name T24
Test name
Test status
Simulation time 44541665 ps
CPU time 0.97 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196760 kb
Host smart-51d5e67d-669e-4a55-a0fd-da84f59e74d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214546633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4214546633
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3801497519
Short name T95
Test name
Test status
Simulation time 172086982 ps
CPU time 0.98 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 197004 kb
Host smart-74bfb4fa-d41f-490e-ab60-967de13cb56c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801497519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3801497519
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1720426267
Short name T290
Test name
Test status
Simulation time 14539949752 ps
CPU time 210.85 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:49:16 PM PDT 24
Peak memory 198756 kb
Host smart-b7ee0a47-bdac-4cb9-a8d7-ee54ee61a02b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720426267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1720426267
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.483867457
Short name T663
Test name
Test status
Simulation time 41184704 ps
CPU time 0.59 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 195124 kb
Host smart-7fc991e5-7034-4a50-a7cb-1aa1646bdd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483867457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.483867457
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.864354020
Short name T298
Test name
Test status
Simulation time 59912421 ps
CPU time 0.84 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 196724 kb
Host smart-9b944ec6-fb43-4d12-acd3-1de159e3675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864354020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.864354020
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2106899897
Short name T97
Test name
Test status
Simulation time 1321013610 ps
CPU time 12 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:46:03 PM PDT 24
Peak memory 197240 kb
Host smart-cf82d935-5b31-4358-b15d-be566e8392ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106899897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2106899897
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3780725168
Short name T683
Test name
Test status
Simulation time 75221146 ps
CPU time 1.12 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 197144 kb
Host smart-22746306-2497-494c-bc6d-9a6ad297127a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780725168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3780725168
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2466797075
Short name T106
Test name
Test status
Simulation time 49760367 ps
CPU time 0.72 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 194824 kb
Host smart-efdc8b11-7e02-4ace-99bd-4cd806e0714a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466797075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2466797075
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1220459697
Short name T453
Test name
Test status
Simulation time 192157239 ps
CPU time 4.18 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 198536 kb
Host smart-5b8f0f6c-b045-4965-b3a5-0b44081c0d73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220459697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1220459697
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3019099875
Short name T390
Test name
Test status
Simulation time 300880906 ps
CPU time 1.42 seconds
Started Aug 03 04:45:34 PM PDT 24
Finished Aug 03 04:45:35 PM PDT 24
Peak memory 196608 kb
Host smart-fed1d0e5-e566-449f-8037-9db78f6144ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019099875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3019099875
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.692149498
Short name T497
Test name
Test status
Simulation time 252772902 ps
CPU time 1.3 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 198616 kb
Host smart-ce85b8d7-1dbc-467f-83d8-f63e6666ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692149498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.692149498
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1325776762
Short name T431
Test name
Test status
Simulation time 66792226 ps
CPU time 1.2 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:49 PM PDT 24
Peak memory 197164 kb
Host smart-7e6b25b5-7d19-4adf-be12-afc447ad8824
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325776762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1325776762
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1423630880
Short name T154
Test name
Test status
Simulation time 136611853 ps
CPU time 6.22 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 198528 kb
Host smart-7599427f-5672-4c93-b169-550a7cefb7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423630880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1423630880
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.292260733
Short name T637
Test name
Test status
Simulation time 71174570 ps
CPU time 1.29 seconds
Started Aug 03 04:45:53 PM PDT 24
Finished Aug 03 04:45:54 PM PDT 24
Peak memory 197376 kb
Host smart-59e9ad18-38ca-44c7-9755-d46137c59ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292260733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.292260733
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1039413856
Short name T415
Test name
Test status
Simulation time 46898955 ps
CPU time 1.27 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 196808 kb
Host smart-1f61c0dd-5777-4951-b7d1-0bcd74157e24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039413856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1039413856
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1725925221
Short name T225
Test name
Test status
Simulation time 58392237283 ps
CPU time 156.57 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:48:17 PM PDT 24
Peak memory 198680 kb
Host smart-3af79fd9-4bb2-400b-9c20-fbc8f383ce48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725925221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1725925221
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2051702042
Short name T489
Test name
Test status
Simulation time 164993081848 ps
CPU time 306.01 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:50:49 PM PDT 24
Peak memory 198872 kb
Host smart-42a2bdc0-ae2d-4759-a8e6-99855d8fcbc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2051702042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2051702042
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2063360990
Short name T652
Test name
Test status
Simulation time 12808947 ps
CPU time 0.58 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 196208 kb
Host smart-87ba3bbf-e0bb-4272-8d40-95f73ddcab6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063360990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2063360990
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.637372240
Short name T124
Test name
Test status
Simulation time 65715358 ps
CPU time 0.81 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 195936 kb
Host smart-09a97541-c89a-47e4-ac11-cde76c3b87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637372240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.637372240
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3972932141
Short name T165
Test name
Test status
Simulation time 1531160265 ps
CPU time 26.2 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:46:09 PM PDT 24
Peak memory 196064 kb
Host smart-8169d38c-e2e4-416f-b050-08488b90e1d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972932141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3972932141
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1100185886
Short name T607
Test name
Test status
Simulation time 43976159 ps
CPU time 0.84 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 196532 kb
Host smart-278310b1-9a9d-445b-91e4-cd61e11eb193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100185886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1100185886
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2296705943
Short name T614
Test name
Test status
Simulation time 68343000 ps
CPU time 0.95 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 197232 kb
Host smart-8e57158c-443f-4ce3-a722-df2bcaabd978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296705943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2296705943
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1035034480
Short name T648
Test name
Test status
Simulation time 91862340 ps
CPU time 3.71 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 198712 kb
Host smart-c6b2300d-b5b7-45b3-9d3f-66b1b0d4d987
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035034480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1035034480
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.583409605
Short name T261
Test name
Test status
Simulation time 258049691 ps
CPU time 2.66 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:49 PM PDT 24
Peak memory 198496 kb
Host smart-7ecf4889-7e8b-40bd-aa29-d9eede667b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583409605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
583409605
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1510105097
Short name T373
Test name
Test status
Simulation time 55013403 ps
CPU time 1.08 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 196648 kb
Host smart-336a2467-d313-4e72-b3ab-7ef973f6a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510105097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1510105097
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2296678125
Short name T502
Test name
Test status
Simulation time 49688426 ps
CPU time 0.64 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 194716 kb
Host smart-a2629b52-4c9a-44f6-94d9-cbdfd71a17c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296678125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2296678125
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2536388452
Short name T7
Test name
Test status
Simulation time 1061964797 ps
CPU time 6.11 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 198500 kb
Host smart-607eb195-7c27-4ad0-85de-e2125911dbe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536388452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2536388452
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1215040474
Short name T627
Test name
Test status
Simulation time 743899265 ps
CPU time 1.13 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196136 kb
Host smart-74689a53-6812-448d-abf3-5e771500b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215040474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1215040474
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1915925723
Short name T316
Test name
Test status
Simulation time 111947555 ps
CPU time 0.99 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 196156 kb
Host smart-9b865ee1-8676-4281-8634-d35e5499047d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915925723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1915925723
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3985586958
Short name T285
Test name
Test status
Simulation time 18895173418 ps
CPU time 66.79 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:46:51 PM PDT 24
Peak memory 198732 kb
Host smart-4252cbf0-5a84-493e-8b9b-1b023c97aee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985586958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3985586958
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1745019680
Short name T514
Test name
Test status
Simulation time 109040508808 ps
CPU time 2369.24 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 199020 kb
Host smart-713d7ddb-7d41-4839-9811-bf514cebcb8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1745019680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1745019680
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3404816709
Short name T303
Test name
Test status
Simulation time 16417358 ps
CPU time 0.6 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 194616 kb
Host smart-0ff697d9-10b5-42a6-83df-beffee5f4ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404816709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3404816709
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3568700924
Short name T177
Test name
Test status
Simulation time 166895483 ps
CPU time 0.97 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 196988 kb
Host smart-b6f2835f-a373-48dc-9836-73b70c9cab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568700924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3568700924
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.931736825
Short name T287
Test name
Test status
Simulation time 2501046933 ps
CPU time 17.5 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 198048 kb
Host smart-ef8936db-fde7-411b-8d52-95f15b898681
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931736825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.931736825
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.743070386
Short name T656
Test name
Test status
Simulation time 41460705 ps
CPU time 0.82 seconds
Started Aug 03 04:45:43 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 196468 kb
Host smart-90bda294-ccf3-4dbc-8bf2-c08c1ad29855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743070386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.743070386
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4088285141
Short name T441
Test name
Test status
Simulation time 136968241 ps
CPU time 0.95 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 197304 kb
Host smart-a35f3e14-c37e-49ce-bc32-97e8019a60d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088285141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4088285141
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1523466420
Short name T600
Test name
Test status
Simulation time 143449479 ps
CPU time 2.93 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 198624 kb
Host smart-397fb2f5-8dd8-4593-84bd-4492c5209c4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523466420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1523466420
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.979545535
Short name T385
Test name
Test status
Simulation time 99875474 ps
CPU time 2.17 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:39 PM PDT 24
Peak memory 198648 kb
Host smart-19cc640b-8b39-4bff-864e-9c318c07c88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979545535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
979545535
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.777956572
Short name T300
Test name
Test status
Simulation time 31226467 ps
CPU time 0.71 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 195860 kb
Host smart-bd1a1a90-f02e-42c5-8cad-cf95261eb9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777956572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.777956572
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3476428736
Short name T655
Test name
Test status
Simulation time 66442215 ps
CPU time 0.87 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 196016 kb
Host smart-6e933947-83ed-434d-a537-7b65e8c6e047
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476428736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3476428736
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2812781331
Short name T296
Test name
Test status
Simulation time 62284415 ps
CPU time 2.88 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 198512 kb
Host smart-207c3ba6-03a2-4f8c-b59c-de2b9093ae81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812781331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2812781331
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4051643771
Short name T700
Test name
Test status
Simulation time 120657402 ps
CPU time 0.78 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 195856 kb
Host smart-ab7217b9-3c7e-45f3-9ba9-cb77a714e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051643771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4051643771
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.380360607
Short name T705
Test name
Test status
Simulation time 77635266 ps
CPU time 1.25 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 196108 kb
Host smart-b7c8749e-d78b-4c51-b188-96c93b9de97d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380360607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.380360607
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.409023478
Short name T624
Test name
Test status
Simulation time 57182804728 ps
CPU time 175.31 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:48:40 PM PDT 24
Peak memory 198732 kb
Host smart-01196a92-fb84-4c57-98c6-25f2d50ffa25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409023478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.409023478
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.661619362
Short name T459
Test name
Test status
Simulation time 203408438402 ps
CPU time 1536.3 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 05:11:22 PM PDT 24
Peak memory 198740 kb
Host smart-ab541bb2-a25e-4c45-a2ca-3819aab1540f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=661619362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.661619362
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2767292150
Short name T344
Test name
Test status
Simulation time 49897778 ps
CPU time 0.53 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 193208 kb
Host smart-fd5bd8b5-7586-4714-9217-7a3a41974c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767292150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2767292150
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.665201976
Short name T349
Test name
Test status
Simulation time 18481129 ps
CPU time 0.69 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 195296 kb
Host smart-a0b69f41-a2cd-45b9-bc6e-6b3dfa42ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665201976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.665201976
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3322263330
Short name T579
Test name
Test status
Simulation time 363563612 ps
CPU time 3.04 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196444 kb
Host smart-0548999a-c754-4788-8e4f-116e59352e61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322263330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3322263330
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2365907967
Short name T414
Test name
Test status
Simulation time 221302708 ps
CPU time 0.93 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 196900 kb
Host smart-9047ccfc-208d-4177-bc51-8f269cf48a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365907967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2365907967
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2828715869
Short name T641
Test name
Test status
Simulation time 422315158 ps
CPU time 1.51 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196364 kb
Host smart-1fc4278a-0a1c-44d1-9655-b59e8a6ad82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828715869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2828715869
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.843959427
Short name T714
Test name
Test status
Simulation time 70612534 ps
CPU time 2.73 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 198600 kb
Host smart-df39a0d2-7a14-4664-b174-e85076c44595
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843959427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.843959427
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2509503573
Short name T139
Test name
Test status
Simulation time 117473156 ps
CPU time 3.58 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 198632 kb
Host smart-464c37d3-8881-49d2-8bad-a87d342ae224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509503573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2509503573
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3292020586
Short name T526
Test name
Test status
Simulation time 28769468 ps
CPU time 1.04 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 196396 kb
Host smart-071ec006-fbc1-445c-8dd8-1e39638051cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292020586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3292020586
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1453810111
Short name T534
Test name
Test status
Simulation time 366451136 ps
CPU time 1.42 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 197632 kb
Host smart-25329b29-295b-4d50-ae50-a73ef44fb3cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453810111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1453810111
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3479536486
Short name T707
Test name
Test status
Simulation time 502640915 ps
CPU time 5.12 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:37 PM PDT 24
Peak memory 198556 kb
Host smart-83edf1ef-78c3-4a30-a6e1-536d3e88fa1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479536486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3479536486
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3701287953
Short name T54
Test name
Test status
Simulation time 84144351 ps
CPU time 1 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 215584 kb
Host smart-220aeb1b-d2f9-4d99-8886-1e489c024771
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701287953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3701287953
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1034620463
Short name T176
Test name
Test status
Simulation time 493024005 ps
CPU time 1.35 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 197352 kb
Host smart-ba7472f9-8b09-497e-bac2-a2c6f2b03f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034620463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1034620463
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.579529695
Short name T597
Test name
Test status
Simulation time 48461860 ps
CPU time 1.13 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 196892 kb
Host smart-02cae0e8-2740-4673-aa7e-c3ca117efebf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579529695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.579529695
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.903440649
Short name T469
Test name
Test status
Simulation time 6279093334 ps
CPU time 47.75 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 198784 kb
Host smart-e034e4a0-a597-45c6-b00f-50d5952f9fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903440649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.903440649
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1935444152
Short name T56
Test name
Test status
Simulation time 67405887874 ps
CPU time 1471.87 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 198864 kb
Host smart-d702ef88-c6c9-4fcc-9fff-62c8ce0e8f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1935444152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1935444152
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2060318587
Short name T98
Test name
Test status
Simulation time 16448798 ps
CPU time 0.62 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 194852 kb
Host smart-36a4fdad-4e68-4516-9e60-cba0a2d7b74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060318587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2060318587
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1959591721
Short name T135
Test name
Test status
Simulation time 29264311 ps
CPU time 0.7 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 194640 kb
Host smart-fabe0377-5e9f-4208-9e0a-f9095819e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959591721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1959591721
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2629255957
Short name T32
Test name
Test status
Simulation time 1000783021 ps
CPU time 11.64 seconds
Started Aug 03 04:45:53 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 198568 kb
Host smart-1680fa92-4672-44b4-83f5-31ba565fa6b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629255957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2629255957
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.151519751
Short name T498
Test name
Test status
Simulation time 554984995 ps
CPU time 0.94 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 197800 kb
Host smart-d65741e8-2ec7-4452-8ec9-3a16f9d9908d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151519751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.151519751
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3696492701
Short name T620
Test name
Test status
Simulation time 47247003 ps
CPU time 0.93 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 197376 kb
Host smart-e8d540ff-c5b8-4bd9-866a-61409cb99932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696492701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3696492701
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3796270184
Short name T15
Test name
Test status
Simulation time 98909788 ps
CPU time 1.01 seconds
Started Aug 03 04:45:39 PM PDT 24
Finished Aug 03 04:45:40 PM PDT 24
Peak memory 196588 kb
Host smart-47dbf682-a9f2-4810-9262-99afbc2258d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796270184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3796270184
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2337039329
Short name T539
Test name
Test status
Simulation time 337768168 ps
CPU time 2.59 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:54 PM PDT 24
Peak memory 197716 kb
Host smart-dd52e611-c553-4554-9872-9b4e07410ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337039329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2337039329
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.230136595
Short name T22
Test name
Test status
Simulation time 22096250 ps
CPU time 0.9 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 197248 kb
Host smart-78561093-cb22-4a43-9abf-02bf6dd30f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230136595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.230136595
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2738602507
Short name T382
Test name
Test status
Simulation time 38862185 ps
CPU time 1.23 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 197364 kb
Host smart-9f17d4f2-5386-4f38-85df-8465153fccd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738602507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2738602507
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1545558398
Short name T695
Test name
Test status
Simulation time 1364793046 ps
CPU time 4.15 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 198296 kb
Host smart-984ef892-3a69-4c6b-b057-a1a5287d02e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545558398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1545558398
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.301109976
Short name T444
Test name
Test status
Simulation time 51743587 ps
CPU time 0.97 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:49 PM PDT 24
Peak memory 196924 kb
Host smart-aaf0970d-6024-4e2d-a61e-3340bc2ad429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301109976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.301109976
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2142988329
Short name T304
Test name
Test status
Simulation time 215544800 ps
CPU time 1.32 seconds
Started Aug 03 04:45:38 PM PDT 24
Finished Aug 03 04:45:40 PM PDT 24
Peak memory 197312 kb
Host smart-55050dfa-4bae-413b-8bef-e51ae381985d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142988329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2142988329
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.588116104
Short name T352
Test name
Test status
Simulation time 10900466648 ps
CPU time 46.27 seconds
Started Aug 03 04:45:38 PM PDT 24
Finished Aug 03 04:46:25 PM PDT 24
Peak memory 198816 kb
Host smart-6a61430d-70f3-41e2-a048-942134e394ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588116104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.588116104
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2925746135
Short name T34
Test name
Test status
Simulation time 122049232804 ps
CPU time 753.47 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 198852 kb
Host smart-eda773ed-d55e-44e1-ac3e-5565276b0d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2925746135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2925746135
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1324951037
Short name T161
Test name
Test status
Simulation time 11070922 ps
CPU time 0.57 seconds
Started Aug 03 04:46:03 PM PDT 24
Finished Aug 03 04:46:03 PM PDT 24
Peak memory 194608 kb
Host smart-234c5109-f96f-4725-a45a-9198b618316c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324951037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1324951037
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.234010505
Short name T509
Test name
Test status
Simulation time 132062104 ps
CPU time 0.85 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 196500 kb
Host smart-19167826-7ac1-4b8c-88c5-3f4cd366e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234010505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.234010505
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2233314710
Short name T30
Test name
Test status
Simulation time 746626108 ps
CPU time 23.61 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:46:09 PM PDT 24
Peak memory 197548 kb
Host smart-e50d008a-1390-4f1f-8d7e-bdebcd03b41d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233314710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2233314710
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1800532736
Short name T332
Test name
Test status
Simulation time 64424198 ps
CPU time 0.93 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197488 kb
Host smart-767d6d4b-53f5-4ba3-9c50-040c015697c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800532736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1800532736
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1668644693
Short name T111
Test name
Test status
Simulation time 24834556 ps
CPU time 0.88 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 196072 kb
Host smart-13e0e0d4-c6bc-4d4f-accc-7a0f5e69e4d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668644693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1668644693
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4184085015
Short name T413
Test name
Test status
Simulation time 211275877 ps
CPU time 3.21 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 197088 kb
Host smart-df2eb458-2a24-4483-9ad3-447735a4aa9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184085015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4184085015
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.677030661
Short name T643
Test name
Test status
Simulation time 65151191 ps
CPU time 1.42 seconds
Started Aug 03 04:45:40 PM PDT 24
Finished Aug 03 04:45:41 PM PDT 24
Peak memory 198604 kb
Host smart-8f583f29-e431-413e-b30f-875ab4b6afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677030661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.677030661
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3299701703
Short name T144
Test name
Test status
Simulation time 35244684 ps
CPU time 0.79 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 195968 kb
Host smart-7233edaa-7ca1-4f0e-a846-31b162dd4e06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299701703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3299701703
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1985539831
Short name T348
Test name
Test status
Simulation time 1029850447 ps
CPU time 2.5 seconds
Started Aug 03 04:45:41 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 198576 kb
Host smart-4a8add2a-577b-494d-84cb-cda6be04af0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985539831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1985539831
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3303418043
Short name T581
Test name
Test status
Simulation time 197641143 ps
CPU time 0.67 seconds
Started Aug 03 04:45:35 PM PDT 24
Finished Aug 03 04:45:36 PM PDT 24
Peak memory 194724 kb
Host smart-10dc0f36-b15e-41d5-af34-56cc308e4924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303418043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3303418043
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1904867312
Short name T507
Test name
Test status
Simulation time 70612778 ps
CPU time 1.19 seconds
Started Aug 03 04:45:37 PM PDT 24
Finished Aug 03 04:45:39 PM PDT 24
Peak memory 197112 kb
Host smart-2bbf7a30-2819-43dc-a7dc-d3b28c6d5109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904867312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1904867312
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1300937385
Short name T405
Test name
Test status
Simulation time 3453169330 ps
CPU time 50.32 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:46:48 PM PDT 24
Peak memory 192376 kb
Host smart-d7c1e5dd-89ad-43cd-b84d-3003ef24644a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300937385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1300937385
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.247454316
Short name T679
Test name
Test status
Simulation time 13539542 ps
CPU time 0.62 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 194640 kb
Host smart-a8af24c5-612c-4ed2-afbe-6240df166b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247454316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.247454316
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2698417603
Short name T613
Test name
Test status
Simulation time 164372107 ps
CPU time 0.87 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 197716 kb
Host smart-f4576e8a-a3e0-4309-b1df-b339c0ab6853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698417603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2698417603
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2607624271
Short name T522
Test name
Test status
Simulation time 205192203 ps
CPU time 5.7 seconds
Started Aug 03 04:47:01 PM PDT 24
Finished Aug 03 04:47:07 PM PDT 24
Peak memory 196976 kb
Host smart-af029e1d-ead9-495a-93b0-17e28efe18a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607624271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2607624271
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1605834719
Short name T222
Test name
Test status
Simulation time 36752242 ps
CPU time 0.79 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 196484 kb
Host smart-8c0c2c46-b1ee-4f0f-9487-91fef4269a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605834719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1605834719
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2056503954
Short name T271
Test name
Test status
Simulation time 153495423 ps
CPU time 0.9 seconds
Started Aug 03 04:47:01 PM PDT 24
Finished Aug 03 04:47:02 PM PDT 24
Peak memory 196252 kb
Host smart-b8d699c0-8b83-439a-8af8-2a5f5e02258d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056503954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2056503954
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1764578699
Short name T145
Test name
Test status
Simulation time 76205504 ps
CPU time 1 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196856 kb
Host smart-56a95680-674f-4e0a-8db7-39100569f170
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764578699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1764578699
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.959270910
Short name T200
Test name
Test status
Simulation time 1319197681 ps
CPU time 3.31 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 197684 kb
Host smart-92077d11-6906-4a8f-9105-bcbcd4a9989a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959270910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
959270910
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.965951417
Short name T576
Test name
Test status
Simulation time 54958908 ps
CPU time 1.04 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:49 PM PDT 24
Peak memory 196360 kb
Host smart-78dfc6e2-e631-4b20-8556-9e2908a3e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965951417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.965951417
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1369694539
Short name T527
Test name
Test status
Simulation time 24548903 ps
CPU time 0.89 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:45 PM PDT 24
Peak memory 196380 kb
Host smart-aa053bee-a02e-437a-9dcc-71ad34f77433
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369694539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1369694539
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2450175539
Short name T658
Test name
Test status
Simulation time 91080717 ps
CPU time 3.95 seconds
Started Aug 03 04:45:44 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 198560 kb
Host smart-fd99ef60-369b-4465-ad0a-d1d300d3f812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450175539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2450175539
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.543413467
Short name T191
Test name
Test status
Simulation time 68221506 ps
CPU time 1.19 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 196328 kb
Host smart-842cc0eb-f62f-4315-8925-85aafba41fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543413467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.543413467
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3293326258
Short name T710
Test name
Test status
Simulation time 271278906 ps
CPU time 1.17 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 196184 kb
Host smart-8d2365fc-61bc-43bd-8220-7e04d8182479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293326258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3293326258
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1953568159
Short name T428
Test name
Test status
Simulation time 2104169069 ps
CPU time 41.45 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:46:38 PM PDT 24
Peak memory 198604 kb
Host smart-d8fea0b1-f97f-4c3b-b1b1-0299f0ef85bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953568159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1953568159
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.745200569
Short name T418
Test name
Test status
Simulation time 14004130 ps
CPU time 0.6 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:46 PM PDT 24
Peak memory 195400 kb
Host smart-03784a15-424c-420c-a771-084119b3e42b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745200569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.745200569
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1136791903
Short name T308
Test name
Test status
Simulation time 170053695 ps
CPU time 0.85 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 196460 kb
Host smart-454d0dde-9e5d-400c-86a3-b92aeac1117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136791903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1136791903
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2374295945
Short name T306
Test name
Test status
Simulation time 840300654 ps
CPU time 15.01 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:46:04 PM PDT 24
Peak memory 197352 kb
Host smart-f1e6c77f-e3ee-44d6-882a-aab54cec9d8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374295945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2374295945
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3234685276
Short name T417
Test name
Test status
Simulation time 270246245 ps
CPU time 0.77 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 195036 kb
Host smart-14b3ad0a-6753-4d9e-b295-778eae2ce619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234685276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3234685276
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.847854544
Short name T323
Test name
Test status
Simulation time 40902740 ps
CPU time 1.07 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 197392 kb
Host smart-84804f0a-9839-4c58-8fcd-392e4900d5b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847854544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.847854544
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3662909481
Short name T687
Test name
Test status
Simulation time 32397725 ps
CPU time 1.33 seconds
Started Aug 03 04:46:03 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 196800 kb
Host smart-0e86b688-6d25-4421-9488-f9cbd9a014d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662909481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3662909481
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2927519822
Short name T150
Test name
Test status
Simulation time 416654872 ps
CPU time 2.14 seconds
Started Aug 03 04:45:45 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 196396 kb
Host smart-208e0304-e879-48c0-a62b-923d36a4eff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927519822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2927519822
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3789493045
Short name T565
Test name
Test status
Simulation time 56260661 ps
CPU time 1.23 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 197464 kb
Host smart-f1a181de-0d1e-471c-8c52-0ab604ff5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789493045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3789493045
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1426975818
Short name T245
Test name
Test status
Simulation time 30334994 ps
CPU time 1.03 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 196588 kb
Host smart-5de4d7c9-b39f-4a1d-9d28-fea995afac46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426975818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1426975818
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2593575100
Short name T118
Test name
Test status
Simulation time 407750658 ps
CPU time 1.98 seconds
Started Aug 03 04:45:48 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 198524 kb
Host smart-eeb9c4b7-d351-402c-a949-9ff520a0c13b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593575100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2593575100
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3132491264
Short name T468
Test name
Test status
Simulation time 75444879 ps
CPU time 1.3 seconds
Started Aug 03 04:45:42 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 197252 kb
Host smart-dec0d450-d8a4-4fe8-a18e-f0dd02a4b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132491264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3132491264
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3126566082
Short name T644
Test name
Test status
Simulation time 80021371 ps
CPU time 1.23 seconds
Started Aug 03 04:45:46 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 197284 kb
Host smart-217f5dac-ba73-4762-a33f-1ec57eef25a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126566082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3126566082
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2275348598
Short name T673
Test name
Test status
Simulation time 8982582980 ps
CPU time 63.66 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:47:07 PM PDT 24
Peak memory 198760 kb
Host smart-891ae041-1613-4471-9c17-3eebfbaf4f4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275348598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2275348598
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3332592820
Short name T113
Test name
Test status
Simulation time 31214059392 ps
CPU time 425.09 seconds
Started Aug 03 04:46:52 PM PDT 24
Finished Aug 03 04:53:58 PM PDT 24
Peak memory 197848 kb
Host smart-5ad69964-758b-4e2a-8942-8e647c583721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3332592820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3332592820
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.831498466
Short name T458
Test name
Test status
Simulation time 11971053 ps
CPU time 0.59 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 194308 kb
Host smart-5957b325-d980-46e3-91b2-d531ff7562ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831498466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.831498466
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2229386987
Short name T445
Test name
Test status
Simulation time 55544926 ps
CPU time 0.65 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 195280 kb
Host smart-d67d505e-da85-4789-959d-17b0523dbfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229386987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2229386987
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3012912065
Short name T603
Test name
Test status
Simulation time 5230592756 ps
CPU time 27.23 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:46:17 PM PDT 24
Peak memory 198176 kb
Host smart-1f3dc795-35e2-4783-b7a0-14f979f17ec3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012912065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3012912065
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.207676764
Short name T706
Test name
Test status
Simulation time 38981807 ps
CPU time 0.77 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 195292 kb
Host smart-05df68f2-83e9-43e2-9eb3-f467b6fb85f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207676764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.207676764
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3029902915
Short name T194
Test name
Test status
Simulation time 135245942 ps
CPU time 0.85 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196660 kb
Host smart-ce3b93e2-c901-4073-a499-756ea95d8469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029902915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3029902915
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1993124352
Short name T511
Test name
Test status
Simulation time 70864448 ps
CPU time 1.48 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 197072 kb
Host smart-e9b09141-b712-46e2-9dc4-7fee9c511ed6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993124352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1993124352
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3705695919
Short name T582
Test name
Test status
Simulation time 71591288 ps
CPU time 1.03 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196052 kb
Host smart-0bc60830-4721-42f7-8c84-01aa4371f32d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705695919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3705695919
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4191066650
Short name T272
Test name
Test status
Simulation time 103300555 ps
CPU time 1.15 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 196020 kb
Host smart-b85b8904-14f3-4723-bdba-963809e6b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191066650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4191066650
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.733396367
Short name T662
Test name
Test status
Simulation time 97722557 ps
CPU time 0.89 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:55 PM PDT 24
Peak memory 196512 kb
Host smart-f1a28051-c53c-4966-b414-c02f4941e39a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733396367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.733396367
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2187259789
Short name T640
Test name
Test status
Simulation time 335886658 ps
CPU time 5.12 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:46:01 PM PDT 24
Peak memory 198500 kb
Host smart-1f4f9175-9cb4-4476-9aa4-dd9312cecad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187259789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2187259789
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2243003537
Short name T117
Test name
Test status
Simulation time 231934359 ps
CPU time 1.03 seconds
Started Aug 03 04:45:43 PM PDT 24
Finished Aug 03 04:45:44 PM PDT 24
Peak memory 196316 kb
Host smart-76826990-6720-48fc-a851-fa92ca28212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243003537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2243003537
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2631371089
Short name T591
Test name
Test status
Simulation time 64475692 ps
CPU time 1.15 seconds
Started Aug 03 04:45:47 PM PDT 24
Finished Aug 03 04:45:48 PM PDT 24
Peak memory 197068 kb
Host smart-15f5a1c5-c3cc-45b3-9e77-e65b34de7432
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631371089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2631371089
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2868411893
Short name T299
Test name
Test status
Simulation time 6085692095 ps
CPU time 33.15 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:46:24 PM PDT 24
Peak memory 198724 kb
Host smart-1e93165a-fdbe-41ca-ba30-81a396307f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868411893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2868411893
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2404178869
Short name T57
Test name
Test status
Simulation time 296936291276 ps
CPU time 2657.46 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 05:30:10 PM PDT 24
Peak memory 198812 kb
Host smart-c4b8b03b-e7bf-41df-bb4d-d294eb4ba837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2404178869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2404178869
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1579658212
Short name T496
Test name
Test status
Simulation time 37048033 ps
CPU time 0.57 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 194488 kb
Host smart-f6dbfd5c-6f45-48c2-aea5-747ecc3a91e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579658212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1579658212
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1915968392
Short name T493
Test name
Test status
Simulation time 46252778 ps
CPU time 0.97 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 196392 kb
Host smart-7ecb9cea-d1d7-4971-bd5a-79661570aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915968392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1915968392
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3601024561
Short name T314
Test name
Test status
Simulation time 72784724 ps
CPU time 3.28 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:45:54 PM PDT 24
Peak memory 197284 kb
Host smart-ce88e91a-5f92-4822-a7b4-b9d3b4a5d51c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601024561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3601024561
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3670310610
Short name T661
Test name
Test status
Simulation time 311776289 ps
CPU time 0.97 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197200 kb
Host smart-e9caed3a-3f21-41b5-99b0-2b927e859a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670310610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3670310610
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1882106566
Short name T555
Test name
Test status
Simulation time 434005954 ps
CPU time 1.25 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 197120 kb
Host smart-23b43663-eafb-4be9-87aa-13e548522194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882106566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1882106566
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3752128347
Short name T190
Test name
Test status
Simulation time 91355357 ps
CPU time 3.73 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:06 PM PDT 24
Peak memory 198300 kb
Host smart-82725a91-1963-4e15-94bd-ecf17d6f6356
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752128347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3752128347
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.794834579
Short name T540
Test name
Test status
Simulation time 164827882 ps
CPU time 3.1 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 197852 kb
Host smart-25b80889-25be-4d17-a88a-a5ad5a795263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794834579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
794834579
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2642559586
Short name T258
Test name
Test status
Simulation time 166581088 ps
CPU time 1.04 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 196208 kb
Host smart-301a55ea-e990-4f68-ab3c-31d1296c50fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642559586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2642559586
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3717988308
Short name T638
Test name
Test status
Simulation time 22901322 ps
CPU time 0.73 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:03 PM PDT 24
Peak memory 194752 kb
Host smart-0ae80bcd-bf1d-4a8d-85e7-0b66bead89ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717988308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3717988308
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.279671228
Short name T356
Test name
Test status
Simulation time 524408216 ps
CPU time 1.83 seconds
Started Aug 03 04:45:58 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 198532 kb
Host smart-ef4e06cd-7f48-4706-8be5-095c413c2f64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279671228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.279671228
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1848126398
Short name T157
Test name
Test status
Simulation time 274188485 ps
CPU time 1.19 seconds
Started Aug 03 04:45:52 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 196332 kb
Host smart-f8b9e2a6-7b34-4cc4-b529-9d7d48f18de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848126398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1848126398
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2027212510
Short name T174
Test name
Test status
Simulation time 48185166 ps
CPU time 0.98 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 195764 kb
Host smart-6024a1ed-801d-4a58-b0cf-5f9b4cb59f8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027212510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2027212510
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2877873099
Short name T294
Test name
Test status
Simulation time 9668077475 ps
CPU time 47.27 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:49 PM PDT 24
Peak memory 198396 kb
Host smart-38547a25-4a93-401f-82d1-5fdc90563540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877873099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2877873099
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.167025747
Short name T379
Test name
Test status
Simulation time 24797375625 ps
CPU time 311.39 seconds
Started Aug 03 04:45:53 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 198836 kb
Host smart-ec17ea9f-e207-4d01-b31f-bccb11a55937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=167025747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.167025747
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3445904694
Short name T398
Test name
Test status
Simulation time 14066495 ps
CPU time 0.63 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 195072 kb
Host smart-d699b80e-fa11-4e08-af9a-ae023a6c61e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445904694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3445904694
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.243844233
Short name T472
Test name
Test status
Simulation time 62118174 ps
CPU time 0.65 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 195312 kb
Host smart-586e9d0b-998e-4961-9d5f-573f9632f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243844233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.243844233
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1833140884
Short name T717
Test name
Test status
Simulation time 438246873 ps
CPU time 9.35 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 197524 kb
Host smart-48f5fb02-df14-4478-981f-f2b762e93444
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833140884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1833140884
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4121763508
Short name T432
Test name
Test status
Simulation time 63823594 ps
CPU time 1.03 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197160 kb
Host smart-acdb9b0c-917e-41f3-a191-b98f3f28ee0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121763508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4121763508
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.758224942
Short name T439
Test name
Test status
Simulation time 43627438 ps
CPU time 0.71 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196636 kb
Host smart-ccfe1c58-5966-4e92-82ad-7e2312387166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758224942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.758224942
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.880876196
Short name T256
Test name
Test status
Simulation time 164353883 ps
CPU time 1.7 seconds
Started Aug 03 04:45:54 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 197280 kb
Host smart-109c0e52-47d6-449d-bc6e-17709c7af073
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880876196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.880876196
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2075484237
Short name T213
Test name
Test status
Simulation time 797865613 ps
CPU time 2.64 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:52 PM PDT 24
Peak memory 197700 kb
Host smart-9eb4e3bc-857b-4c37-9378-38a48f2eb88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075484237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2075484237
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2421669675
Short name T109
Test name
Test status
Simulation time 41923251 ps
CPU time 0.9 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197436 kb
Host smart-d2f2c346-befe-4337-8a58-9467a7eeaa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421669675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2421669675
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4127513674
Short name T531
Test name
Test status
Simulation time 35475578 ps
CPU time 0.71 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 194780 kb
Host smart-d6a88507-9f4e-46cd-b1fb-b98dd96a5e56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127513674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4127513674
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3191444427
Short name T2
Test name
Test status
Simulation time 3487737090 ps
CPU time 3.48 seconds
Started Aug 03 04:47:02 PM PDT 24
Finished Aug 03 04:47:06 PM PDT 24
Peak memory 198404 kb
Host smart-8b50d726-a75a-427d-bfa9-3daf79615dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191444427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3191444427
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3202991065
Short name T699
Test name
Test status
Simulation time 108953213 ps
CPU time 0.94 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 197668 kb
Host smart-a7625b6a-8fb1-4b9a-a677-3d95557e5538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202991065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3202991065
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2676665066
Short name T590
Test name
Test status
Simulation time 33895889 ps
CPU time 0.8 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 195884 kb
Host smart-fcff65f0-60c1-4e3d-b409-da4a9d3f2d3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676665066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2676665066
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2158916183
Short name T610
Test name
Test status
Simulation time 71152189037 ps
CPU time 70.02 seconds
Started Aug 03 04:45:51 PM PDT 24
Finished Aug 03 04:47:01 PM PDT 24
Peak memory 198716 kb
Host smart-3a85f150-7bd4-4223-b5d2-5f950592dcaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158916183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2158916183
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1891200780
Short name T483
Test name
Test status
Simulation time 31563029 ps
CPU time 0.59 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 195176 kb
Host smart-61496e60-a052-44e8-8dd4-40a23d5d7ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891200780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1891200780
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.851539497
Short name T283
Test name
Test status
Simulation time 111879798 ps
CPU time 0.93 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 197056 kb
Host smart-edceae33-7888-4438-8dab-fd0e92c39d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851539497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.851539497
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.471312963
Short name T28
Test name
Test status
Simulation time 68538803 ps
CPU time 4 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 196776 kb
Host smart-90c4a207-1d30-46c1-a6de-224b1e63bf7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471312963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.471312963
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3699595982
Short name T596
Test name
Test status
Simulation time 82549162 ps
CPU time 0.81 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:01 PM PDT 24
Peak memory 196516 kb
Host smart-7e21bfb2-cb10-47ee-b794-0b4fdf86d32f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699595982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3699595982
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2895079117
Short name T223
Test name
Test status
Simulation time 191077547 ps
CPU time 0.93 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196984 kb
Host smart-907da091-4642-4341-94c9-34a8b7037ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895079117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2895079117
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2421310105
Short name T215
Test name
Test status
Simulation time 75064045 ps
CPU time 1.94 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 198692 kb
Host smart-e56101a1-ea0f-47bd-94d4-86c93e4f9501
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421310105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2421310105
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2766461460
Short name T238
Test name
Test status
Simulation time 88465368 ps
CPU time 1.81 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:04 PM PDT 24
Peak memory 196524 kb
Host smart-96681e70-ca0d-48d7-9785-a45fea9681f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766461460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2766461460
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2169156488
Short name T262
Test name
Test status
Simulation time 28789848 ps
CPU time 1.07 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196584 kb
Host smart-a1eb41be-8eca-4751-b1a0-17124a671f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169156488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2169156488
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1192414862
Short name T499
Test name
Test status
Simulation time 48635452 ps
CPU time 0.68 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:03 PM PDT 24
Peak memory 194908 kb
Host smart-1ce7145b-ca3a-4f03-bbcc-7bb9ea21feb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192414862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1192414862
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1985101889
Short name T451
Test name
Test status
Simulation time 511451843 ps
CPU time 2.37 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 198524 kb
Host smart-0bd2be81-997f-4c8e-8f5e-8d653d0c3a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985101889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1985101889
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3387579980
Short name T369
Test name
Test status
Simulation time 64539193 ps
CPU time 1.22 seconds
Started Aug 03 04:45:49 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196956 kb
Host smart-f8c53891-5b9a-4a09-aa25-c157b163e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387579980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3387579980
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1451398128
Short name T512
Test name
Test status
Simulation time 59349918 ps
CPU time 0.82 seconds
Started Aug 03 04:45:50 PM PDT 24
Finished Aug 03 04:45:51 PM PDT 24
Peak memory 196616 kb
Host smart-9e725d29-c7ad-4ea2-a712-a8d9eab63a6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451398128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1451398128
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3436301603
Short name T403
Test name
Test status
Simulation time 2359959408 ps
CPU time 36.56 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:46:34 PM PDT 24
Peak memory 198616 kb
Host smart-78132958-a4a1-4774-895f-59e4277a0f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436301603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3436301603
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2502531755
Short name T276
Test name
Test status
Simulation time 13906378 ps
CPU time 0.57 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 194436 kb
Host smart-0ec83bae-387e-41d8-be4c-0c1156755bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502531755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2502531755
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2002558962
Short name T278
Test name
Test status
Simulation time 22425207 ps
CPU time 0.83 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 195728 kb
Host smart-49541a41-4868-4216-afdd-79c4304ae301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002558962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2002558962
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3475890809
Short name T400
Test name
Test status
Simulation time 216471101 ps
CPU time 11.3 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:12 PM PDT 24
Peak memory 196060 kb
Host smart-fb0394ed-98d1-4829-8a44-81d0da5f6f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475890809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3475890809
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.900591541
Short name T427
Test name
Test status
Simulation time 225113637 ps
CPU time 0.83 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 196452 kb
Host smart-9d910e58-d4f2-459a-9ea9-af19bc43b0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900591541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.900591541
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.67018376
Short name T318
Test name
Test status
Simulation time 173055360 ps
CPU time 0.98 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 197132 kb
Host smart-0700f6e0-763a-4538-ad3f-50bc916f60b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67018376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.67018376
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4186543053
Short name T305
Test name
Test status
Simulation time 303780269 ps
CPU time 3.14 seconds
Started Aug 03 04:45:58 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 198600 kb
Host smart-beb8e70f-da72-44e4-8a9e-b4830afc3465
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186543053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4186543053
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2397594093
Short name T475
Test name
Test status
Simulation time 149754473 ps
CPU time 2.25 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 197612 kb
Host smart-3dc1d93b-9768-4f4c-a347-e8982e4a778e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397594093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2397594093
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3821620426
Short name T211
Test name
Test status
Simulation time 74567894 ps
CPU time 1.32 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 198608 kb
Host smart-04ae847e-2693-43f2-bc41-583a8a3424ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821620426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3821620426
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2512911255
Short name T476
Test name
Test status
Simulation time 25617674 ps
CPU time 1.11 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 196536 kb
Host smart-3ed7ac68-789b-40bc-b47c-48d326d1c9ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512911255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2512911255
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1083827214
Short name T466
Test name
Test status
Simulation time 234596192 ps
CPU time 2.44 seconds
Started Aug 03 04:46:03 PM PDT 24
Finished Aug 03 04:46:06 PM PDT 24
Peak memory 198524 kb
Host smart-a27b8e11-d644-42b3-a982-919859b35a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083827214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1083827214
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1876635695
Short name T392
Test name
Test status
Simulation time 171386401 ps
CPU time 0.89 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:05 PM PDT 24
Peak memory 195912 kb
Host smart-a5972175-675d-48d9-8be9-238a26c05120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876635695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1876635695
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2988760152
Short name T393
Test name
Test status
Simulation time 202215275 ps
CPU time 0.98 seconds
Started Aug 03 04:46:55 PM PDT 24
Finished Aug 03 04:46:57 PM PDT 24
Peak memory 195276 kb
Host smart-b3f741d6-2a0b-4a8a-beb7-82fe23499328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988760152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2988760152
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3991350785
Short name T237
Test name
Test status
Simulation time 26277330383 ps
CPU time 99.49 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:47:35 PM PDT 24
Peak memory 198656 kb
Host smart-eda8a161-b827-40ff-b23c-5d359ebbce27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991350785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3991350785
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1790913726
Short name T60
Test name
Test status
Simulation time 60606198491 ps
CPU time 844.39 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 05:00:04 PM PDT 24
Peak memory 198832 kb
Host smart-e3f22dc6-3dbb-48c5-9cd8-2a8c7afcd656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1790913726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1790913726
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.148241089
Short name T523
Test name
Test status
Simulation time 16081556 ps
CPU time 0.55 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 194492 kb
Host smart-d0aa8ade-6cd1-4104-a9d2-e970d58a011d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148241089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.148241089
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2609672619
Short name T366
Test name
Test status
Simulation time 20980512 ps
CPU time 0.57 seconds
Started Aug 03 04:45:58 PM PDT 24
Finished Aug 03 04:45:59 PM PDT 24
Peak memory 195096 kb
Host smart-6390f9de-4c81-434e-abfe-b3ec5e591716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609672619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2609672619
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.623902006
Short name T456
Test name
Test status
Simulation time 945340477 ps
CPU time 11.9 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:12 PM PDT 24
Peak memory 197400 kb
Host smart-f8455a68-9199-4bab-bafb-09924accfa4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623902006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.623902006
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2954225598
Short name T274
Test name
Test status
Simulation time 24095335 ps
CPU time 0.61 seconds
Started Aug 03 04:45:58 PM PDT 24
Finished Aug 03 04:45:59 PM PDT 24
Peak memory 195752 kb
Host smart-96901bf2-4226-4183-bfa8-33e824c9e786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954225598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2954225598
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.74023779
Short name T574
Test name
Test status
Simulation time 65027417 ps
CPU time 1.05 seconds
Started Aug 03 04:45:56 PM PDT 24
Finished Aug 03 04:45:57 PM PDT 24
Peak memory 196316 kb
Host smart-86642ebf-3ff2-4146-82cd-5f4765cf5b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74023779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.74023779
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2911638220
Short name T642
Test name
Test status
Simulation time 35805305 ps
CPU time 1.67 seconds
Started Aug 03 04:45:59 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 197248 kb
Host smart-24d6f4fc-9e2c-4c2a-bfd6-fde7d572cfb6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911638220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2911638220
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4129898867
Short name T330
Test name
Test status
Simulation time 485775643 ps
CPU time 2.8 seconds
Started Aug 03 04:45:59 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 196376 kb
Host smart-16aa7213-a90a-4ded-847b-6bd7fcdd7165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129898867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4129898867
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3542866550
Short name T183
Test name
Test status
Simulation time 65296021 ps
CPU time 1.18 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:02 PM PDT 24
Peak memory 196528 kb
Host smart-731de16c-2272-4240-9387-9e49593d7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542866550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3542866550
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2572712430
Short name T708
Test name
Test status
Simulation time 25210109 ps
CPU time 0.97 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:01 PM PDT 24
Peak memory 197104 kb
Host smart-ccc0849a-98c7-4f9f-a781-071d4da9aab9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572712430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2572712430
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1515065970
Short name T312
Test name
Test status
Simulation time 164470773 ps
CPU time 2.35 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:46:03 PM PDT 24
Peak memory 198548 kb
Host smart-98332f3b-f01a-4867-b52c-65234c8a110d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515065970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1515065970
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1385102223
Short name T601
Test name
Test status
Simulation time 308099888 ps
CPU time 1.3 seconds
Started Aug 03 04:45:55 PM PDT 24
Finished Aug 03 04:45:56 PM PDT 24
Peak memory 198508 kb
Host smart-c0589d3f-5cad-43a6-a665-431ee7df3e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385102223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1385102223
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2907631866
Short name T525
Test name
Test status
Simulation time 177626126 ps
CPU time 1.36 seconds
Started Aug 03 04:45:59 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 196064 kb
Host smart-0ab72dc2-4747-4398-81bf-c99f8155be3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907631866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2907631866
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2908726778
Short name T342
Test name
Test status
Simulation time 29006273906 ps
CPU time 87.87 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:47:28 PM PDT 24
Peak memory 198764 kb
Host smart-6e88b201-157a-4e0a-9fd0-42a40bb472f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908726778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2908726778
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1677013780
Short name T10
Test name
Test status
Simulation time 61828798736 ps
CPU time 400.5 seconds
Started Aug 03 04:45:58 PM PDT 24
Finished Aug 03 04:52:39 PM PDT 24
Peak memory 198856 kb
Host smart-6a943a6c-0445-4c50-81b3-1d5fee6b760e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1677013780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1677013780
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2054838190
Short name T289
Test name
Test status
Simulation time 10492197 ps
CPU time 0.58 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 195152 kb
Host smart-a55293ce-3a20-4daa-a2fb-891f97a6a8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054838190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2054838190
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3196097843
Short name T396
Test name
Test status
Simulation time 472500328 ps
CPU time 0.89 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 197020 kb
Host smart-5e43a6a2-d1c9-408e-8641-2bcb12e1975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196097843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3196097843
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2041904928
Short name T372
Test name
Test status
Simulation time 283635838 ps
CPU time 9.19 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 197376 kb
Host smart-8d4109c3-9cc1-492e-8968-bae815cd8d50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041904928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2041904928
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1455695370
Short name T186
Test name
Test status
Simulation time 174730355 ps
CPU time 1.05 seconds
Started Aug 03 04:44:31 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 197084 kb
Host smart-ec0854f7-8694-49f3-bbd8-fbb0a55acdfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455695370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1455695370
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3714980635
Short name T533
Test name
Test status
Simulation time 877886904 ps
CPU time 1.29 seconds
Started Aug 03 04:44:30 PM PDT 24
Finished Aug 03 04:44:31 PM PDT 24
Peak memory 196432 kb
Host smart-d2313e6c-88d9-4c0b-9fc8-ad6fbe33391e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714980635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3714980635
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1764677114
Short name T484
Test name
Test status
Simulation time 39407113 ps
CPU time 0.94 seconds
Started Aug 03 04:44:36 PM PDT 24
Finished Aug 03 04:44:37 PM PDT 24
Peak memory 196564 kb
Host smart-0e0846fa-2615-47db-aa1f-a1e12df145c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764677114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1764677114
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2037916242
Short name T64
Test name
Test status
Simulation time 398833725 ps
CPU time 2.55 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 197596 kb
Host smart-68491872-b211-45fc-88ba-4f39663ba027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037916242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2037916242
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1569024033
Short name T437
Test name
Test status
Simulation time 75145117 ps
CPU time 0.81 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197852 kb
Host smart-e4d13dbd-5470-4757-9d4d-e6e59f272204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569024033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1569024033
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3174318032
Short name T202
Test name
Test status
Simulation time 31367016 ps
CPU time 0.86 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197128 kb
Host smart-bd810a6b-34b8-4de6-ba7f-ff6396e072e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174318032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3174318032
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2426983347
Short name T691
Test name
Test status
Simulation time 699938795 ps
CPU time 5.76 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 198540 kb
Host smart-b8c44c36-3e9d-4b77-8288-78eb73c92b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426983347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2426983347
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3190833311
Short name T653
Test name
Test status
Simulation time 81861720 ps
CPU time 0.99 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 196308 kb
Host smart-ee0806ed-cb34-4441-8b7f-68b79b4f1f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190833311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3190833311
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3203769091
Short name T685
Test name
Test status
Simulation time 179921271 ps
CPU time 1.63 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 197408 kb
Host smart-814d2179-ab79-41e4-a89e-9878f2ababf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203769091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3203769091
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1767287685
Short name T311
Test name
Test status
Simulation time 17020681768 ps
CPU time 64.16 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:45:38 PM PDT 24
Peak memory 198744 kb
Host smart-c355ee29-5d58-4957-b02b-2f3fd18181b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767287685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1767287685
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.769790379
Short name T42
Test name
Test status
Simulation time 36653132 ps
CPU time 0.61 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 195412 kb
Host smart-142bc047-9932-4cd0-8e88-71238cce3a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769790379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.769790379
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3618020506
Short name T140
Test name
Test status
Simulation time 89934155 ps
CPU time 0.67 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 194616 kb
Host smart-73a47917-3e0a-4d99-8a4a-a429e791a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618020506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3618020506
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4232173121
Short name T675
Test name
Test status
Simulation time 1528637772 ps
CPU time 17.68 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 198060 kb
Host smart-27879a90-d411-403d-a7ef-d1a81b667736
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232173121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4232173121
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1937016084
Short name T676
Test name
Test status
Simulation time 185271665 ps
CPU time 1.08 seconds
Started Aug 03 04:44:33 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 197044 kb
Host smart-125823eb-8387-42ab-8dd0-cb367cd8d400
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937016084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1937016084
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3520052255
Short name T362
Test name
Test status
Simulation time 113860978 ps
CPU time 0.87 seconds
Started Aug 03 04:44:32 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 197944 kb
Host smart-e7cabb4a-29ce-4f94-8900-7d63a3647cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520052255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3520052255
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1755834969
Short name T269
Test name
Test status
Simulation time 155556524 ps
CPU time 1.46 seconds
Started Aug 03 04:44:36 PM PDT 24
Finished Aug 03 04:44:37 PM PDT 24
Peak memory 196892 kb
Host smart-0dcde0f4-11ec-4c00-b4be-293207a57d56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755834969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1755834969
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3134184767
Short name T660
Test name
Test status
Simulation time 109742710 ps
CPU time 1.88 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:37 PM PDT 24
Peak memory 196368 kb
Host smart-f3afa60c-83ff-4f2f-a6b7-188c6b8af068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134184767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3134184767
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4063743628
Short name T542
Test name
Test status
Simulation time 53091199 ps
CPU time 0.65 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 194792 kb
Host smart-0dbc2533-0734-415d-8982-8f5043df20a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063743628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4063743628
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3837137605
Short name T694
Test name
Test status
Simulation time 52158708 ps
CPU time 1.11 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 197084 kb
Host smart-2e2093f1-e47a-45cd-b3a1-f5007411343b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837137605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3837137605
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3295128325
Short name T8
Test name
Test status
Simulation time 216299299 ps
CPU time 2.8 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 198164 kb
Host smart-c1a1d698-a2cd-4bcd-ba36-186e6a77478e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295128325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3295128325
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.688213043
Short name T321
Test name
Test status
Simulation time 70686004 ps
CPU time 1.46 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196860 kb
Host smart-338d90ac-92a8-48f8-b7c9-836e4f0a6cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688213043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.688213043
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2300103749
Short name T360
Test name
Test status
Simulation time 35012925 ps
CPU time 0.78 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 196148 kb
Host smart-77c2eb27-2cf4-4dea-932f-3c6a03683269
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300103749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2300103749
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3615449218
Short name T209
Test name
Test status
Simulation time 1159842782 ps
CPU time 18.17 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 198616 kb
Host smart-27fc5819-972a-409f-a0aa-feaa6efd6dc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615449218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3615449218
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1757772981
Short name T592
Test name
Test status
Simulation time 376864777963 ps
CPU time 1791.78 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 05:14:36 PM PDT 24
Peak memory 198796 kb
Host smart-8daff6fd-5e9d-4ca3-b45c-70b225f3af18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1757772981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1757772981
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2867557049
Short name T635
Test name
Test status
Simulation time 11386121 ps
CPU time 0.63 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 194484 kb
Host smart-0a3f0a45-742f-428c-9de2-643a694fe00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867557049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2867557049
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1287199063
Short name T93
Test name
Test status
Simulation time 374084031 ps
CPU time 0.89 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 197044 kb
Host smart-fc714449-ed0d-4e1a-be66-48507daf1098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287199063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1287199063
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3611428539
Short name T132
Test name
Test status
Simulation time 773227308 ps
CPU time 26.85 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:45:02 PM PDT 24
Peak memory 197144 kb
Host smart-bb4e3d99-35cf-4999-bc8d-41cf35c97f3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611428539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3611428539
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1408738237
Short name T221
Test name
Test status
Simulation time 690812971 ps
CPU time 0.77 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196208 kb
Host smart-929e22e9-6976-45c6-a8e4-3583b6fa4978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408738237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1408738237
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2612887380
Short name T328
Test name
Test status
Simulation time 115540735 ps
CPU time 0.95 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 197204 kb
Host smart-f64ccf6c-8247-4b16-b50c-79a081618b4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612887380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2612887380
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1500312707
Short name T689
Test name
Test status
Simulation time 307492920 ps
CPU time 3.03 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 198572 kb
Host smart-f17ef5ef-80b7-4d7e-8964-24b175542273
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500312707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1500312707
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1985542464
Short name T479
Test name
Test status
Simulation time 638944915 ps
CPU time 3.4 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 197036 kb
Host smart-169db26a-17c9-4567-8842-04456b2b065d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985542464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1985542464
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2521558505
Short name T546
Test name
Test status
Simulation time 19905163 ps
CPU time 0.77 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 197092 kb
Host smart-eedae7d3-ac0b-4c30-8834-ce66a18c98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521558505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2521558505
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3536583821
Short name T666
Test name
Test status
Simulation time 266830217 ps
CPU time 1.12 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 197360 kb
Host smart-f8839806-4a60-4391-bfc5-cd217fcc6946
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536583821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3536583821
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1100353123
Short name T435
Test name
Test status
Simulation time 285267944 ps
CPU time 4.9 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 198472 kb
Host smart-f795fcc7-4e72-40c2-b1cb-446dfeef0025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100353123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1100353123
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1900161555
Short name T536
Test name
Test status
Simulation time 43400504 ps
CPU time 0.96 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:35 PM PDT 24
Peak memory 196248 kb
Host smart-306e0296-a3ea-4d9a-8eed-06f86c06ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900161555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1900161555
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2112255241
Short name T549
Test name
Test status
Simulation time 71491396 ps
CPU time 1.12 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 196324 kb
Host smart-d2678b66-b716-496e-a56a-b8c0af5110a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112255241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2112255241
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3564878999
Short name T284
Test name
Test status
Simulation time 87810424198 ps
CPU time 141.86 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:47:00 PM PDT 24
Peak memory 198724 kb
Host smart-dfeca6b6-c8c9-470f-bba2-48d216be71b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564878999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3564878999
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2371870495
Short name T670
Test name
Test status
Simulation time 543112200549 ps
CPU time 2432.65 seconds
Started Aug 03 04:44:35 PM PDT 24
Finished Aug 03 05:25:08 PM PDT 24
Peak memory 198872 kb
Host smart-5b31b49b-0aef-420d-bcd8-2b1f2001bcc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2371870495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2371870495
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.868780525
Short name T67
Test name
Test status
Simulation time 11898700 ps
CPU time 0.59 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 195188 kb
Host smart-33839651-37a4-4a7f-a28d-35bf6d458274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868780525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.868780525
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.696994764
Short name T29
Test name
Test status
Simulation time 160110043 ps
CPU time 0.77 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 195652 kb
Host smart-db0a937e-81a1-4423-89d0-9177cb5d9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696994764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.696994764
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.5673115
Short name T452
Test name
Test status
Simulation time 1849966505 ps
CPU time 23.02 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 197404 kb
Host smart-ae4930c3-05e7-4a53-9d52-88df0b4a28a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5673115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.5673115
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2088142989
Short name T20
Test name
Test status
Simulation time 124333948 ps
CPU time 0.87 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:39 PM PDT 24
Peak memory 197244 kb
Host smart-7d4a46ff-aa59-4844-bb37-0c759edbeb57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088142989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2088142989
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.739950307
Short name T31
Test name
Test status
Simulation time 60151711 ps
CPU time 0.74 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 194892 kb
Host smart-1a69136c-492f-4ab3-ba8d-9d88291dfcd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739950307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.739950307
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.803602674
Short name T340
Test name
Test status
Simulation time 159911086 ps
CPU time 1.91 seconds
Started Aug 03 04:44:47 PM PDT 24
Finished Aug 03 04:44:49 PM PDT 24
Peak memory 197040 kb
Host smart-11991898-c767-4890-bcfd-2b75fc45f125
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803602674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.803602674
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1803808654
Short name T170
Test name
Test status
Simulation time 498541788 ps
CPU time 2.36 seconds
Started Aug 03 04:44:42 PM PDT 24
Finished Aug 03 04:44:44 PM PDT 24
Peak memory 197684 kb
Host smart-6814e866-9e5e-4af7-9905-fa5179eca764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803808654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1803808654
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3984080844
Short name T593
Test name
Test status
Simulation time 96901396 ps
CPU time 0.83 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 195952 kb
Host smart-6e31858a-7002-4e45-b49c-750c56b23954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984080844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3984080844
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2007009671
Short name T365
Test name
Test status
Simulation time 54728728 ps
CPU time 1.01 seconds
Started Aug 03 04:44:40 PM PDT 24
Finished Aug 03 04:44:41 PM PDT 24
Peak memory 197064 kb
Host smart-94b74c3b-2a7f-42dd-a92f-1230ddfc073a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007009671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2007009671
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3837600632
Short name T697
Test name
Test status
Simulation time 1514665402 ps
CPU time 4.48 seconds
Started Aug 03 04:44:46 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 198500 kb
Host smart-bf2696da-bae7-4917-9dfb-3230f3838b19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837600632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3837600632
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1738454217
Short name T401
Test name
Test status
Simulation time 41807732 ps
CPU time 1.3 seconds
Started Aug 03 04:44:34 PM PDT 24
Finished Aug 03 04:44:36 PM PDT 24
Peak memory 196792 kb
Host smart-51295518-fae2-4459-b8d7-e83dbd250c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738454217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1738454217
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.109404296
Short name T696
Test name
Test status
Simulation time 62386707 ps
CPU time 0.89 seconds
Started Aug 03 04:44:43 PM PDT 24
Finished Aug 03 04:44:44 PM PDT 24
Peak memory 195936 kb
Host smart-8873e392-f00b-4e0a-8435-88d87ebff2cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109404296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.109404296
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2032911697
Short name T115
Test name
Test status
Simulation time 14383814098 ps
CPU time 196.21 seconds
Started Aug 03 04:44:40 PM PDT 24
Finished Aug 03 04:47:56 PM PDT 24
Peak memory 198596 kb
Host smart-fe4d2924-0c94-43ec-84a3-5add4ac7b845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032911697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2032911697
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3609562862
Short name T442
Test name
Test status
Simulation time 50430449 ps
CPU time 0.58 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 195100 kb
Host smart-9484147a-452c-4ded-9d67-5ef19c206f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609562862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3609562862
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3398184002
Short name T251
Test name
Test status
Simulation time 91814467 ps
CPU time 0.84 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 196596 kb
Host smart-257d4d5c-972b-425e-a1b6-105b167ef422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398184002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3398184002
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2112603810
Short name T678
Test name
Test status
Simulation time 1263411936 ps
CPU time 28.37 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 198536 kb
Host smart-fae3ea1f-1c37-4e5a-8298-e71aeb42efa6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112603810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2112603810
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1572102975
Short name T407
Test name
Test status
Simulation time 166519724 ps
CPU time 0.86 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:44 PM PDT 24
Peak memory 197680 kb
Host smart-5f4440d7-e8e3-4d6c-9d93-7c03ec336b85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572102975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1572102975
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2691140280
Short name T108
Test name
Test status
Simulation time 58906185 ps
CPU time 0.83 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 197720 kb
Host smart-15bf7bfb-4c8a-41f6-8f10-ca36e2362a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691140280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2691140280
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1340948649
Short name T467
Test name
Test status
Simulation time 69568921 ps
CPU time 2.85 seconds
Started Aug 03 04:44:42 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 198644 kb
Host smart-d209fd67-99ae-4e9f-8973-438d2eb9a617
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340948649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1340948649
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1153882971
Short name T690
Test name
Test status
Simulation time 530201243 ps
CPU time 3.49 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 198580 kb
Host smart-6c933777-9ea8-4b32-bb3c-b13ae4b7bdcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153882971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1153882971
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.687070581
Short name T125
Test name
Test status
Simulation time 25990249 ps
CPU time 1.11 seconds
Started Aug 03 04:44:37 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 196372 kb
Host smart-54f19de2-f654-44d5-9157-e4a18d1e200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687070581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.687070581
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2341874218
Short name T232
Test name
Test status
Simulation time 375703395 ps
CPU time 0.85 seconds
Started Aug 03 04:44:44 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 196480 kb
Host smart-5eda2925-2c70-4d5a-9805-1cf9cf1d4fb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341874218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2341874218
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.270251006
Short name T263
Test name
Test status
Simulation time 1120889343 ps
CPU time 3.41 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:43 PM PDT 24
Peak memory 198548 kb
Host smart-fbfcc3bf-59dd-4dc0-8238-aef2311af2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270251006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.270251006
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3767217907
Short name T122
Test name
Test status
Simulation time 150941543 ps
CPU time 1.26 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 197412 kb
Host smart-dcfab3da-6155-4ac8-a983-34b1853917d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767217907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3767217907
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1835674648
Short name T532
Test name
Test status
Simulation time 38527134 ps
CPU time 0.82 seconds
Started Aug 03 04:44:41 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 195652 kb
Host smart-a9ae28b0-888b-4048-bd02-976fce530e40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835674648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1835674648
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.513263961
Short name T5
Test name
Test status
Simulation time 2019612358 ps
CPU time 15.77 seconds
Started Aug 03 04:44:39 PM PDT 24
Finished Aug 03 04:44:55 PM PDT 24
Peak memory 198612 kb
Host smart-4641b5d7-bf7c-4ff1-8372-cdc7082e194e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513263961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.513263961
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3958469488
Short name T61
Test name
Test status
Simulation time 114284736974 ps
CPU time 1991.37 seconds
Started Aug 03 04:44:38 PM PDT 24
Finished Aug 03 05:17:49 PM PDT 24
Peak memory 198892 kb
Host smart-c57b93c1-9ec3-4ac1-82fb-755f63cb456b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3958469488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3958469488
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1123692977
Short name T861
Test name
Test status
Simulation time 56608959 ps
CPU time 0.95 seconds
Started Aug 03 04:19:12 PM PDT 24
Finished Aug 03 04:19:13 PM PDT 24
Peak memory 196856 kb
Host smart-341eaa9a-daf5-4940-b117-c037b55bcc32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1123692977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1123692977
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1229905740
Short name T887
Test name
Test status
Simulation time 59300018 ps
CPU time 1.01 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 197460 kb
Host smart-7c8e232d-c737-451b-bc47-f0d614e06bb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229905740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1229905740
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1936669927
Short name T894
Test name
Test status
Simulation time 91913822 ps
CPU time 0.93 seconds
Started Aug 03 04:21:37 PM PDT 24
Finished Aug 03 04:21:38 PM PDT 24
Peak memory 195872 kb
Host smart-884b3f37-9bc7-4e32-a11d-18a1d74f1e0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1936669927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1936669927
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990847245
Short name T938
Test name
Test status
Simulation time 330613089 ps
CPU time 1.35 seconds
Started Aug 03 04:19:51 PM PDT 24
Finished Aug 03 04:19:53 PM PDT 24
Peak memory 197832 kb
Host smart-a4416b89-6fc2-4354-a502-d7b907b4cd0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990847245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1990847245
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.262051134
Short name T881
Test name
Test status
Simulation time 202984143 ps
CPU time 1.44 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:03 PM PDT 24
Peak memory 195980 kb
Host smart-538ce28d-363a-40ce-b711-003201adbd7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=262051134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.262051134
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3666127625
Short name T888
Test name
Test status
Simulation time 137590580 ps
CPU time 1.42 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:33 PM PDT 24
Peak memory 196340 kb
Host smart-b6754ed4-de1b-4f53-a53d-7c065905d92e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666127625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3666127625
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3061147288
Short name T940
Test name
Test status
Simulation time 185749878 ps
CPU time 0.94 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:20:44 PM PDT 24
Peak memory 196800 kb
Host smart-8aabb4a6-dc1c-461c-88e9-40e79ab6eec2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3061147288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3061147288
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3286571028
Short name T876
Test name
Test status
Simulation time 240040831 ps
CPU time 1.11 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:00 PM PDT 24
Peak memory 197752 kb
Host smart-0bb1be15-117e-420f-b12f-82a7877ac756
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286571028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3286571028
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.185089118
Short name T863
Test name
Test status
Simulation time 152510611 ps
CPU time 1.36 seconds
Started Aug 03 04:23:14 PM PDT 24
Finished Aug 03 04:23:15 PM PDT 24
Peak memory 197904 kb
Host smart-1784eacb-72fd-4853-82f4-6dce39e6da0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=185089118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.185089118
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.134747112
Short name T930
Test name
Test status
Simulation time 100787017 ps
CPU time 1.05 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:00 PM PDT 24
Peak memory 196336 kb
Host smart-8ef8823e-7075-4d20-ae94-0f760bb7bd1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134747112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.134747112
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2006681911
Short name T866
Test name
Test status
Simulation time 94094350 ps
CPU time 1 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:00 PM PDT 24
Peak memory 196364 kb
Host smart-9c0c1076-5bc9-4703-b803-cc29378bde05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2006681911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2006681911
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101411421
Short name T911
Test name
Test status
Simulation time 51665258 ps
CPU time 1.08 seconds
Started Aug 03 04:22:11 PM PDT 24
Finished Aug 03 04:22:12 PM PDT 24
Peak memory 196356 kb
Host smart-1266ba24-5890-422b-a5ed-54de80be299e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101411421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1101411421
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2906803170
Short name T896
Test name
Test status
Simulation time 231336622 ps
CPU time 1.19 seconds
Started Aug 03 04:19:38 PM PDT 24
Finished Aug 03 04:19:39 PM PDT 24
Peak memory 196272 kb
Host smart-81fd258b-1f4c-4891-a4b5-f1e0eee70f5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2906803170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2906803170
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2769434300
Short name T914
Test name
Test status
Simulation time 38161146 ps
CPU time 0.88 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:36 PM PDT 24
Peak memory 196288 kb
Host smart-281531e6-e041-4c91-8717-ab5effa9f4ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769434300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2769434300
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1555714175
Short name T849
Test name
Test status
Simulation time 51194585 ps
CPU time 1.02 seconds
Started Aug 03 04:20:29 PM PDT 24
Finished Aug 03 04:20:30 PM PDT 24
Peak memory 196520 kb
Host smart-f353416f-4705-497e-9b91-ef7af77c7e4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1555714175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1555714175
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3705377679
Short name T850
Test name
Test status
Simulation time 219586750 ps
CPU time 0.98 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 197864 kb
Host smart-5680d8aa-e6bf-4b48-b8cf-4b0032fe0734
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705377679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3705377679
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2890327104
Short name T916
Test name
Test status
Simulation time 45446214 ps
CPU time 0.98 seconds
Started Aug 03 04:18:43 PM PDT 24
Finished Aug 03 04:18:44 PM PDT 24
Peak memory 196340 kb
Host smart-f7330155-e8ad-46b0-871c-5514d50a7f9b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2890327104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2890327104
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.186087134
Short name T858
Test name
Test status
Simulation time 50909774 ps
CPU time 1.26 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:22:34 PM PDT 24
Peak memory 191468 kb
Host smart-fb947d61-81fc-4942-b38d-b2d3c2262007
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186087134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.186087134
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3867414739
Short name T905
Test name
Test status
Simulation time 42856812 ps
CPU time 1.13 seconds
Started Aug 03 04:22:14 PM PDT 24
Finished Aug 03 04:22:15 PM PDT 24
Peak memory 195824 kb
Host smart-a9d49ad9-294d-4671-a848-fe0665a6e40c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3867414739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3867414739
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193953962
Short name T853
Test name
Test status
Simulation time 69875506 ps
CPU time 1.14 seconds
Started Aug 03 04:19:32 PM PDT 24
Finished Aug 03 04:19:33 PM PDT 24
Peak memory 195760 kb
Host smart-831efef5-fa1b-45d5-9553-e08580c433e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193953962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.193953962
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1559809070
Short name T908
Test name
Test status
Simulation time 108057051 ps
CPU time 0.85 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 195068 kb
Host smart-b3c0c7d6-a797-4503-8151-b8e2772250e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1559809070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1559809070
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302485232
Short name T890
Test name
Test status
Simulation time 89483722 ps
CPU time 0.99 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:50 PM PDT 24
Peak memory 195524 kb
Host smart-9c7b6a74-860f-4859-a366-1e66560db4a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302485232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.302485232
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.258950691
Short name T854
Test name
Test status
Simulation time 77198200 ps
CPU time 1.44 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:20:46 PM PDT 24
Peak memory 191368 kb
Host smart-37bc23fb-9191-44e1-8453-5f1072ce3c57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=258950691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.258950691
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2951574545
Short name T852
Test name
Test status
Simulation time 49214249 ps
CPU time 1.03 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:20:45 PM PDT 24
Peak memory 195276 kb
Host smart-ce405e20-347a-4d50-9a7a-56ce971db8a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951574545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2951574545
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2144103782
Short name T906
Test name
Test status
Simulation time 52780418 ps
CPU time 1.25 seconds
Started Aug 03 04:20:34 PM PDT 24
Finished Aug 03 04:20:35 PM PDT 24
Peak memory 196344 kb
Host smart-edbdf1c8-ff34-4c79-b1c7-6a5456509544
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2144103782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2144103782
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639837779
Short name T919
Test name
Test status
Simulation time 145661819 ps
CPU time 0.81 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:41 PM PDT 24
Peak memory 195908 kb
Host smart-3a826a44-a3c6-461a-bb94-d45556700eb8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639837779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1639837779
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3446468557
Short name T856
Test name
Test status
Simulation time 62066347 ps
CPU time 1.25 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 195628 kb
Host smart-a92ed85a-8277-41a6-b872-8278805491dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3446468557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3446468557
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3171641359
Short name T895
Test name
Test status
Simulation time 49258791 ps
CPU time 0.94 seconds
Started Aug 03 04:22:06 PM PDT 24
Finished Aug 03 04:22:07 PM PDT 24
Peak memory 196260 kb
Host smart-1af3b22b-4847-46c0-8efd-0f10a0991078
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171641359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3171641359
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2833493987
Short name T868
Test name
Test status
Simulation time 140830331 ps
CPU time 1.18 seconds
Started Aug 03 04:19:13 PM PDT 24
Finished Aug 03 04:19:14 PM PDT 24
Peak memory 196500 kb
Host smart-51bc5a38-757a-4767-9973-b091e185b93f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2833493987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2833493987
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4185818000
Short name T851
Test name
Test status
Simulation time 84268378 ps
CPU time 1.18 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:47 PM PDT 24
Peak memory 195936 kb
Host smart-352b055c-8245-4680-8068-36d0d50e9ecb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185818000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4185818000
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2941484409
Short name T892
Test name
Test status
Simulation time 116353709 ps
CPU time 0.79 seconds
Started Aug 03 04:21:16 PM PDT 24
Finished Aug 03 04:21:16 PM PDT 24
Peak memory 195260 kb
Host smart-ca0713f0-8763-43d1-9f69-b8749523e4da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2941484409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2941484409
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698655825
Short name T929
Test name
Test status
Simulation time 325006946 ps
CPU time 1.55 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 197768 kb
Host smart-0e5d163c-e701-45c1-8915-8a950f85390d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698655825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2698655825
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3753609940
Short name T944
Test name
Test status
Simulation time 102244772 ps
CPU time 1.03 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:46 PM PDT 24
Peak memory 194524 kb
Host smart-92c1146a-1690-4c59-b8f0-d65b4d0d2246
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3753609940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3753609940
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2701766374
Short name T900
Test name
Test status
Simulation time 70070487 ps
CPU time 0.75 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:01 PM PDT 24
Peak memory 195072 kb
Host smart-426c89d6-baeb-4639-a1c6-34385d9a1d3f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701766374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2701766374
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2865303508
Short name T943
Test name
Test status
Simulation time 41460190 ps
CPU time 1.24 seconds
Started Aug 03 04:19:36 PM PDT 24
Finished Aug 03 04:19:38 PM PDT 24
Peak memory 195468 kb
Host smart-f0822ca4-6d11-466f-8742-313e1d110e10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2865303508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2865303508
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207721062
Short name T865
Test name
Test status
Simulation time 265745240 ps
CPU time 1.16 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:25 PM PDT 24
Peak memory 195504 kb
Host smart-cb04e4fe-9e9c-4e87-9ce4-b8df2a9f0bb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207721062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.207721062
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.889671256
Short name T921
Test name
Test status
Simulation time 85036352 ps
CPU time 1.48 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 196416 kb
Host smart-97df73ec-b510-409d-8f43-560e4c313d7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=889671256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.889671256
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4074981825
Short name T915
Test name
Test status
Simulation time 59157299 ps
CPU time 1.02 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:53 PM PDT 24
Peak memory 194636 kb
Host smart-fffb9ad8-42fa-4a81-be9a-7c3c9c026047
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074981825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4074981825
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3950199807
Short name T884
Test name
Test status
Simulation time 57850886 ps
CPU time 0.93 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 195204 kb
Host smart-22889821-65d7-464c-b33e-c1a8a574e14e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3950199807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3950199807
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187806947
Short name T942
Test name
Test status
Simulation time 148775442 ps
CPU time 1.34 seconds
Started Aug 03 04:18:50 PM PDT 24
Finished Aug 03 04:18:51 PM PDT 24
Peak memory 196624 kb
Host smart-bc0d2d41-c5a5-4539-8a53-670c6fb1523e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187806947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4187806947
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1329907618
Short name T948
Test name
Test status
Simulation time 227130545 ps
CPU time 1.11 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 196384 kb
Host smart-43832e72-0513-4d55-85f7-b67e592c761e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1329907618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1329907618
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618924004
Short name T941
Test name
Test status
Simulation time 68190418 ps
CPU time 1.43 seconds
Started Aug 03 04:19:32 PM PDT 24
Finished Aug 03 04:19:33 PM PDT 24
Peak memory 196348 kb
Host smart-1d54a598-57d3-422a-bf8a-dc8ac8bd2243
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618924004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.618924004
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2998087350
Short name T923
Test name
Test status
Simulation time 95462903 ps
CPU time 1.02 seconds
Started Aug 03 04:19:25 PM PDT 24
Finished Aug 03 04:19:26 PM PDT 24
Peak memory 196392 kb
Host smart-8f0953d9-0bcd-4f87-a8fa-10fa02e32251
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2998087350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2998087350
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2490844131
Short name T862
Test name
Test status
Simulation time 67549419 ps
CPU time 1.08 seconds
Started Aug 03 04:21:00 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 196500 kb
Host smart-bf740ed2-a83a-4d77-8708-92b2508c25e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490844131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2490844131
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.133312789
Short name T886
Test name
Test status
Simulation time 86284307 ps
CPU time 1.04 seconds
Started Aug 03 04:21:04 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 195248 kb
Host smart-f9bb5aff-cf7b-4f73-ac69-4cd2066870f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=133312789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.133312789
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1409567254
Short name T912
Test name
Test status
Simulation time 133814801 ps
CPU time 0.9 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:20:44 PM PDT 24
Peak memory 193992 kb
Host smart-ace89225-1a74-4c80-88c4-dc75b6043d9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409567254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1409567254
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1422823359
Short name T879
Test name
Test status
Simulation time 134736569 ps
CPU time 1.15 seconds
Started Aug 03 04:23:38 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 197520 kb
Host smart-2c4ca582-991e-433d-b0e8-3cac7f8616ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1422823359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1422823359
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.669370803
Short name T903
Test name
Test status
Simulation time 579987645 ps
CPU time 1.31 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:37 PM PDT 24
Peak memory 195600 kb
Host smart-a026f02e-984c-42cd-affd-126afc390884
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669370803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.669370803
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4265234036
Short name T871
Test name
Test status
Simulation time 72407043 ps
CPU time 1.09 seconds
Started Aug 03 04:19:23 PM PDT 24
Finished Aug 03 04:19:24 PM PDT 24
Peak memory 197804 kb
Host smart-14d173da-4e3d-42ad-bc93-f3f576cf620a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4265234036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4265234036
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2685842442
Short name T934
Test name
Test status
Simulation time 64636190 ps
CPU time 1.14 seconds
Started Aug 03 04:19:48 PM PDT 24
Finished Aug 03 04:19:50 PM PDT 24
Peak memory 196456 kb
Host smart-e62b6f0a-f34e-40f7-b2df-7a8bed012f7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685842442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2685842442
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.191879833
Short name T902
Test name
Test status
Simulation time 81267406 ps
CPU time 0.81 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:57 PM PDT 24
Peak memory 196348 kb
Host smart-08e76d62-d299-44d9-9050-926f170d79ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=191879833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.191879833
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2380874787
Short name T857
Test name
Test status
Simulation time 249465568 ps
CPU time 1.34 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 196896 kb
Host smart-a9085571-5dff-4250-b850-687b1550f5d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380874787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2380874787
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.277342312
Short name T907
Test name
Test status
Simulation time 52119625 ps
CPU time 1.32 seconds
Started Aug 03 04:20:43 PM PDT 24
Finished Aug 03 04:20:44 PM PDT 24
Peak memory 195580 kb
Host smart-1c6a89ed-d291-4605-bddf-8fb0554c0e31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=277342312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.277342312
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3180522862
Short name T901
Test name
Test status
Simulation time 260714666 ps
CPU time 1.1 seconds
Started Aug 03 04:21:00 PM PDT 24
Finished Aug 03 04:21:01 PM PDT 24
Peak memory 196292 kb
Host smart-236ebb1c-7d48-4635-ab9f-ef23e36d17ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180522862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3180522862
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3369753388
Short name T874
Test name
Test status
Simulation time 138245657 ps
CPU time 1.35 seconds
Started Aug 03 04:19:20 PM PDT 24
Finished Aug 03 04:19:21 PM PDT 24
Peak memory 196704 kb
Host smart-74f20ec4-9649-468b-b153-b200fcb48b86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3369753388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3369753388
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2992189580
Short name T939
Test name
Test status
Simulation time 261101793 ps
CPU time 1.15 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:20:44 PM PDT 24
Peak memory 194880 kb
Host smart-e492f210-e8e8-4cbb-ab27-1d8483d81663
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992189580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2992189580
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.30986947
Short name T913
Test name
Test status
Simulation time 278554659 ps
CPU time 1.28 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 197828 kb
Host smart-38bc6b52-6344-4c23-8cd6-09df7ffa03f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=30986947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.30986947
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178712300
Short name T859
Test name
Test status
Simulation time 312547936 ps
CPU time 1.26 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 196364 kb
Host smart-b379ac76-b909-424f-a076-cdfa0d6aa61b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178712300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1178712300
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.971316456
Short name T918
Test name
Test status
Simulation time 79004950 ps
CPU time 1.3 seconds
Started Aug 03 04:19:45 PM PDT 24
Finished Aug 03 04:19:46 PM PDT 24
Peak memory 196840 kb
Host smart-7a348355-209a-4cff-833a-d9fd1f97a101
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=971316456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.971316456
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272389833
Short name T924
Test name
Test status
Simulation time 280926547 ps
CPU time 1.36 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:47 PM PDT 24
Peak memory 196200 kb
Host smart-9cb7143a-15ae-45f3-9552-b6fe7cd684da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272389833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1272389833
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2759488712
Short name T897
Test name
Test status
Simulation time 118657539 ps
CPU time 1.1 seconds
Started Aug 03 04:19:38 PM PDT 24
Finished Aug 03 04:19:39 PM PDT 24
Peak memory 196404 kb
Host smart-afad4530-fc2e-43f5-9e0a-6916a8e125aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2759488712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2759488712
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652618048
Short name T878
Test name
Test status
Simulation time 285326076 ps
CPU time 1.32 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 195896 kb
Host smart-044f1b2a-d265-47fa-bc5c-4ddf569e993b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652618048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3652618048
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1573688006
Short name T875
Test name
Test status
Simulation time 39517718 ps
CPU time 1.18 seconds
Started Aug 03 04:22:47 PM PDT 24
Finished Aug 03 04:22:48 PM PDT 24
Peak memory 196256 kb
Host smart-7794b88d-cf6d-40bf-802e-aaa49f22d7f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1573688006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1573688006
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040477637
Short name T947
Test name
Test status
Simulation time 341598992 ps
CPU time 1.35 seconds
Started Aug 03 04:20:58 PM PDT 24
Finished Aug 03 04:20:59 PM PDT 24
Peak memory 197356 kb
Host smart-94539f08-3820-4791-8e4c-6aa59e71fc68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040477637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1040477637
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.487371743
Short name T877
Test name
Test status
Simulation time 130729963 ps
CPU time 0.9 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:20:41 PM PDT 24
Peak memory 193264 kb
Host smart-2976e5b8-2864-4a35-8f75-987664edbd9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=487371743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.487371743
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332550493
Short name T870
Test name
Test status
Simulation time 124277574 ps
CPU time 0.9 seconds
Started Aug 03 04:19:19 PM PDT 24
Finished Aug 03 04:19:20 PM PDT 24
Peak memory 195248 kb
Host smart-4d626934-07b7-41b4-83f9-5f3a66581597
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332550493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2332550493
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1058834498
Short name T869
Test name
Test status
Simulation time 39834144 ps
CPU time 0.88 seconds
Started Aug 03 04:19:44 PM PDT 24
Finished Aug 03 04:19:44 PM PDT 24
Peak memory 195228 kb
Host smart-cce68092-f8f4-4315-863f-8bb429cb931e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1058834498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1058834498
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2760158523
Short name T920
Test name
Test status
Simulation time 262012367 ps
CPU time 1.12 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:20:42 PM PDT 24
Peak memory 195928 kb
Host smart-9d9e73a8-ca9f-4557-8228-a9d3736efee7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760158523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2760158523
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2871243532
Short name T904
Test name
Test status
Simulation time 86796644 ps
CPU time 1.01 seconds
Started Aug 03 04:18:39 PM PDT 24
Finished Aug 03 04:18:41 PM PDT 24
Peak memory 196292 kb
Host smart-521e5cc2-5ab0-4a42-8def-15621233612b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2871243532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2871243532
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2756708928
Short name T899
Test name
Test status
Simulation time 131290210 ps
CPU time 0.72 seconds
Started Aug 03 04:19:24 PM PDT 24
Finished Aug 03 04:19:25 PM PDT 24
Peak memory 194824 kb
Host smart-56670759-59d1-4b5e-902b-ab01f26b1333
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756708928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2756708928
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.163417463
Short name T936
Test name
Test status
Simulation time 70083924 ps
CPU time 0.95 seconds
Started Aug 03 04:21:00 PM PDT 24
Finished Aug 03 04:21:01 PM PDT 24
Peak memory 196296 kb
Host smart-1c059768-e97d-4acc-8efb-69072f7d4c5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=163417463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.163417463
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2477601051
Short name T872
Test name
Test status
Simulation time 19776159 ps
CPU time 0.72 seconds
Started Aug 03 04:20:40 PM PDT 24
Finished Aug 03 04:20:41 PM PDT 24
Peak memory 193216 kb
Host smart-b74374b4-c34b-4b09-9fb8-104f4cc434eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477601051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2477601051
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3754799593
Short name T922
Test name
Test status
Simulation time 88135432 ps
CPU time 1.31 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 196812 kb
Host smart-bb497a48-e8df-4ddd-8fd6-b4accf582894
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3754799593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3754799593
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132854542
Short name T946
Test name
Test status
Simulation time 39995872 ps
CPU time 0.85 seconds
Started Aug 03 04:21:09 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 194760 kb
Host smart-9378c6c1-339d-4ca5-b6e0-d91ed1221edc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132854542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4132854542
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3681557429
Short name T935
Test name
Test status
Simulation time 67596142 ps
CPU time 1.18 seconds
Started Aug 03 04:21:16 PM PDT 24
Finished Aug 03 04:21:17 PM PDT 24
Peak memory 196340 kb
Host smart-c572bbbc-1877-44c8-b107-d589dab8fa7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3681557429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3681557429
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.774794204
Short name T945
Test name
Test status
Simulation time 632101578 ps
CPU time 1.37 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 196664 kb
Host smart-b3fa29a2-6524-4698-9cbd-00cf21ec8fe2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774794204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.774794204
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.774269754
Short name T882
Test name
Test status
Simulation time 42051244 ps
CPU time 1.14 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 196284 kb
Host smart-7a59463c-2018-4a3b-89fd-0a091e943945
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=774269754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.774269754
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3076435668
Short name T898
Test name
Test status
Simulation time 113492601 ps
CPU time 0.97 seconds
Started Aug 03 04:19:34 PM PDT 24
Finished Aug 03 04:19:35 PM PDT 24
Peak memory 196344 kb
Host smart-b2730288-4fe5-4af5-8bcb-265dafcebeaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076435668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3076435668
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.759631957
Short name T925
Test name
Test status
Simulation time 112897771 ps
CPU time 1.06 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 197768 kb
Host smart-9a604458-ba79-44df-ade2-763d4c56c7af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=759631957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.759631957
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1858814333
Short name T917
Test name
Test status
Simulation time 326624869 ps
CPU time 1.21 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:20:59 PM PDT 24
Peak memory 195756 kb
Host smart-6f1f456c-275d-4bd3-965f-ebd85544d67f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858814333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1858814333
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.922051327
Short name T926
Test name
Test status
Simulation time 504596075 ps
CPU time 1.2 seconds
Started Aug 03 04:20:58 PM PDT 24
Finished Aug 03 04:21:00 PM PDT 24
Peak memory 197660 kb
Host smart-f289b831-f677-47e6-87d1-2275177744b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=922051327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.922051327
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1440952798
Short name T932
Test name
Test status
Simulation time 43520950 ps
CPU time 0.85 seconds
Started Aug 03 04:21:10 PM PDT 24
Finished Aug 03 04:21:11 PM PDT 24
Peak memory 195172 kb
Host smart-b3ba8cc1-2aa9-4bef-a01a-f1cd05089599
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440952798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1440952798
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1573854008
Short name T860
Test name
Test status
Simulation time 146792056 ps
CPU time 1.19 seconds
Started Aug 03 04:19:32 PM PDT 24
Finished Aug 03 04:19:33 PM PDT 24
Peak memory 196396 kb
Host smart-fc5fe694-0c3d-4ef5-a0b3-f2ad3b1adfd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1573854008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1573854008
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538655903
Short name T893
Test name
Test status
Simulation time 53966729 ps
CPU time 1.07 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:05 PM PDT 24
Peak memory 196960 kb
Host smart-39a39fc3-94e6-4a1e-95f3-4c7c69ab6bfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538655903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2538655903
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3759100530
Short name T889
Test name
Test status
Simulation time 162009040 ps
CPU time 0.99 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:48 PM PDT 24
Peak memory 195064 kb
Host smart-7fc8974e-fe2b-4ad9-b247-9c1eef82c182
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3759100530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3759100530
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.226307406
Short name T883
Test name
Test status
Simulation time 155450007 ps
CPU time 1.16 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:10 PM PDT 24
Peak memory 194844 kb
Host smart-aa87e3b7-0251-488a-9591-5b9eb41b981c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226307406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.226307406
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3295499272
Short name T910
Test name
Test status
Simulation time 45519959 ps
CPU time 1.19 seconds
Started Aug 03 04:21:22 PM PDT 24
Finished Aug 03 04:21:23 PM PDT 24
Peak memory 197892 kb
Host smart-e53ea3f2-74a1-4f42-a690-2b78202be769
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3295499272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3295499272
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2419865457
Short name T867
Test name
Test status
Simulation time 22625129 ps
CPU time 0.76 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:48 PM PDT 24
Peak memory 195660 kb
Host smart-833a87df-2b8f-447a-ad51-f539705e1efe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419865457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2419865457
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.479510309
Short name T931
Test name
Test status
Simulation time 313412391 ps
CPU time 1.53 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:47 PM PDT 24
Peak memory 194664 kb
Host smart-a72991da-032b-4c99-b1a5-70b8340e4c71
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=479510309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.479510309
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3348144175
Short name T885
Test name
Test status
Simulation time 108831462 ps
CPU time 0.99 seconds
Started Aug 03 04:21:03 PM PDT 24
Finished Aug 03 04:21:04 PM PDT 24
Peak memory 195416 kb
Host smart-080b2739-fe9a-460f-8d81-a7ebe9e2e095
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348144175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3348144175
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3515338649
Short name T909
Test name
Test status
Simulation time 37407159 ps
CPU time 1.17 seconds
Started Aug 03 04:19:20 PM PDT 24
Finished Aug 03 04:19:21 PM PDT 24
Peak memory 196412 kb
Host smart-1e3ef283-72d2-4096-bbf4-a4cc8435987c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3515338649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3515338649
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2827658199
Short name T933
Test name
Test status
Simulation time 154976070 ps
CPU time 1.21 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 197000 kb
Host smart-02330cf8-d179-455f-ae9c-39579e489f49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827658199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2827658199
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2183410456
Short name T880
Test name
Test status
Simulation time 33873258 ps
CPU time 0.92 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:41 PM PDT 24
Peak memory 197564 kb
Host smart-11f347d7-a006-4ee4-8746-6bf20bacae5f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2183410456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2183410456
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322126395
Short name T873
Test name
Test status
Simulation time 51992110 ps
CPU time 0.96 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 196380 kb
Host smart-522662fc-d4c6-4a5c-9f09-a0b6588d09e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322126395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1322126395
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1565888210
Short name T864
Test name
Test status
Simulation time 363129865 ps
CPU time 0.92 seconds
Started Aug 03 04:21:36 PM PDT 24
Finished Aug 03 04:21:37 PM PDT 24
Peak memory 196276 kb
Host smart-a70ff8aa-4a12-4b5b-8880-20007b8cc05c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1565888210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1565888210
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1252861415
Short name T855
Test name
Test status
Simulation time 617810760 ps
CPU time 1 seconds
Started Aug 03 04:21:21 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 195684 kb
Host smart-954b6814-0249-40d8-8129-aee9d038882e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252861415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1252861415
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3959484336
Short name T891
Test name
Test status
Simulation time 54116936 ps
CPU time 1.35 seconds
Started Aug 03 04:21:21 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 194852 kb
Host smart-c186ae32-a57c-4f20-85cf-67856a503e61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3959484336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3959484336
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3729286851
Short name T927
Test name
Test status
Simulation time 55634888 ps
CPU time 0.83 seconds
Started Aug 03 04:21:44 PM PDT 24
Finished Aug 03 04:21:45 PM PDT 24
Peak memory 196140 kb
Host smart-aca70c27-be52-4ff7-af1f-967e8bd13d09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729286851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3729286851
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3503493326
Short name T937
Test name
Test status
Simulation time 51210268 ps
CPU time 1.25 seconds
Started Aug 03 04:21:30 PM PDT 24
Finished Aug 03 04:21:31 PM PDT 24
Peak memory 196716 kb
Host smart-d7fe5b65-4690-40e1-ac1f-b8ccfa5ff03b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3503493326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3503493326
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3211020250
Short name T928
Test name
Test status
Simulation time 43510379 ps
CPU time 0.96 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 195956 kb
Host smart-7533c533-bca7-4dcf-a974-f5f9220d8c18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211020250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3211020250
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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