Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3106042	1			T22	1		T23	58		T24	47
all_pins[1]	3106042	1			T22	1		T23	58		T24	47
all_pins[2]	3106042	1			T22	1		T23	58		T24	47
all_pins[3]	3106042	1			T22	1		T23	58		T24	47
all_pins[4]	3106042	1			T22	1		T23	58		T24	47
all_pins[5]	3106042	1			T22	1		T23	58		T24	47
all_pins[6]	3106042	1			T22	1		T23	58		T24	47
all_pins[7]	3106042	1			T22	1		T23	58		T24	47
all_pins[8]	3106042	1			T22	1		T23	58		T24	47
all_pins[9]	3106042	1			T22	1		T23	58		T24	47
all_pins[10]	3106042	1			T22	1		T23	58		T24	47
all_pins[11]	3106042	1			T22	1		T23	58		T24	47
all_pins[12]	3106042	1			T22	1		T23	58		T24	47
all_pins[13]	3106042	1			T22	1		T23	58		T24	47
all_pins[14]	3106042	1			T22	1		T23	58		T24	47
all_pins[15]	3106042	1			T22	1		T23	58		T24	47
all_pins[16]	3106042	1			T22	1		T23	58		T24	47
all_pins[17]	3106042	1			T22	1		T23	58		T24	47
all_pins[18]	3106042	1			T22	1		T23	58		T24	47
all_pins[19]	3106042	1			T22	1		T23	58		T24	47
all_pins[20]	3106042	1			T22	1		T23	58		T24	47
all_pins[21]	3106042	1			T22	1		T23	58		T24	47
all_pins[22]	3106042	1			T22	1		T23	58		T24	47
all_pins[23]	3106042	1			T22	1		T23	58		T24	47
all_pins[24]	3106042	1			T22	1		T23	58		T24	47
all_pins[25]	3106042	1			T22	1		T23	58		T24	47
all_pins[26]	3106042	1			T22	1		T23	58		T24	47
all_pins[27]	3106042	1			T22	1		T23	58		T24	47
all_pins[28]	3106042	1			T22	1		T23	58		T24	47
all_pins[29]	3106042	1			T22	1		T23	58		T24	47
all_pins[30]	3106042	1			T22	1		T23	58		T24	47
all_pins[31]	3106042	1			T22	1		T23	58		T24	47

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	61745873	1			T22	32		T23	1580		T24	849
values[0x1]	37647471	1			T23	276		T24	655		T25	9369
transitions[0x0=>0x1]	22554608	1			T23	182		T24	351		T25	5493
transitions[0x1=>0x0]	22554442	1			T23	182		T24	350		T25	5492

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1924431	1			T22	1		T23	50		T24	33
all_pins[0]	values[0x1]	1181611	1			T23	8		T24	14		T25	289
all_pins[0]	transitions[0x0=>0x1]	728379	1			T23	6		T24	7		T25	199
all_pins[0]	transitions[0x1=>0x0]	726433	1			T23	6		T24	19		T25	165
all_pins[1]	values[0x0]	1926896	1			T22	1		T23	49		T24	27
all_pins[1]	values[0x1]	1179146	1			T23	9		T24	20		T25	378
all_pins[1]	transitions[0x0=>0x1]	702434	1			T23	8		T24	15		T25	235
all_pins[1]	transitions[0x1=>0x0]	704899	1			T23	7		T24	9		T25	146
all_pins[2]	values[0x0]	1932265	1			T22	1		T23	47		T24	25
all_pins[2]	values[0x1]	1173777	1			T23	11		T24	22		T25	353
all_pins[2]	transitions[0x0=>0x1]	702210	1			T23	7		T24	12		T25	176
all_pins[2]	transitions[0x1=>0x0]	707579	1			T23	5		T24	10		T25	201
all_pins[3]	values[0x0]	1930024	1			T22	1		T23	42		T24	32
all_pins[3]	values[0x1]	1176018	1			T23	16		T24	15		T25	314
all_pins[3]	transitions[0x0=>0x1]	704420	1			T23	12		T24	6		T25	175
all_pins[3]	transitions[0x1=>0x0]	702179	1			T23	7		T24	13		T25	214
all_pins[4]	values[0x0]	1926442	1			T22	1		T23	48		T24	24
all_pins[4]	values[0x1]	1179600	1			T23	10		T24	23		T25	340
all_pins[4]	transitions[0x0=>0x1]	706101	1			T23	3		T24	17		T25	163
all_pins[4]	transitions[0x1=>0x0]	702519	1			T23	9		T24	9		T25	137
all_pins[5]	values[0x0]	1934137	1			T22	1		T23	50		T24	32
all_pins[5]	values[0x1]	1171905	1			T23	8		T24	15		T25	252
all_pins[5]	transitions[0x0=>0x1]	699905	1			T24	7		T25	124		T1	1452
all_pins[5]	transitions[0x1=>0x0]	707600	1			T23	2		T24	15		T25	212
all_pins[6]	values[0x0]	1928738	1			T22	1		T23	51		T24	31
all_pins[6]	values[0x1]	1177304	1			T23	7		T24	16		T25	245
all_pins[6]	transitions[0x0=>0x1]	706867	1			T23	1		T24	11		T25	132
all_pins[6]	transitions[0x1=>0x0]	701468	1			T23	2		T24	10		T25	139
all_pins[7]	values[0x0]	1932661	1			T22	1		T23	55		T24	15
all_pins[7]	values[0x1]	1173381	1			T23	3		T24	32		T25	325
all_pins[7]	transitions[0x0=>0x1]	701397	1			T23	3		T24	25		T25	193
all_pins[7]	transitions[0x1=>0x0]	705320	1			T23	7		T24	9		T25	113
all_pins[8]	values[0x0]	1927394	1			T22	1		T23	52		T24	29
all_pins[8]	values[0x1]	1178648	1			T23	6		T24	18		T25	344
all_pins[8]	transitions[0x0=>0x1]	705540	1			T23	6		T24	6		T25	174
all_pins[8]	transitions[0x1=>0x0]	700273	1			T23	3		T24	20		T25	155
all_pins[9]	values[0x0]	1933994	1			T22	1		T23	40		T24	30
all_pins[9]	values[0x1]	1172048	1			T23	18		T24	17		T25	342
all_pins[9]	transitions[0x0=>0x1]	698817	1			T23	14		T24	9		T25	187
all_pins[9]	transitions[0x1=>0x0]	705417	1			T23	2		T24	10		T25	189
all_pins[10]	values[0x0]	1926175	1			T22	1		T23	47		T24	28
all_pins[10]	values[0x1]	1179867	1			T23	11		T24	19		T25	283
all_pins[10]	transitions[0x0=>0x1]	708835	1			T23	3		T24	10		T25	171
all_pins[10]	transitions[0x1=>0x0]	701016	1			T23	10		T24	8		T25	230
all_pins[11]	values[0x0]	1931500	1			T22	1		T23	52		T24	31
all_pins[11]	values[0x1]	1174542	1			T23	6		T24	16		T25	259
all_pins[11]	transitions[0x0=>0x1]	703225	1			T23	2		T24	7		T25	177
all_pins[11]	transitions[0x1=>0x0]	708550	1			T23	7		T24	10		T25	201
all_pins[12]	values[0x0]	1928760	1			T22	1		T23	56		T24	29
all_pins[12]	values[0x1]	1177282	1			T23	2		T24	18		T25	232
all_pins[12]	transitions[0x0=>0x1]	706431	1			T23	2		T24	12		T25	130
all_pins[12]	transitions[0x1=>0x0]	703691	1			T23	6		T24	10		T25	157
all_pins[13]	values[0x0]	1931522	1			T22	1		T23	46		T24	31
all_pins[13]	values[0x1]	1174520	1			T23	12		T24	16		T25	208
all_pins[13]	transitions[0x0=>0x1]	701795	1			T23	12		T24	8		T25	134
all_pins[13]	transitions[0x1=>0x0]	704557	1			T23	2		T24	10		T25	158
all_pins[14]	values[0x0]	1934548	1			T22	1		T23	46		T24	26
all_pins[14]	values[0x1]	1171494	1			T23	12		T24	21		T25	273
all_pins[14]	transitions[0x0=>0x1]	702741	1			T23	6		T24	11		T25	190
all_pins[14]	transitions[0x1=>0x0]	705767	1			T23	6		T24	6		T25	125
all_pins[15]	values[0x0]	1930255	1			T22	1		T23	52		T24	28
all_pins[15]	values[0x1]	1175787	1			T23	6		T24	19		T25	324
all_pins[15]	transitions[0x0=>0x1]	705387	1			T23	6		T24	14		T25	225
all_pins[15]	transitions[0x1=>0x0]	701094	1			T23	12		T24	16		T25	174
all_pins[16]	values[0x0]	1931052	1			T22	1		T23	51		T24	27
all_pins[16]	values[0x1]	1174990	1			T23	7		T24	20		T25	308
all_pins[16]	transitions[0x0=>0x1]	704771	1			T23	7		T24	10		T25	215
all_pins[16]	transitions[0x1=>0x0]	705568	1			T23	6		T24	9		T25	231
all_pins[17]	values[0x0]	1929168	1			T22	1		T23	50		T24	24
all_pins[17]	values[0x1]	1176874	1			T23	8		T24	23		T25	251
all_pins[17]	transitions[0x0=>0x1]	704893	1			T23	6		T24	13		T25	161
all_pins[17]	transitions[0x1=>0x0]	703009	1			T23	5		T24	10		T25	218
all_pins[18]	values[0x0]	1926655	1			T22	1		T23	52		T24	25
all_pins[18]	values[0x1]	1179387	1			T23	6		T24	22		T25	287
all_pins[18]	transitions[0x0=>0x1]	706172	1			T23	5		T24	8		T25	164
all_pins[18]	transitions[0x1=>0x0]	703659	1			T23	7		T24	9		T25	128
all_pins[19]	values[0x0]	1931652	1			T22	1		T23	49		T24	21
all_pins[19]	values[0x1]	1174390	1			T23	9		T24	26		T25	305
all_pins[19]	transitions[0x0=>0x1]	700457	1			T23	5		T24	15		T25	202
all_pins[19]	transitions[0x1=>0x0]	705454	1			T23	2		T24	11		T25	184
all_pins[20]	values[0x0]	1931158	1			T22	1		T23	50		T24	22
all_pins[20]	values[0x1]	1174884	1			T23	8		T24	25		T25	364
all_pins[20]	transitions[0x0=>0x1]	705184	1			T23	5		T24	9		T25	204
all_pins[20]	transitions[0x1=>0x0]	704690	1			T23	6		T24	10		T25	145
all_pins[21]	values[0x0]	1929883	1			T22	1		T23	53		T24	31
all_pins[21]	values[0x1]	1176159	1			T23	5		T24	16		T25	260
all_pins[21]	transitions[0x0=>0x1]	704398	1			T23	5		T24	4		T25	164
all_pins[21]	transitions[0x1=>0x0]	703123	1			T23	8		T24	13		T25	268
all_pins[22]	values[0x0]	1928508	1			T22	1		T23	54		T24	29
all_pins[22]	values[0x1]	1177534	1			T23	4		T24	18		T25	269
all_pins[22]	transitions[0x0=>0x1]	704217	1			T23	4		T24	10		T25	164
all_pins[22]	transitions[0x1=>0x0]	702842	1			T23	5		T24	8		T25	155
all_pins[23]	values[0x0]	1930529	1			T22	1		T23	51		T24	27
all_pins[23]	values[0x1]	1175513	1			T23	7		T24	20		T25	265
all_pins[23]	transitions[0x0=>0x1]	702785	1			T23	7		T24	14		T25	183
all_pins[23]	transitions[0x1=>0x0]	704806	1			T23	4		T24	12		T25	187
all_pins[24]	values[0x0]	1935584	1			T22	1		T23	54		T24	21
all_pins[24]	values[0x1]	1170458	1			T23	4		T24	26		T25	240
all_pins[24]	transitions[0x0=>0x1]	698231	1			T23	1		T24	14		T25	123
all_pins[24]	transitions[0x1=>0x0]	703286	1			T23	4		T24	8		T25	148
all_pins[25]	values[0x0]	1929793	1			T22	1		T23	48		T24	21
all_pins[25]	values[0x1]	1176249	1			T23	10		T24	26		T25	327
all_pins[25]	transitions[0x0=>0x1]	706459	1			T23	7		T24	12		T25	212
all_pins[25]	transitions[0x1=>0x0]	700668	1			T23	1		T24	12		T25	125
all_pins[26]	values[0x0]	1925557	1			T22	1		T23	52		T24	25
all_pins[26]	values[0x1]	1180485	1			T23	6		T24	22		T25	283
all_pins[26]	transitions[0x0=>0x1]	706945	1			T23	2		T24	9		T25	127
all_pins[26]	transitions[0x1=>0x0]	702709	1			T23	6		T24	13		T25	171
all_pins[27]	values[0x0]	1927474	1			T22	1		T23	50		T24	26
all_pins[27]	values[0x1]	1178568	1			T23	8		T24	21		T25	328
all_pins[27]	transitions[0x0=>0x1]	704913	1			T23	8		T24	8		T25	210
all_pins[27]	transitions[0x1=>0x0]	706830	1			T23	6		T24	9		T25	165
all_pins[28]	values[0x0]	1925115	1			T22	1		T23	47		T24	26
all_pins[28]	values[0x1]	1180927	1			T23	11		T24	21		T25	291
all_pins[28]	transitions[0x0=>0x1]	705995	1			T23	9		T24	11		T25	142
all_pins[28]	transitions[0x1=>0x0]	703636	1			T23	6		T24	11		T25	179
all_pins[29]	values[0x0]	1930095	1			T22	1		T23	41		T24	26
all_pins[29]	values[0x1]	1175947	1			T23	17		T24	21		T25	289
all_pins[29]	transitions[0x0=>0x1]	701912	1			T23	10		T24	10		T25	147
all_pins[29]	transitions[0x1=>0x0]	706892	1			T23	4		T24	10		T25	149
all_pins[30]	values[0x0]	1927697	1			T22	1		T23	45		T24	27
all_pins[30]	values[0x1]	1178345	1			T23	13		T24	20		T25	285
all_pins[30]	transitions[0x0=>0x1]	706891	1			T23	4		T24	12		T25	137
all_pins[30]	transitions[0x1=>0x0]	704493	1			T23	8		T24	13		T25	141
all_pins[31]	values[0x0]	1926211	1			T22	1		T23	50		T24	20
all_pins[31]	values[0x1]	1179831	1			T23	8		T24	27		T25	256
all_pins[31]	transitions[0x0=>0x1]	705901	1			T23	6		T24	15		T25	153
all_pins[31]	transitions[0x1=>0x0]	704415	1			T23	11		T24	8		T25	182