Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	10766331	1			T22	155		T23	98		T24	648
all_values[1]	10766331	1			T22	155		T23	98		T24	648
all_values[2]	10766331	1			T22	155		T23	98		T24	648
all_values[3]	10766331	1			T22	155		T23	98		T24	648
all_values[4]	10766331	1			T22	155		T23	98		T24	648
all_values[5]	10766331	1			T22	155		T23	98		T24	648
all_values[6]	10766331	1			T22	155		T23	98		T24	648
all_values[7]	10766331	1			T22	155		T23	98		T24	648
all_values[8]	10766331	1			T22	155		T23	98		T24	648
all_values[9]	10766331	1			T22	155		T23	98		T24	648
all_values[10]	10766331	1			T22	155		T23	98		T24	648
all_values[11]	10766331	1			T22	155		T23	98		T24	648
all_values[12]	10766331	1			T22	155		T23	98		T24	648
all_values[13]	10766331	1			T22	155		T23	98		T24	648
all_values[14]	10766331	1			T22	155		T23	98		T24	648
all_values[15]	10766331	1			T22	155		T23	98		T24	648
all_values[16]	10766331	1			T22	155		T23	98		T24	648
all_values[17]	10766331	1			T22	155		T23	98		T24	648
all_values[18]	10766331	1			T22	155		T23	98		T24	648
all_values[19]	10766331	1			T22	155		T23	98		T24	648
all_values[20]	10766331	1			T22	155		T23	98		T24	648
all_values[21]	10766331	1			T22	155		T23	98		T24	648
all_values[22]	10766331	1			T22	155		T23	98		T24	648
all_values[23]	10766331	1			T22	155		T23	98		T24	648
all_values[24]	10766331	1			T22	155		T23	98		T24	648
all_values[25]	10766331	1			T22	155		T23	98		T24	648
all_values[26]	10766331	1			T22	155		T23	98		T24	648
all_values[27]	10766331	1			T22	155		T23	98		T24	648
all_values[28]	10766331	1			T22	155		T23	98		T24	648
all_values[29]	10766331	1			T22	155		T23	98		T24	648
all_values[30]	10766331	1			T22	155		T23	98		T24	648
all_values[31]	10766331	1			T22	155		T23	98		T24	648

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205214588

1

T22

4960

T23

2213

T24

20736

auto[1]

139308004

1

T23

923

T25

28191

T1

295115

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93001578

1

T22

4960

T23

1968

T24

20736

auto[1]

251521014

1

T23

1168

T25

48898

T1

534025

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340882838

1

T22

4960

T23

3005

T24

20736

auto[1]

3639754

1

T23

131

T1

6119

T12

18113

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2482613	1			T22	155		T23	50		T24	648
all_values[0]	auto[0]	auto[0]	auto[1]	3859216	1			T23	22		T25	761		T1	8000
all_values[0]	auto[0]	auto[1]	auto[0]	428987	1			T23	12		T25	60		T1	1032
all_values[0]	auto[0]	auto[1]	auto[1]	3881420	1			T23	10		T25	815		T1	8196
all_values[0]	auto[1]	auto[0]	auto[1]	56745	1			T23	3		T1	93		T12	273
all_values[0]	auto[1]	auto[1]	auto[1]	57350	1			T23	1		T1	91		T12	300
all_values[1]	auto[0]	auto[0]	auto[0]	2479637	1			T22	155		T23	37		T24	648
all_values[1]	auto[0]	auto[0]	auto[1]	3862157	1			T23	19		T25	472		T1	8569
all_values[1]	auto[0]	auto[1]	auto[0]	423659	1			T23	29		T25	99		T1	663
all_values[1]	auto[0]	auto[1]	auto[1]	3887116	1			T23	11		T25	1070		T1	8001
all_values[1]	auto[1]	auto[0]	auto[1]	57194	1			T23	2		T1	102		T12	289
all_values[1]	auto[1]	auto[1]	auto[1]	56568	1			T1	79		T12	292		T2	47
all_values[2]	auto[0]	auto[0]	auto[0]	2480249	1			T22	155		T23	33		T24	648
all_values[2]	auto[0]	auto[0]	auto[1]	3887571	1			T23	28		T25	626		T1	8076
all_values[2]	auto[0]	auto[1]	auto[0]	425816	1			T23	17		T25	70		T1	843
all_values[2]	auto[0]	auto[1]	auto[1]	3858721	1			T23	14		T25	942		T1	7992
all_values[2]	auto[1]	auto[0]	auto[1]	56789	1			T23	5		T1	94		T12	268
all_values[2]	auto[1]	auto[1]	auto[1]	57185	1			T23	1		T1	103		T12	314
all_values[3]	auto[0]	auto[0]	auto[0]	2481474	1			T22	155		T23	46		T24	648
all_values[3]	auto[0]	auto[0]	auto[1]	3874497	1			T23	12		T25	805		T1	8062
all_values[3]	auto[0]	auto[1]	auto[0]	426680	1			T23	11		T25	52		T1	820
all_values[3]	auto[0]	auto[1]	auto[1]	3870083	1			T23	25		T25	808		T1	8220
all_values[3]	auto[1]	auto[0]	auto[1]	57076	1			T23	3		T1	92		T12	278
all_values[3]	auto[1]	auto[1]	auto[1]	56521	1			T23	1		T1	94		T12	285
all_values[4]	auto[0]	auto[0]	auto[0]	2477857	1			T22	155		T23	44		T24	648
all_values[4]	auto[0]	auto[0]	auto[1]	3893887	1			T23	23		T25	510		T1	7952
all_values[4]	auto[0]	auto[1]	auto[0]	423574	1			T23	15		T25	113		T1	937
all_values[4]	auto[0]	auto[1]	auto[1]	3857214	1			T23	12		T25	982		T1	8494
all_values[4]	auto[1]	auto[0]	auto[1]	57126	1			T23	3		T1	99		T12	279
all_values[4]	auto[1]	auto[1]	auto[1]	56673	1			T23	1		T1	111		T12	280
all_values[5]	auto[0]	auto[0]	auto[0]	2478331	1			T22	155		T23	47		T24	648
all_values[5]	auto[0]	auto[0]	auto[1]	3880789	1			T23	25		T25	869		T1	7817
all_values[5]	auto[0]	auto[1]	auto[0]	425438	1			T23	13		T25	102		T1	731
all_values[5]	auto[0]	auto[1]	auto[1]	3868450	1			T23	10		T25	675		T1	8871
all_values[5]	auto[1]	auto[0]	auto[1]	56982	1			T23	2		T1	95		T12	317
all_values[5]	auto[1]	auto[1]	auto[1]	56341	1			T23	1		T1	104		T12	254
all_values[6]	auto[0]	auto[0]	auto[0]	2478321	1			T22	155		T23	66		T24	648
all_values[6]	auto[0]	auto[0]	auto[1]	3870138	1			T23	12		T25	777		T1	8408
all_values[6]	auto[0]	auto[1]	auto[0]	426337	1			T23	11		T25	165		T1	759
all_values[6]	auto[0]	auto[1]	auto[1]	3877535	1			T23	6		T25	653		T1	8150
all_values[6]	auto[1]	auto[0]	auto[1]	57322	1			T23	1		T1	91		T12	288
all_values[6]	auto[1]	auto[1]	auto[1]	56678	1			T23	2		T1	130		T12	285
all_values[7]	auto[0]	auto[0]	auto[0]	2474585	1			T22	155		T23	55		T24	648
all_values[7]	auto[0]	auto[0]	auto[1]	3902248	1			T23	21		T25	681		T1	8335
all_values[7]	auto[0]	auto[1]	auto[0]	428788	1			T23	10		T25	106		T1	691
all_values[7]	auto[0]	auto[1]	auto[1]	3847410	1			T23	6		T25	868		T1	8370
all_values[7]	auto[1]	auto[0]	auto[1]	56770	1			T23	5		T1	99		T12	264
all_values[7]	auto[1]	auto[1]	auto[1]	56530	1			T23	1		T1	83		T12	272
all_values[8]	auto[0]	auto[0]	auto[0]	2480747	1			T22	155		T23	48		T24	648
all_values[8]	auto[0]	auto[0]	auto[1]	3850946	1			T23	26		T25	605		T1	8426
all_values[8]	auto[0]	auto[1]	auto[0]	428809	1			T23	18		T25	125		T1	863
all_values[8]	auto[0]	auto[1]	auto[1]	3891794	1			T23	4		T25	927		T1	8082
all_values[8]	auto[1]	auto[0]	auto[1]	56942	1			T1	112		T12	296		T2	34
all_values[8]	auto[1]	auto[1]	auto[1]	57093	1			T23	2		T1	89		T12	277
all_values[9]	auto[0]	auto[0]	auto[0]	2477813	1			T22	155		T23	38		T24	648
all_values[9]	auto[0]	auto[0]	auto[1]	3878956	1			T23	15		T25	700		T1	8073
all_values[9]	auto[0]	auto[1]	auto[0]	423719	1			T23	15		T25	64		T1	923
all_values[9]	auto[0]	auto[1]	auto[1]	3872000	1			T23	27		T25	900		T1	8391
all_values[9]	auto[1]	auto[0]	auto[1]	57354	1			T23	2		T1	104		T12	272
all_values[9]	auto[1]	auto[1]	auto[1]	56489	1			T23	1		T1	96		T12	303
all_values[10]	auto[0]	auto[0]	auto[0]	2483775	1			T22	155		T23	44		T24	648
all_values[10]	auto[0]	auto[0]	auto[1]	3867795	1			T23	15		T25	834		T1	7177
all_values[10]	auto[0]	auto[1]	auto[0]	430494	1			T23	19		T25	85		T1	893
all_values[10]	auto[0]	auto[1]	auto[1]	3870676	1			T23	18		T25	703		T1	9231
all_values[10]	auto[1]	auto[0]	auto[1]	56752	1			T23	2		T1	91		T12	293
all_values[10]	auto[1]	auto[1]	auto[1]	56839	1			T1	97		T12	306		T2	40
all_values[11]	auto[0]	auto[0]	auto[0]	2483154	1			T22	155		T23	51		T24	648
all_values[11]	auto[0]	auto[0]	auto[1]	3860688	1			T23	21		T25	710		T1	8175
all_values[11]	auto[0]	auto[1]	auto[0]	427212	1			T23	15		T25	187		T1	705
all_values[11]	auto[0]	auto[1]	auto[1]	3881496	1			T23	9		T25	698		T1	8478
all_values[11]	auto[1]	auto[0]	auto[1]	57127	1			T23	2		T1	101		T12	288
all_values[11]	auto[1]	auto[1]	auto[1]	56654	1			T1	113		T12	290		T2	40
all_values[12]	auto[0]	auto[0]	auto[0]	2484226	1			T22	155		T23	47		T24	648
all_values[12]	auto[0]	auto[0]	auto[1]	3871400	1			T23	33		T25	836		T1	7884
all_values[12]	auto[0]	auto[1]	auto[0]	424742	1			T23	9		T25	117		T1	768
all_values[12]	auto[0]	auto[1]	auto[1]	3872139	1			T23	5		T25	648		T1	8669
all_values[12]	auto[1]	auto[0]	auto[1]	57186	1			T23	4		T1	84		T12	290
all_values[12]	auto[1]	auto[1]	auto[1]	56638	1			T1	95		T12	261		T2	31
all_values[13]	auto[0]	auto[0]	auto[0]	2482210	1			T22	155		T23	51		T24	648
all_values[13]	auto[0]	auto[0]	auto[1]	3876818	1			T23	10		T25	1000		T1	6967
all_values[13]	auto[0]	auto[1]	auto[0]	425551	1			T23	23		T25	62		T1	1017
all_values[13]	auto[0]	auto[1]	auto[1]	3867681	1			T23	9		T25	513		T1	9490
all_values[13]	auto[1]	auto[0]	auto[1]	57488	1			T23	3		T1	108		T12	300
all_values[13]	auto[1]	auto[1]	auto[1]	56583	1			T23	2		T1	76		T12	268
all_values[14]	auto[0]	auto[0]	auto[0]	2484499	1			T22	155		T23	43		T24	648
all_values[14]	auto[0]	auto[0]	auto[1]	3891696	1			T23	21		T25	811		T1	8731
all_values[14]	auto[0]	auto[1]	auto[0]	428197	1			T23	19		T25	75		T1	959
all_values[14]	auto[0]	auto[1]	auto[1]	3848434	1			T23	12		T25	735		T1	7571
all_values[14]	auto[1]	auto[0]	auto[1]	57005	1			T23	2		T1	91		T12	291
all_values[14]	auto[1]	auto[1]	auto[1]	56500	1			T23	1		T1	97		T12	272
all_values[15]	auto[0]	auto[0]	auto[0]	2484206	1			T22	155		T23	47		T24	648
all_values[15]	auto[0]	auto[0]	auto[1]	3860681	1			T23	11		T25	730		T1	8144
all_values[15]	auto[0]	auto[1]	auto[0]	430342	1			T23	24		T25	53		T1	1029
all_values[15]	auto[0]	auto[1]	auto[1]	3877565	1			T23	10		T25	827		T1	8179
all_values[15]	auto[1]	auto[0]	auto[1]	57107	1			T23	4		T1	86		T12	278
all_values[15]	auto[1]	auto[1]	auto[1]	56430	1			T23	2		T1	85		T12	267
all_values[16]	auto[0]	auto[0]	auto[0]	2477546	1			T22	155		T23	34		T24	648
all_values[16]	auto[0]	auto[0]	auto[1]	3871272	1			T23	37		T25	646		T1	8087
all_values[16]	auto[0]	auto[1]	auto[0]	431023	1			T23	13		T25	99		T1	706
all_values[16]	auto[0]	auto[1]	auto[1]	3872904	1			T23	9		T25	877		T1	8431
all_values[16]	auto[1]	auto[0]	auto[1]	57414	1			T23	4		T1	100		T12	259
all_values[16]	auto[1]	auto[1]	auto[1]	56172	1			T23	1		T1	98		T12	298
all_values[17]	auto[0]	auto[0]	auto[0]	2478400	1			T22	155		T23	36		T24	648
all_values[17]	auto[0]	auto[0]	auto[1]	3890810	1			T23	18		T25	884		T1	8373
all_values[17]	auto[0]	auto[1]	auto[0]	417620	1			T23	28		T25	66		T1	742
all_values[17]	auto[0]	auto[1]	auto[1]	3865606	1			T23	13		T25	639		T1	8143
all_values[17]	auto[1]	auto[0]	auto[1]	57199	1			T23	2		T1	88		T12	263
all_values[17]	auto[1]	auto[1]	auto[1]	56696	1			T23	1		T1	112		T12	280
all_values[18]	auto[0]	auto[0]	auto[0]	2471856	1			T22	155		T23	42		T24	648
all_values[18]	auto[0]	auto[0]	auto[1]	3863305	1			T23	31		T25	773		T1	7960
all_values[18]	auto[0]	auto[1]	auto[0]	431644	1			T23	8		T25	57		T1	820
all_values[18]	auto[0]	auto[1]	auto[1]	3885570	1			T23	9		T25	783		T1	8504
all_values[18]	auto[1]	auto[0]	auto[1]	56979	1			T23	7		T1	89		T12	287
all_values[18]	auto[1]	auto[1]	auto[1]	56977	1			T23	1		T1	83		T12	290
all_values[19]	auto[0]	auto[0]	auto[0]	2480416	1			T22	155		T23	37		T24	648
all_values[19]	auto[0]	auto[0]	auto[1]	3879434	1			T23	30		T25	690		T1	8165
all_values[19]	auto[0]	auto[1]	auto[0]	426356	1			T23	7		T25	110		T1	831
all_values[19]	auto[0]	auto[1]	auto[1]	3866845	1			T23	17		T25	817		T1	8472
all_values[19]	auto[1]	auto[0]	auto[1]	56734	1			T23	5		T1	100		T12	265
all_values[19]	auto[1]	auto[1]	auto[1]	56546	1			T23	2		T1	86		T12	287
all_values[20]	auto[0]	auto[0]	auto[0]	2481012	1			T22	155		T23	45		T24	648
all_values[20]	auto[0]	auto[0]	auto[1]	3861883	1			T23	16		T25	644		T1	8176
all_values[20]	auto[0]	auto[1]	auto[0]	427402	1			T23	23		T25	67		T1	837
all_values[20]	auto[0]	auto[1]	auto[1]	3882263	1			T23	11		T25	933		T1	8306
all_values[20]	auto[1]	auto[0]	auto[1]	57582	1			T23	1		T1	101		T12	287
all_values[20]	auto[1]	auto[1]	auto[1]	56189	1			T23	2		T1	82		T12	262
all_values[21]	auto[0]	auto[0]	auto[0]	2475588	1			T22	155		T23	41		T24	648
all_values[21]	auto[0]	auto[0]	auto[1]	3897885	1			T23	31		T25	786		T1	9161
all_values[21]	auto[0]	auto[1]	auto[0]	430227	1			T23	11		T25	100		T1	756
all_values[21]	auto[0]	auto[1]	auto[1]	3849087	1			T23	9		T25	704		T1	7305
all_values[21]	auto[1]	auto[0]	auto[1]	56645	1			T23	5		T1	97		T12	296
all_values[21]	auto[1]	auto[1]	auto[1]	56899	1			T23	1		T1	85		T12	279
all_values[22]	auto[0]	auto[0]	auto[0]	2485298	1			T22	155		T23	40		T24	648
all_values[22]	auto[0]	auto[0]	auto[1]	3881187	1			T23	34		T25	797		T1	7788
all_values[22]	auto[0]	auto[1]	auto[0]	428500	1			T23	9		T25	99		T1	740
all_values[22]	auto[0]	auto[1]	auto[1]	3857682	1			T23	9		T25	732		T1	8820
all_values[22]	auto[1]	auto[0]	auto[1]	57134	1			T23	6		T1	95		T12	293
all_values[22]	auto[1]	auto[1]	auto[1]	56530	1			T1	104		T12	284		T2	31
all_values[23]	auto[0]	auto[0]	auto[0]	2487221	1			T22	155		T23	39		T24	648
all_values[23]	auto[0]	auto[0]	auto[1]	3878361	1			T23	23		T25	849		T1	8975
all_values[23]	auto[0]	auto[1]	auto[0]	422239	1			T23	23		T25	83		T1	671
all_values[23]	auto[0]	auto[1]	auto[1]	3864575	1			T23	7		T25	703		T1	7759
all_values[23]	auto[1]	auto[0]	auto[1]	57062	1			T23	4		T1	102		T12	284
all_values[23]	auto[1]	auto[1]	auto[1]	56873	1			T23	2		T1	106		T12	284
all_values[24]	auto[0]	auto[0]	auto[0]	2487290	1			T22	155		T23	55		T24	648
all_values[24]	auto[0]	auto[0]	auto[1]	3879878	1			T23	15		T25	853		T1	8122
all_values[24]	auto[0]	auto[1]	auto[0]	421555	1			T23	17		T25	73		T1	907
all_values[24]	auto[0]	auto[1]	auto[1]	3863879	1			T23	6		T25	686		T1	8337
all_values[24]	auto[1]	auto[0]	auto[1]	57337	1			T23	4		T1	102		T12	291
all_values[24]	auto[1]	auto[1]	auto[1]	56392	1			T23	1		T1	105		T12	285
all_values[25]	auto[0]	auto[0]	auto[0]	2478987	1			T22	155		T23	46		T24	648
all_values[25]	auto[0]	auto[0]	auto[1]	3879754	1			T23	24		T25	654		T1	8289
all_values[25]	auto[0]	auto[1]	auto[0]	428644	1			T23	12		T25	126		T1	1000
all_values[25]	auto[0]	auto[1]	auto[1]	3865305	1			T23	15		T25	889		T1	8206
all_values[25]	auto[1]	auto[0]	auto[1]	56753	1			T23	1		T1	75		T12	261
all_values[25]	auto[1]	auto[1]	auto[1]	56888	1			T1	103		T12	272		T2	36
all_values[26]	auto[0]	auto[0]	auto[0]	2483495	1			T22	155		T23	56		T24	648
all_values[26]	auto[0]	auto[0]	auto[1]	3845827	1			T23	20		T25	850		T1	8495
all_values[26]	auto[0]	auto[1]	auto[0]	425451	1			T23	13		T25	93		T1	714
all_values[26]	auto[0]	auto[1]	auto[1]	3897934	1			T23	7		T25	690		T1	8061
all_values[26]	auto[1]	auto[0]	auto[1]	57404	1			T23	1		T1	90		T12	269
all_values[26]	auto[1]	auto[1]	auto[1]	56220	1			T23	1		T1	91		T12	293
all_values[27]	auto[0]	auto[0]	auto[0]	2477924	1			T22	155		T23	54		T24	648
all_values[27]	auto[0]	auto[0]	auto[1]	3865742	1			T23	12		T25	593		T1	8222
all_values[27]	auto[0]	auto[1]	auto[0]	425460	1			T23	14		T25	102		T1	783
all_values[27]	auto[0]	auto[1]	auto[1]	3883265	1			T23	13		T25	934		T1	8424
all_values[27]	auto[1]	auto[0]	auto[1]	56908	1			T23	4		T1	85		T12	307
all_values[27]	auto[1]	auto[1]	auto[1]	57032	1			T23	1		T1	100		T12	262
all_values[28]	auto[0]	auto[0]	auto[0]	2472335	1			T22	155		T23	49		T24	648
all_values[28]	auto[0]	auto[0]	auto[1]	3887658	1			T23	17		T25	763		T1	8297
all_values[28]	auto[0]	auto[1]	auto[0]	425077	1			T23	15		T25	52		T1	875
all_values[28]	auto[0]	auto[1]	auto[1]	3867265	1			T23	13		T25	765		T1	8222
all_values[28]	auto[1]	auto[0]	auto[1]	56833	1			T23	2		T1	86		T12	271
all_values[28]	auto[1]	auto[1]	auto[1]	57163	1			T23	2		T1	90		T12	284
all_values[29]	auto[0]	auto[0]	auto[0]	2481437	1			T22	155		T23	36		T24	648
all_values[29]	auto[0]	auto[0]	auto[1]	3880222	1			T23	6		T25	669		T1	8633
all_values[29]	auto[0]	auto[1]	auto[0]	426508	1			T23	33		T25	152		T1	870
all_values[29]	auto[0]	auto[1]	auto[1]	3864091	1			T23	19		T25	786		T1	7804
all_values[29]	auto[1]	auto[0]	auto[1]	57119	1			T23	2		T1	68		T12	304
all_values[29]	auto[1]	auto[1]	auto[1]	56954	1			T23	2		T1	125		T12	278
all_values[30]	auto[0]	auto[0]	auto[0]	2473018	1			T22	155		T23	46		T24	648
all_values[30]	auto[0]	auto[0]	auto[1]	3895098	1			T23	11		T25	714		T1	9412
all_values[30]	auto[0]	auto[1]	auto[0]	421376	1			T23	18		T25	102		T1	672
all_values[30]	auto[0]	auto[1]	auto[1]	3863361	1			T23	19		T25	812		T1	7320
all_values[30]	auto[1]	auto[0]	auto[1]	56935	1			T23	2		T1	86		T12	267
all_values[30]	auto[1]	auto[1]	auto[1]	56543	1			T23	2		T1	114		T12	286
all_values[31]	auto[0]	auto[0]	auto[0]	2474045	1			T22	155		T23	52		T24	648
all_values[31]	auto[0]	auto[0]	auto[1]	3880761	1			T23	23		T25	821		T1	7378
all_values[31]	auto[0]	auto[1]	auto[0]	424586	1			T23	9		T25	90		T1	861
all_values[31]	auto[0]	auto[1]	auto[1]	3873334	1			T23	11		T25	671		T1	9078
all_values[31]	auto[1]	auto[0]	auto[1]	57460	1			T23	3		T1	93		T12	328
all_values[31]	auto[1]	auto[1]	auto[1]	56145	1			T1	93		T12	267		T2	33

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal