Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[1]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[2]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[3]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[4]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[5]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[6]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[7]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[8]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[9]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[10]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[11]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[12]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[13]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[14]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[15]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[16]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[17]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[18]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[19]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[20]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[21]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[22]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[23]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[24]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[25]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[26]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[27]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[28]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[29]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[30]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[31]	10591372	1			T22	277		T23	138		T24	648

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197945188

1

T22

2085

T23

2093

T24

10435

auto[1]

140978716

1

T22

6779

T23

2323

T24

10301

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

274329224

1

T22

8078

T23

4024

T24

20736

auto[1]

64594680

1

T22

786

T23

392

T1

153291

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255467700

1

T22

4709

T23

3391

T24

20736

auto[1]

83456204

1

T22

4155

T23

1025

T1

213167

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3943672	1			T22	10		T23	49		T24	355
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3023081	1			T22	74		T23	35		T24	293
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1012187	1			T22	13		T23	16		T1	2256
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1238419	1			T22	41		T23	3		T1	3809
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	365012	1			T22	129		T23	20		T1	293
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1009001	1			T22	10		T23	15		T1	2536
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3924240	1			T22	51		T23	67		T24	363
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3043431	1			T22	174		T23	33		T24	285
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1009305	1			T22	31		T23	3		T1	2489
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1241875	1			T22	3		T23	24		T1	3914
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	363876	1			T22	18		T23	9		T1	323
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1008645	1			T23	2		T1	2373		T11	127
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3924643	1			T22	30		T23	28		T24	288
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3037428	1			T22	115		T23	71		T24	360
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1014524	1			T22	17		T23	9		T1	2486
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1242616	1			T22	34		T23	3		T1	3648
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	366497	1			T22	75		T23	17		T1	343
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1005664	1			T22	6		T23	10		T1	2467
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3929896	1			T22	29		T23	34		T24	285
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3033179	1			T22	94		T23	75		T24	363
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1015653	1			T22	15		T23	10		T1	2225
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1235795	1			T22	26		T23	8		T1	3872
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	367008	1			T22	96		T23	4		T1	353
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1009841	1			T22	17		T23	7		T1	2343
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3937590	1			T22	15		T23	38		T24	352
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3032189	1			T22	41		T23	66		T24	296
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1019345	1			T22	6		T23	3		T1	2490
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1233034	1			T22	40		T23	19		T1	3964
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	362734	1			T22	150		T23	12		T1	351
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1006480	1			T22	25		T1	2427		T11	216
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3945616	1			T22	36		T23	43		T24	368
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3025644	1			T22	143		T23	57		T24	280
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1019968	1			T22	18		T23	10		T1	2377
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1232839	1			T22	12		T23	14		T1	3852
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	363696	1			T22	56		T23	4		T1	283
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1003609	1			T22	12		T23	10		T1	2413
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3943451	1			T22	32		T23	42		T24	279
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3023148	1			T22	149		T23	54		T24	369
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1016238	1			T22	17		T23	2		T1	2407
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1236100	1			T22	10		T23	21		T1	3764
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	364895	1			T22	69		T23	10		T1	323
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1007540	1			T23	9		T1	2564		T11	146
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3925834	1			T22	23		T23	39		T24	299
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3040112	1			T22	78		T23	40		T24	349
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1015139	1			T22	8		T23	7		T1	2445
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1239659	1			T22	30		T23	12		T1	3873
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	362003	1			T22	117		T23	29		T1	306
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1008625	1			T22	21		T23	11		T1	2214
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3928896	1			T22	17		T23	71		T24	358
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3038279	1			T22	124		T23	23		T24	290
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1015518	1			T22	9		T23	14		T1	2521
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1236713	1			T22	35		T23	17		T1	3851
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	364376	1			T22	84		T23	3		T1	417
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1007590	1			T22	8		T23	10		T1	2540
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3934609	1			T22	47		T23	50		T24	334
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3036557	1			T22	201		T23	43		T24	314
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1015840	1			T22	18		T23	13		T1	2628
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1236928	1			T23	16		T1	3740		T11	163
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	363122	1			T22	11		T23	12		T1	338
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1004316	1			T23	4		T1	2367		T11	180
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3930549	1			T22	13		T23	38		T24	286
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3039138	1			T22	69		T23	70		T24	362
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1014804	1			T22	8		T1	2445		T11	160
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1239287	1			T22	28		T23	4		T1	3989
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	362557	1			T22	144		T23	24		T1	360
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1005037	1			T22	15		T23	2		T1	2177
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3933685	1			T22	12		T23	28		T24	361
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3033889	1			T22	63		T23	69		T24	287
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1016127	1			T22	14		T1	2259		T11	167
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1234587	1			T22	35		T23	14		T1	4036
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	366414	1			T22	132		T23	22		T1	371
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1006670	1			T22	21		T23	5		T1	2420
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3927229	1			T22	5		T23	56		T24	264
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3038652	1			T22	30		T23	43		T24	384
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1016484	1			T22	2		T23	6		T1	2307
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1236417	1			T22	42		T23	27		T1	3991
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	364671	1			T22	167		T23	4		T1	363
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1007919	1			T22	31		T23	2		T1	2218
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3925475	1			T22	22		T23	41		T24	331
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3047653	1			T22	137		T23	65		T24	317
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1014112	1			T22	24		T23	9		T1	2246
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1235168	1			T22	25		T23	2		T1	4153
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	362581	1			T22	55		T23	10		T1	375
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1006383	1			T22	14		T23	11		T1	2454
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3925009	1			T22	8		T23	54		T24	380
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3043017	1			T22	52		T23	41		T24	268
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1017348	1			T22	7		T23	5		T1	2503
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1233572	1			T22	47		T23	14		T1	3852
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	365835	1			T22	148		T23	15		T1	377
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1006591	1			T22	15		T23	9		T1	2416
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3939790	1			T22	12		T23	13		T24	373
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3035431	1			T22	79		T23	86		T24	275
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1016487	1			T22	2		T23	4		T1	2469
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1228230	1			T22	42		T23	2		T1	3727
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	365352	1			T22	129		T23	20		T1	328
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1006082	1			T22	13		T23	13		T1	2290
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3927602	1			T22	39		T23	63		T24	387
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3039805	1			T22	178		T23	40		T24	261
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1011844	1			T22	21		T23	3		T1	2365
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1245063	1			T22	4		T23	16		T1	3849
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	364253	1			T22	35		T23	12		T1	335
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1002805	1			T23	4		T1	2306		T11	190
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3940797	1			T22	5		T23	48		T24	403
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3029425	1			T22	43		T23	49		T24	245
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1008562	1			T23	1		T1	2487		T11	144
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1242172	1			T22	44		T23	26		T1	3754
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	368267	1			T22	156		T23	12		T1	353
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1002149	1			T22	29		T23	2		T1	2502
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3926216	1			T22	4		T23	39		T24	353
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3039271	1			T22	42		T23	62		T24	295
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1010281	1			T22	2		T23	2		T1	2507
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1242186	1			T22	47		T23	13		T1	3740
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	367859	1			T22	154		T23	14		T1	346
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1005559	1			T22	28		T23	8		T1	2423
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3932588	1			T22	39		T23	46		T24	297
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3034125	1			T22	142		T23	62		T24	351
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1009727	1			T22	13		T23	2		T1	2216
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1245964	1			T22	16		T23	17		T1	3959
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	365785	1			T22	63		T23	10		T1	387
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1003183	1			T22	4		T23	1		T1	2397
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3931287	1			T22	24		T23	42		T24	338
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3040110	1			T22	130		T23	86		T24	310
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1013501	1			T22	21		T23	1		T1	2508
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1239013	1			T22	36		T23	1		T1	4118
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	365373	1			T22	59		T23	4		T1	378
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1002088	1			T22	7		T23	4		T1	2434
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3945719	1			T22	29		T23	69		T24	329
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3033452	1			T22	154		T23	40		T24	319
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1016825	1			T22	15		T23	4		T1	2226
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1231089	1			T22	20		T23	9		T1	4121
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	364771	1			T22	55		T23	13		T1	352
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	999516	1			T22	4		T23	3		T1	2307
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3933945	1			T22	48		T23	34		T24	293
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3039262	1			T22	187		T23	64		T24	355
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1012454	1			T22	28		T23	2		T1	2454
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1239887	1			T22	2		T23	11		T1	3595
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	365168	1			T22	12		T23	25		T1	319
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1000656	1			T23	2		T1	2256		T11	149
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3933265	1			T22	40		T23	51		T24	284
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3041173	1			T22	129		T23	55		T24	364
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1012114	1			T22	10		T23	5		T1	2386
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1239366	1			T22	21		T23	10		T1	3920
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	363267	1			T22	73		T23	17		T1	369
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1002187	1			T22	4		T1	2469		T11	193
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3937833	1			T22	37		T23	48		T24	268
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3032941	1			T22	140		T23	30		T24	380
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1010893	1			T22	18		T23	18		T1	2420
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1242044	1			T22	17		T23	10		T1	4140
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	362763	1			T22	53		T23	11		T1	399
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1004898	1			T22	12		T23	21		T1	2357
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3937949	1			T22	25		T23	58		T24	337
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3030793	1			T22	149		T23	47		T24	311
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1011962	1			T22	25		T23	5		T1	2336
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1237300	1			T22	18		T23	15		T1	4136
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	366522	1			T22	52		T23	11		T1	286
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1006846	1			T22	8		T23	2		T1	2394
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3947292	1			T22	13		T23	61		T24	293
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3026431	1			T22	55		T23	46		T24	355
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1012918	1			T22	3		T23	15		T1	2381
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1236529	1			T22	41		T23	9		T1	4102
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	363610	1			T22	154		T23	3		T1	408
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1004592	1			T22	11		T23	4		T1	2522
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3933365	1			T22	8		T23	27		T24	346
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3040530	1			T22	35		T23	68		T24	302
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1008193	1			T22	6		T1	2226		T11	166
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1240697	1			T22	47		T23	18		T1	4229
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	366673	1			T22	168		T23	17		T1	362
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1001914	1			T22	13		T23	8		T1	2390
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3937685	1			T22	53		T23	50		T24	320
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3034257	1			T22	184		T23	53		T24	328
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1013471	1			T22	23		T23	1		T1	2376
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1240252	1			T22	3		T23	20		T1	4108
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	361415	1			T22	14		T23	12		T1	378
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1004292	1			T23	2		T1	2333		T11	178
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3930387	1			T22	39		T23	41		T24	321
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3039635	1			T22	129		T23	58		T24	327
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1014337	1			T22	6		T23	18		T1	2402
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1241728	1			T22	13		T23	1		T1	3921
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	364358	1			T22	82		T23	13		T1	369
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1000927	1			T22	8		T23	7		T1	2490
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3942871	1			T22	12		T23	34		T24	280
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3035655	1			T22	65		T23	64		T24	368
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1009583	1			T22	2		T23	2		T1	2416
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1238973	1			T22	46		T23	28		T1	3742
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	363387	1			T22	135		T23	10		T1	366
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1000903	1			T22	17		T1	2440		T11	164
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3920918	1			T22	24		T23	67		T24	310
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3044328	1			T22	94		T23	27		T24	338
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1010032	1			T22	27		T23	10		T1	2480
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1246007	1			T22	30		T23	20		T1	3886
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	363691	1			T22	98		T23	10		T1	349
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1006396	1			T22	4		T23	4		T1	2313

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal