Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[1]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[2]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[3]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[4]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[5]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[6]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[7]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[8]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[9]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[10]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[11]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[12]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[13]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[14]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[15]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[16]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[17]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[18]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[19]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[20]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[21]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[22]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[23]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[24]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[25]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[26]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[27]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[28]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[29]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[30]	10591372	1			T22	277		T23	138		T24	648
bins_for_gpio_bits[31]	10591372	1			T22	277		T23	138		T24	648

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197945188

1

T22

2085

T23

2093

T24

10435

auto[1]

140978716

1

T22

6779

T23

2323

T24

10301

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197936301

1

T22

2089

T23

2092

T24

10435

auto[1]

140987603

1

T22

6775

T23

2324

T24

10301

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6013341	1			T22	61		T23	67		T24	355
bins_for_gpio_bits[0]	auto[0]	auto[1]	180648	1			T22	3		T23	1		T1	461
bins_for_gpio_bits[0]	auto[1]	auto[0]	180937	1			T22	3		T23	1		T1	463
bins_for_gpio_bits[0]	auto[1]	auto[1]	4216446	1			T22	210		T23	69		T24	293
bins_for_gpio_bits[1]	auto[0]	auto[0]	5994152	1			T22	76		T23	94		T24	363
bins_for_gpio_bits[1]	auto[0]	auto[1]	180974	1			T22	9		T1	433		T11	34
bins_for_gpio_bits[1]	auto[1]	auto[0]	181268	1			T22	9		T1	435		T11	35
bins_for_gpio_bits[1]	auto[1]	auto[1]	4234978	1			T22	183		T23	44		T24	285
bins_for_gpio_bits[2]	auto[0]	auto[0]	6001273	1			T22	76		T23	39		T24	288
bins_for_gpio_bits[2]	auto[0]	auto[1]	180255	1			T22	5		T23	1		T1	457
bins_for_gpio_bits[2]	auto[1]	auto[0]	180510	1			T22	5		T23	1		T1	458
bins_for_gpio_bits[2]	auto[1]	auto[1]	4229334	1			T22	191		T23	97		T24	360
bins_for_gpio_bits[3]	auto[0]	auto[0]	6000049	1			T22	67		T23	50		T24	285
bins_for_gpio_bits[3]	auto[0]	auto[1]	181022	1			T22	3		T23	2		T1	415
bins_for_gpio_bits[3]	auto[1]	auto[0]	181295	1			T22	3		T23	2		T1	417
bins_for_gpio_bits[3]	auto[1]	auto[1]	4229006	1			T22	204		T23	84		T24	363
bins_for_gpio_bits[4]	auto[0]	auto[0]	6008689	1			T22	60		T23	60		T24	352
bins_for_gpio_bits[4]	auto[0]	auto[1]	180999	1			T22	1		T1	453		T11	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	181280	1			T22	1		T1	454		T11	46
bins_for_gpio_bits[4]	auto[1]	auto[1]	4220404	1			T22	215		T23	78		T24	296
bins_for_gpio_bits[5]	auto[0]	auto[0]	6017827	1			T22	60		T23	67		T24	368
bins_for_gpio_bits[5]	auto[0]	auto[1]	180279	1			T22	6		T1	446		T11	42
bins_for_gpio_bits[5]	auto[1]	auto[0]	180596	1			T22	6		T1	448		T11	42
bins_for_gpio_bits[5]	auto[1]	auto[1]	4212670	1			T22	205		T23	71		T24	280
bins_for_gpio_bits[6]	auto[0]	auto[0]	6015330	1			T22	55		T23	65		T24	279
bins_for_gpio_bits[6]	auto[0]	auto[1]	180217	1			T22	4		T1	481		T11	38
bins_for_gpio_bits[6]	auto[1]	auto[0]	180459	1			T22	4		T1	481		T11	38
bins_for_gpio_bits[6]	auto[1]	auto[1]	4215366	1			T22	214		T23	73		T24	369
bins_for_gpio_bits[7]	auto[0]	auto[0]	5999215	1			T22	59		T23	58		T24	299
bins_for_gpio_bits[7]	auto[0]	auto[1]	181173	1			T22	2		T1	412		T11	44
bins_for_gpio_bits[7]	auto[1]	auto[0]	181417	1			T22	2		T1	414		T11	44
bins_for_gpio_bits[7]	auto[1]	auto[1]	4229567	1			T22	214		T23	80		T24	349
bins_for_gpio_bits[8]	auto[0]	auto[0]	6000488	1			T22	59		T23	102		T24	358
bins_for_gpio_bits[8]	auto[0]	auto[1]	180322	1			T22	2		T1	465		T11	45
bins_for_gpio_bits[8]	auto[1]	auto[0]	180639	1			T22	2		T1	467		T11	45
bins_for_gpio_bits[8]	auto[1]	auto[1]	4229923	1			T22	214		T23	36		T24	290
bins_for_gpio_bits[9]	auto[0]	auto[0]	6006670	1			T22	60		T23	79		T24	334
bins_for_gpio_bits[9]	auto[0]	auto[1]	180479	1			T22	5		T1	445		T11	45
bins_for_gpio_bits[9]	auto[1]	auto[0]	180707	1			T22	5		T1	448		T11	45
bins_for_gpio_bits[9]	auto[1]	auto[1]	4223516	1			T22	207		T23	59		T24	314
bins_for_gpio_bits[10]	auto[0]	auto[0]	6003819	1			T22	46		T23	42		T24	286
bins_for_gpio_bits[10]	auto[0]	auto[1]	180528	1			T22	3		T1	418		T11	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	180821	1			T22	3		T1	423		T11	40
bins_for_gpio_bits[10]	auto[1]	auto[1]	4226204	1			T22	225		T23	96		T24	362
bins_for_gpio_bits[11]	auto[0]	auto[0]	6003428	1			T22	58		T23	42		T24	361
bins_for_gpio_bits[11]	auto[0]	auto[1]	180668	1			T22	3		T1	442		T11	43
bins_for_gpio_bits[11]	auto[1]	auto[0]	180971	1			T22	3		T1	445		T11	43
bins_for_gpio_bits[11]	auto[1]	auto[1]	4226305	1			T22	213		T23	96		T24	287
bins_for_gpio_bits[12]	auto[0]	auto[0]	5999304	1			T22	48		T23	89		T24	264
bins_for_gpio_bits[12]	auto[0]	auto[1]	180572	1			T22	1		T1	437		T11	46
bins_for_gpio_bits[12]	auto[1]	auto[0]	180826	1			T22	1		T1	439		T11	46
bins_for_gpio_bits[12]	auto[1]	auto[1]	4230670	1			T22	227		T23	49		T24	384
bins_for_gpio_bits[13]	auto[0]	auto[0]	5993933	1			T22	65		T23	52		T24	331
bins_for_gpio_bits[13]	auto[0]	auto[1]	180535	1			T22	6		T1	431		T11	42
bins_for_gpio_bits[13]	auto[1]	auto[0]	180822	1			T22	6		T1	432		T11	42
bins_for_gpio_bits[13]	auto[1]	auto[1]	4236082	1			T22	200		T23	86		T24	317
bins_for_gpio_bits[14]	auto[0]	auto[0]	5995289	1			T22	61		T23	73		T24	380
bins_for_gpio_bits[14]	auto[0]	auto[1]	180382	1			T22	1		T1	466		T11	42
bins_for_gpio_bits[14]	auto[1]	auto[0]	180640	1			T22	1		T1	469		T11	42
bins_for_gpio_bits[14]	auto[1]	auto[1]	4235061	1			T22	214		T23	65		T24	268
bins_for_gpio_bits[15]	auto[0]	auto[0]	6004153	1			T22	55		T23	19		T24	373
bins_for_gpio_bits[15]	auto[0]	auto[1]	180065	1			T22	1		T1	427		T11	41
bins_for_gpio_bits[15]	auto[1]	auto[0]	180354	1			T22	1		T1	427		T11	41
bins_for_gpio_bits[15]	auto[1]	auto[1]	4226800	1			T22	220		T23	119		T24	275
bins_for_gpio_bits[16]	auto[0]	auto[0]	6003677	1			T22	56		T23	82		T24	387
bins_for_gpio_bits[16]	auto[0]	auto[1]	180563	1			T22	9		T1	440		T11	44
bins_for_gpio_bits[16]	auto[1]	auto[0]	180832	1			T22	8		T1	442		T11	44
bins_for_gpio_bits[16]	auto[1]	auto[1]	4226300	1			T22	204		T23	56		T24	261
bins_for_gpio_bits[17]	auto[0]	auto[0]	6010953	1			T22	49		T23	75		T24	403
bins_for_gpio_bits[17]	auto[0]	auto[1]	180316	1			T1	454		T11	43		T12	788
bins_for_gpio_bits[17]	auto[1]	auto[0]	180578	1			T1	456		T11	43		T12	794
bins_for_gpio_bits[17]	auto[1]	auto[1]	4219525	1			T22	228		T23	63		T24	245
bins_for_gpio_bits[18]	auto[0]	auto[0]	5998109	1			T22	52		T23	54		T24	353
bins_for_gpio_bits[18]	auto[0]	auto[1]	180286	1			T22	1		T1	418		T11	40
bins_for_gpio_bits[18]	auto[1]	auto[0]	180574	1			T22	1		T1	421		T11	40
bins_for_gpio_bits[18]	auto[1]	auto[1]	4232403	1			T22	223		T23	84		T24	295
bins_for_gpio_bits[19]	auto[0]	auto[0]	6007775	1			T22	63		T23	65		T24	297
bins_for_gpio_bits[19]	auto[0]	auto[1]	180229	1			T22	6		T1	443		T11	41
bins_for_gpio_bits[19]	auto[1]	auto[0]	180504	1			T22	5		T1	444		T11	41
bins_for_gpio_bits[19]	auto[1]	auto[1]	4222864	1			T22	203		T23	73		T24	351
bins_for_gpio_bits[20]	auto[0]	auto[0]	6002766	1			T22	75		T23	44		T24	338
bins_for_gpio_bits[20]	auto[0]	auto[1]	180763	1			T22	6		T1	485		T11	48
bins_for_gpio_bits[20]	auto[1]	auto[0]	181035	1			T22	6		T1	487		T11	49
bins_for_gpio_bits[20]	auto[1]	auto[1]	4226808	1			T22	190		T23	94		T24	310
bins_for_gpio_bits[21]	auto[0]	auto[0]	6012894	1			T22	60		T23	82		T24	329
bins_for_gpio_bits[21]	auto[0]	auto[1]	180467	1			T22	4		T1	441		T11	43
bins_for_gpio_bits[21]	auto[1]	auto[0]	180739	1			T22	4		T1	444		T11	43
bins_for_gpio_bits[21]	auto[1]	auto[1]	4217272	1			T22	209		T23	56		T24	319
bins_for_gpio_bits[22]	auto[0]	auto[0]	6005371	1			T22	69		T23	47		T24	293
bins_for_gpio_bits[22]	auto[0]	auto[1]	180635	1			T22	9		T1	450		T11	41
bins_for_gpio_bits[22]	auto[1]	auto[0]	180915	1			T22	9		T1	451		T11	42
bins_for_gpio_bits[22]	auto[1]	auto[1]	4224451	1			T22	190		T23	91		T24	355
bins_for_gpio_bits[23]	auto[0]	auto[0]	6003663	1			T22	67		T23	66		T24	284
bins_for_gpio_bits[23]	auto[0]	auto[1]	180798	1			T22	4		T1	449		T11	45
bins_for_gpio_bits[23]	auto[1]	auto[0]	181082	1			T22	4		T1	451		T11	46
bins_for_gpio_bits[23]	auto[1]	auto[1]	4225829	1			T22	202		T23	72		T24	364
bins_for_gpio_bits[24]	auto[0]	auto[0]	6009518	1			T22	64		T23	76		T24	268
bins_for_gpio_bits[24]	auto[0]	auto[1]	180926	1			T22	8		T1	460		T11	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	181252	1			T22	8		T1	463		T11	44
bins_for_gpio_bits[24]	auto[1]	auto[1]	4219676	1			T22	197		T23	62		T24	380
bins_for_gpio_bits[25]	auto[0]	auto[0]	6006164	1			T22	59		T23	78		T24	337
bins_for_gpio_bits[25]	auto[0]	auto[1]	180770	1			T22	9		T1	449		T11	39
bins_for_gpio_bits[25]	auto[1]	auto[0]	181047	1			T22	9		T1	451		T11	39
bins_for_gpio_bits[25]	auto[1]	auto[1]	4223391	1			T22	200		T23	60		T24	311
bins_for_gpio_bits[26]	auto[0]	auto[0]	6016107	1			T22	56		T23	84		T24	293
bins_for_gpio_bits[26]	auto[0]	auto[1]	180333	1			T22	2		T1	465		T11	43
bins_for_gpio_bits[26]	auto[1]	auto[0]	180632	1			T22	1		T23	1		T1	465
bins_for_gpio_bits[26]	auto[1]	auto[1]	4214300	1			T22	218		T23	53		T24	355
bins_for_gpio_bits[27]	auto[0]	auto[0]	6001794	1			T22	60		T23	45		T24	346
bins_for_gpio_bits[27]	auto[0]	auto[1]	180188	1			T22	1		T1	451		T11	53
bins_for_gpio_bits[27]	auto[1]	auto[0]	180461	1			T22	1		T1	451		T11	53
bins_for_gpio_bits[27]	auto[1]	auto[1]	4228929	1			T22	215		T23	93		T24	302
bins_for_gpio_bits[28]	auto[0]	auto[0]	6010111	1			T22	71		T23	71		T24	320
bins_for_gpio_bits[28]	auto[0]	auto[1]	181000	1			T22	9		T1	449		T11	45
bins_for_gpio_bits[28]	auto[1]	auto[0]	181297	1			T22	8		T1	452		T11	45
bins_for_gpio_bits[28]	auto[1]	auto[1]	4218964	1			T22	189		T23	67		T24	328
bins_for_gpio_bits[29]	auto[0]	auto[0]	6005634	1			T22	55		T23	60		T24	321
bins_for_gpio_bits[29]	auto[0]	auto[1]	180597	1			T22	3		T1	474		T11	39
bins_for_gpio_bits[29]	auto[1]	auto[0]	180818	1			T22	3		T1	475		T11	39
bins_for_gpio_bits[29]	auto[1]	auto[1]	4224323	1			T22	216		T23	78		T24	327
bins_for_gpio_bits[30]	auto[0]	auto[0]	6010677	1			T22	59		T23	64		T24	280
bins_for_gpio_bits[30]	auto[0]	auto[1]	180466	1			T22	1		T1	449		T11	39
bins_for_gpio_bits[30]	auto[1]	auto[0]	180750	1			T22	1		T1	453		T11	39
bins_for_gpio_bits[30]	auto[1]	auto[1]	4219479	1			T22	216		T23	74		T24	368
bins_for_gpio_bits[31]	auto[0]	auto[0]	5995689	1			T22	72		T23	97		T24	310
bins_for_gpio_bits[31]	auto[0]	auto[1]	180984	1			T22	9		T1	436		T11	35
bins_for_gpio_bits[31]	auto[1]	auto[0]	181268	1			T22	9		T1	436		T11	36
bins_for_gpio_bits[31]	auto[1]	auto[1]	4233431	1			T22	187		T23	41		T24	338