Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6398574 |
1 |
|
|
T22 |
155 |
|
T23 |
75 |
|
T24 |
648 |
| auto[1] |
4367757 |
1 |
|
|
T23 |
23 |
|
T25 |
875 |
|
T1 |
9319 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211802 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
554529 |
1 |
|
|
T23 |
1 |
|
T25 |
157 |
|
T1 |
1356 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6429373 |
1 |
|
|
T22 |
155 |
|
T23 |
87 |
|
T24 |
648 |
| auto[1] |
4336958 |
1 |
|
|
T23 |
11 |
|
T25 |
894 |
|
T1 |
9678 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1883137 |
1 |
|
|
T23 |
10 |
|
T25 |
276 |
|
T1 |
4106 |
| auto[1] |
auto[0] |
auto[1] |
276266 |
1 |
|
|
T23 |
1 |
|
T25 |
53 |
|
T1 |
627 |
| auto[1] |
auto[1] |
auto[0] |
1899292 |
1 |
|
|
T25 |
461 |
|
T1 |
4216 |
|
T12 |
7943 |
| auto[1] |
auto[1] |
auto[1] |
278263 |
1 |
|
|
T25 |
104 |
|
T1 |
729 |
|
T12 |
1023 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6398988 |
1 |
|
|
T22 |
155 |
|
T23 |
58 |
|
T24 |
648 |
| auto[1] |
4367343 |
1 |
|
|
T23 |
40 |
|
T25 |
1169 |
|
T1 |
8743 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10207377 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
558954 |
1 |
|
|
T23 |
2 |
|
T25 |
177 |
|
T1 |
1378 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6402454 |
1 |
|
|
T22 |
155 |
|
T23 |
68 |
|
T24 |
648 |
| auto[1] |
4363877 |
1 |
|
|
T23 |
30 |
|
T25 |
994 |
|
T1 |
9451 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1892449 |
1 |
|
|
T23 |
15 |
|
T25 |
294 |
|
T1 |
3833 |
| auto[1] |
auto[0] |
auto[1] |
278005 |
1 |
|
|
T23 |
1 |
|
T25 |
69 |
|
T1 |
597 |
| auto[1] |
auto[1] |
auto[0] |
1912474 |
1 |
|
|
T23 |
13 |
|
T25 |
523 |
|
T1 |
4240 |
| auto[1] |
auto[1] |
auto[1] |
280949 |
1 |
|
|
T23 |
1 |
|
T25 |
108 |
|
T1 |
781 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6408322 |
1 |
|
|
T22 |
155 |
|
T23 |
61 |
|
T24 |
648 |
| auto[1] |
4358009 |
1 |
|
|
T23 |
37 |
|
T25 |
788 |
|
T1 |
10221 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10207633 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
558698 |
1 |
|
|
T23 |
1 |
|
T25 |
170 |
|
T1 |
1236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6407745 |
1 |
|
|
T22 |
155 |
|
T23 |
78 |
|
T24 |
648 |
| auto[1] |
4358586 |
1 |
|
|
T23 |
20 |
|
T25 |
899 |
|
T1 |
8442 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1894473 |
1 |
|
|
T23 |
12 |
|
T25 |
390 |
|
T1 |
3066 |
| auto[1] |
auto[0] |
auto[1] |
278483 |
1 |
|
|
T25 |
85 |
|
T1 |
493 |
|
T12 |
1206 |
| auto[1] |
auto[1] |
auto[0] |
1905415 |
1 |
|
|
T23 |
7 |
|
T25 |
339 |
|
T1 |
4140 |
| auto[1] |
auto[1] |
auto[1] |
280215 |
1 |
|
|
T23 |
1 |
|
T25 |
85 |
|
T1 |
743 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400969 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4365362 |
1 |
|
|
T23 |
24 |
|
T25 |
885 |
|
T1 |
9296 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210127 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
556204 |
1 |
|
|
T23 |
2 |
|
T25 |
132 |
|
T1 |
1224 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6424715 |
1 |
|
|
T22 |
155 |
|
T23 |
78 |
|
T24 |
648 |
| auto[1] |
4341616 |
1 |
|
|
T23 |
20 |
|
T25 |
723 |
|
T1 |
8673 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1876493 |
1 |
|
|
T23 |
9 |
|
T25 |
301 |
|
T1 |
3556 |
| auto[1] |
auto[0] |
auto[1] |
275558 |
1 |
|
|
T25 |
73 |
|
T1 |
588 |
|
T12 |
1252 |
| auto[1] |
auto[1] |
auto[0] |
1908919 |
1 |
|
|
T23 |
9 |
|
T25 |
290 |
|
T1 |
3893 |
| auto[1] |
auto[1] |
auto[1] |
280646 |
1 |
|
|
T23 |
2 |
|
T25 |
59 |
|
T1 |
636 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412812 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4353519 |
1 |
|
|
T23 |
14 |
|
T25 |
765 |
|
T1 |
9532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10208684 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
557647 |
1 |
|
|
T23 |
1 |
|
T25 |
143 |
|
T1 |
1335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412770 |
1 |
|
|
T22 |
155 |
|
T23 |
82 |
|
T24 |
648 |
| auto[1] |
4353561 |
1 |
|
|
T23 |
16 |
|
T25 |
768 |
|
T1 |
9375 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1895156 |
1 |
|
|
T23 |
15 |
|
T25 |
332 |
|
T1 |
3265 |
| auto[1] |
auto[0] |
auto[1] |
277562 |
1 |
|
|
T23 |
1 |
|
T25 |
73 |
|
T1 |
518 |
| auto[1] |
auto[1] |
auto[0] |
1900758 |
1 |
|
|
T25 |
293 |
|
T1 |
4775 |
|
T12 |
8365 |
| auto[1] |
auto[1] |
auto[1] |
280085 |
1 |
|
|
T25 |
70 |
|
T1 |
817 |
|
T12 |
1158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416516 |
1 |
|
|
T22 |
155 |
|
T23 |
64 |
|
T24 |
648 |
| auto[1] |
4349815 |
1 |
|
|
T23 |
34 |
|
T25 |
575 |
|
T1 |
10583 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10206091 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
560240 |
1 |
|
|
T23 |
1 |
|
T25 |
142 |
|
T1 |
1480 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6388450 |
1 |
|
|
T22 |
155 |
|
T23 |
81 |
|
T24 |
648 |
| auto[1] |
4377881 |
1 |
|
|
T23 |
17 |
|
T25 |
800 |
|
T1 |
10373 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1911150 |
1 |
|
|
T25 |
381 |
|
T1 |
3486 |
|
T12 |
9499 |
| auto[1] |
auto[0] |
auto[1] |
279584 |
1 |
|
|
T25 |
79 |
|
T1 |
546 |
|
T12 |
1397 |
| auto[1] |
auto[1] |
auto[0] |
1906491 |
1 |
|
|
T23 |
16 |
|
T25 |
277 |
|
T1 |
5407 |
| auto[1] |
auto[1] |
auto[1] |
280656 |
1 |
|
|
T23 |
1 |
|
T25 |
63 |
|
T1 |
934 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6433200 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4333131 |
1 |
|
|
T23 |
32 |
|
T25 |
810 |
|
T1 |
8627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211034 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
555297 |
1 |
|
|
T23 |
1 |
|
T25 |
155 |
|
T1 |
1383 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6431067 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4335264 |
1 |
|
|
T23 |
18 |
|
T25 |
850 |
|
T1 |
9545 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1896434 |
1 |
|
|
T23 |
7 |
|
T25 |
382 |
|
T1 |
4048 |
| auto[1] |
auto[0] |
auto[1] |
279594 |
1 |
|
|
T25 |
82 |
|
T1 |
696 |
|
T12 |
1273 |
| auto[1] |
auto[1] |
auto[0] |
1883533 |
1 |
|
|
T23 |
10 |
|
T25 |
313 |
|
T1 |
4114 |
| auto[1] |
auto[1] |
auto[1] |
275703 |
1 |
|
|
T23 |
1 |
|
T25 |
73 |
|
T1 |
687 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6401994 |
1 |
|
|
T22 |
155 |
|
T23 |
62 |
|
T24 |
648 |
| auto[1] |
4364337 |
1 |
|
|
T23 |
36 |
|
T25 |
880 |
|
T1 |
9293 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10207413 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
558918 |
1 |
|
|
T25 |
166 |
|
T1 |
1216 |
|
T12 |
2503 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6392174 |
1 |
|
|
T22 |
155 |
|
T23 |
72 |
|
T24 |
648 |
| auto[1] |
4374157 |
1 |
|
|
T23 |
26 |
|
T25 |
905 |
|
T1 |
8825 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1898411 |
1 |
|
|
T23 |
15 |
|
T25 |
345 |
|
T1 |
3731 |
| auto[1] |
auto[0] |
auto[1] |
277641 |
1 |
|
|
T25 |
71 |
|
T1 |
567 |
|
T12 |
1318 |
| auto[1] |
auto[1] |
auto[0] |
1916828 |
1 |
|
|
T23 |
11 |
|
T25 |
394 |
|
T1 |
3878 |
| auto[1] |
auto[1] |
auto[1] |
281277 |
1 |
|
|
T25 |
95 |
|
T1 |
649 |
|
T12 |
1185 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6406232 |
1 |
|
|
T22 |
155 |
|
T23 |
75 |
|
T24 |
648 |
| auto[1] |
4360099 |
1 |
|
|
T23 |
23 |
|
T25 |
976 |
|
T1 |
9235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10213473 |
1 |
|
|
T22 |
155 |
|
T23 |
95 |
|
T24 |
648 |
| auto[1] |
552858 |
1 |
|
|
T23 |
3 |
|
T25 |
100 |
|
T1 |
1264 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6431878 |
1 |
|
|
T22 |
155 |
|
T23 |
72 |
|
T24 |
648 |
| auto[1] |
4334453 |
1 |
|
|
T23 |
26 |
|
T25 |
554 |
|
T1 |
8720 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1885968 |
1 |
|
|
T23 |
13 |
|
T25 |
160 |
|
T1 |
3467 |
| auto[1] |
auto[0] |
auto[1] |
274850 |
1 |
|
|
T23 |
2 |
|
T25 |
34 |
|
T1 |
559 |
| auto[1] |
auto[1] |
auto[0] |
1895627 |
1 |
|
|
T23 |
10 |
|
T25 |
294 |
|
T1 |
3989 |
| auto[1] |
auto[1] |
auto[1] |
278008 |
1 |
|
|
T23 |
1 |
|
T25 |
66 |
|
T1 |
705 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6426409 |
1 |
|
|
T22 |
155 |
|
T23 |
56 |
|
T24 |
648 |
| auto[1] |
4339922 |
1 |
|
|
T23 |
42 |
|
T25 |
705 |
|
T1 |
8997 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10208638 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
557693 |
1 |
|
|
T25 |
149 |
|
T1 |
1369 |
|
T12 |
2283 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6407756 |
1 |
|
|
T22 |
155 |
|
T23 |
89 |
|
T24 |
648 |
| auto[1] |
4358575 |
1 |
|
|
T23 |
9 |
|
T25 |
827 |
|
T1 |
9182 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1911322 |
1 |
|
|
T23 |
6 |
|
T25 |
437 |
|
T1 |
4270 |
| auto[1] |
auto[0] |
auto[1] |
281693 |
1 |
|
|
T25 |
99 |
|
T1 |
761 |
|
T12 |
1132 |
| auto[1] |
auto[1] |
auto[0] |
1889560 |
1 |
|
|
T23 |
3 |
|
T25 |
241 |
|
T1 |
3543 |
| auto[1] |
auto[1] |
auto[1] |
276000 |
1 |
|
|
T25 |
50 |
|
T1 |
608 |
|
T12 |
1151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6392140 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4374191 |
1 |
|
|
T23 |
18 |
|
T25 |
840 |
|
T1 |
9407 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211668 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
554663 |
1 |
|
|
T23 |
1 |
|
T25 |
168 |
|
T1 |
1135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428400 |
1 |
|
|
T22 |
155 |
|
T23 |
65 |
|
T24 |
648 |
| auto[1] |
4337931 |
1 |
|
|
T23 |
33 |
|
T25 |
936 |
|
T1 |
8185 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1888575 |
1 |
|
|
T23 |
22 |
|
T25 |
372 |
|
T1 |
3481 |
| auto[1] |
auto[0] |
auto[1] |
276721 |
1 |
|
|
T25 |
86 |
|
T1 |
557 |
|
T12 |
1316 |
| auto[1] |
auto[1] |
auto[0] |
1894693 |
1 |
|
|
T23 |
10 |
|
T25 |
396 |
|
T1 |
3569 |
| auto[1] |
auto[1] |
auto[1] |
277942 |
1 |
|
|
T23 |
1 |
|
T25 |
82 |
|
T1 |
578 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416584 |
1 |
|
|
T22 |
155 |
|
T23 |
72 |
|
T24 |
648 |
| auto[1] |
4349747 |
1 |
|
|
T23 |
26 |
|
T25 |
927 |
|
T1 |
9389 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211106 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555225 |
1 |
|
|
T25 |
166 |
|
T1 |
1236 |
|
T12 |
2149 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6422428 |
1 |
|
|
T22 |
155 |
|
T23 |
82 |
|
T24 |
648 |
| auto[1] |
4343903 |
1 |
|
|
T23 |
16 |
|
T25 |
913 |
|
T1 |
8580 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1894505 |
1 |
|
|
T23 |
10 |
|
T25 |
412 |
|
T1 |
3962 |
| auto[1] |
auto[0] |
auto[1] |
277104 |
1 |
|
|
T25 |
89 |
|
T1 |
688 |
|
T12 |
1073 |
| auto[1] |
auto[1] |
auto[0] |
1894173 |
1 |
|
|
T23 |
6 |
|
T25 |
335 |
|
T1 |
3382 |
| auto[1] |
auto[1] |
auto[1] |
278121 |
1 |
|
|
T25 |
77 |
|
T1 |
548 |
|
T12 |
1076 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6424609 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4341722 |
1 |
|
|
T23 |
32 |
|
T25 |
1012 |
|
T1 |
8938 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210799 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555532 |
1 |
|
|
T25 |
102 |
|
T1 |
1301 |
|
T12 |
2476 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6418803 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4347528 |
1 |
|
|
T23 |
14 |
|
T25 |
610 |
|
T1 |
9128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1895735 |
1 |
|
|
T23 |
3 |
|
T25 |
189 |
|
T1 |
3758 |
| auto[1] |
auto[0] |
auto[1] |
278154 |
1 |
|
|
T25 |
33 |
|
T1 |
631 |
|
T12 |
1334 |
| auto[1] |
auto[1] |
auto[0] |
1896261 |
1 |
|
|
T23 |
11 |
|
T25 |
319 |
|
T1 |
4069 |
| auto[1] |
auto[1] |
auto[1] |
277378 |
1 |
|
|
T25 |
69 |
|
T1 |
670 |
|
T12 |
1142 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400477 |
1 |
|
|
T22 |
155 |
|
T23 |
62 |
|
T24 |
648 |
| auto[1] |
4365854 |
1 |
|
|
T23 |
36 |
|
T25 |
1000 |
|
T1 |
9225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211326 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
555005 |
1 |
|
|
T23 |
1 |
|
T25 |
147 |
|
T1 |
1325 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6424200 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4342131 |
1 |
|
|
T23 |
24 |
|
T25 |
836 |
|
T1 |
9292 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1890973 |
1 |
|
|
T23 |
12 |
|
T25 |
417 |
|
T1 |
3984 |
| auto[1] |
auto[0] |
auto[1] |
276777 |
1 |
|
|
T23 |
1 |
|
T25 |
90 |
|
T1 |
668 |
| auto[1] |
auto[1] |
auto[0] |
1896153 |
1 |
|
|
T23 |
11 |
|
T25 |
272 |
|
T1 |
3983 |
| auto[1] |
auto[1] |
auto[1] |
278228 |
1 |
|
|
T25 |
57 |
|
T1 |
657 |
|
T12 |
1361 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430118 |
1 |
|
|
T22 |
155 |
|
T23 |
77 |
|
T24 |
648 |
| auto[1] |
4336213 |
1 |
|
|
T23 |
21 |
|
T25 |
804 |
|
T1 |
8146 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10206746 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
559585 |
1 |
|
|
T25 |
185 |
|
T1 |
1432 |
|
T12 |
2504 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6403473 |
1 |
|
|
T22 |
155 |
|
T23 |
87 |
|
T24 |
648 |
| auto[1] |
4362858 |
1 |
|
|
T23 |
11 |
|
T25 |
967 |
|
T1 |
9919 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1903017 |
1 |
|
|
T23 |
8 |
|
T25 |
410 |
|
T1 |
4933 |
| auto[1] |
auto[0] |
auto[1] |
280633 |
1 |
|
|
T25 |
88 |
|
T1 |
866 |
|
T12 |
1230 |
| auto[1] |
auto[1] |
auto[0] |
1900256 |
1 |
|
|
T23 |
3 |
|
T25 |
372 |
|
T1 |
3554 |
| auto[1] |
auto[1] |
auto[1] |
278952 |
1 |
|
|
T25 |
97 |
|
T1 |
566 |
|
T12 |
1274 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6423619 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4342712 |
1 |
|
|
T23 |
18 |
|
T25 |
831 |
|
T1 |
9664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10207222 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
559109 |
1 |
|
|
T23 |
1 |
|
T25 |
148 |
|
T1 |
1323 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6401361 |
1 |
|
|
T22 |
155 |
|
T23 |
79 |
|
T24 |
648 |
| auto[1] |
4364970 |
1 |
|
|
T23 |
19 |
|
T25 |
851 |
|
T1 |
9282 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1915065 |
1 |
|
|
T23 |
18 |
|
T25 |
387 |
|
T1 |
3710 |
| auto[1] |
auto[0] |
auto[1] |
282573 |
1 |
|
|
T23 |
1 |
|
T25 |
84 |
|
T1 |
621 |
| auto[1] |
auto[1] |
auto[0] |
1890796 |
1 |
|
|
T25 |
316 |
|
T1 |
4249 |
|
T12 |
9618 |
| auto[1] |
auto[1] |
auto[1] |
276536 |
1 |
|
|
T25 |
64 |
|
T1 |
702 |
|
T12 |
1513 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6422644 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4343687 |
1 |
|
|
T23 |
32 |
|
T25 |
786 |
|
T1 |
8536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210522 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555809 |
1 |
|
|
T25 |
182 |
|
T1 |
1286 |
|
T12 |
2219 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6414464 |
1 |
|
|
T22 |
155 |
|
T23 |
86 |
|
T24 |
648 |
| auto[1] |
4351867 |
1 |
|
|
T23 |
12 |
|
T25 |
957 |
|
T1 |
9015 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1882062 |
1 |
|
|
T25 |
463 |
|
T1 |
4172 |
|
T12 |
8297 |
| auto[1] |
auto[0] |
auto[1] |
275267 |
1 |
|
|
T25 |
114 |
|
T1 |
714 |
|
T12 |
1152 |
| auto[1] |
auto[1] |
auto[0] |
1913996 |
1 |
|
|
T23 |
12 |
|
T25 |
312 |
|
T1 |
3557 |
| auto[1] |
auto[1] |
auto[1] |
280542 |
1 |
|
|
T25 |
68 |
|
T1 |
572 |
|
T12 |
1067 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6424505 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4341826 |
1 |
|
|
T23 |
24 |
|
T25 |
759 |
|
T1 |
9349 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211322 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555009 |
1 |
|
|
T25 |
169 |
|
T1 |
1324 |
|
T12 |
2494 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6420958 |
1 |
|
|
T22 |
155 |
|
T23 |
85 |
|
T24 |
648 |
| auto[1] |
4345373 |
1 |
|
|
T23 |
13 |
|
T25 |
910 |
|
T1 |
9376 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1896773 |
1 |
|
|
T23 |
4 |
|
T25 |
459 |
|
T1 |
3820 |
| auto[1] |
auto[0] |
auto[1] |
277428 |
1 |
|
|
T25 |
110 |
|
T1 |
608 |
|
T12 |
1232 |
| auto[1] |
auto[1] |
auto[0] |
1893591 |
1 |
|
|
T23 |
9 |
|
T25 |
282 |
|
T1 |
4232 |
| auto[1] |
auto[1] |
auto[1] |
277581 |
1 |
|
|
T25 |
59 |
|
T1 |
716 |
|
T12 |
1262 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6415494 |
1 |
|
|
T22 |
155 |
|
T23 |
71 |
|
T24 |
648 |
| auto[1] |
4350837 |
1 |
|
|
T23 |
27 |
|
T25 |
1015 |
|
T1 |
9309 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210397 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555934 |
1 |
|
|
T25 |
192 |
|
T1 |
1259 |
|
T12 |
2341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417547 |
1 |
|
|
T22 |
155 |
|
T23 |
78 |
|
T24 |
648 |
| auto[1] |
4348784 |
1 |
|
|
T23 |
20 |
|
T25 |
1042 |
|
T1 |
9093 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1897663 |
1 |
|
|
T23 |
6 |
|
T25 |
381 |
|
T1 |
4153 |
| auto[1] |
auto[0] |
auto[1] |
277921 |
1 |
|
|
T25 |
86 |
|
T1 |
685 |
|
T12 |
1277 |
| auto[1] |
auto[1] |
auto[0] |
1895187 |
1 |
|
|
T23 |
14 |
|
T25 |
469 |
|
T1 |
3681 |
| auto[1] |
auto[1] |
auto[1] |
278013 |
1 |
|
|
T25 |
106 |
|
T1 |
574 |
|
T12 |
1064 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6386726 |
1 |
|
|
T22 |
155 |
|
T23 |
77 |
|
T24 |
648 |
| auto[1] |
4379605 |
1 |
|
|
T23 |
21 |
|
T25 |
783 |
|
T1 |
8866 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10209195 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
557136 |
1 |
|
|
T23 |
1 |
|
T25 |
142 |
|
T1 |
1201 |