Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416102 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4350229 |
1 |
|
|
T23 |
24 |
|
T25 |
777 |
|
T1 |
9706 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210729 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
555602 |
1 |
|
|
T23 |
1 |
|
T25 |
146 |
|
T1 |
1476 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413083 |
1 |
|
|
T22 |
155 |
|
T23 |
77 |
|
T24 |
648 |
| auto[1] |
4353248 |
1 |
|
|
T23 |
21 |
|
T25 |
744 |
|
T1 |
10117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1900325 |
1 |
|
|
T23 |
13 |
|
T25 |
350 |
|
T1 |
3998 |
| auto[1] |
auto[0] |
auto[1] |
278012 |
1 |
|
|
T25 |
87 |
|
T1 |
662 |
|
T12 |
1313 |
| auto[1] |
auto[1] |
auto[0] |
1897321 |
1 |
|
|
T23 |
7 |
|
T25 |
248 |
|
T1 |
4643 |
| auto[1] |
auto[1] |
auto[1] |
277590 |
1 |
|
|
T23 |
1 |
|
T25 |
59 |
|
T1 |
814 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |