Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6405781 |
1 |
|
|
T22 |
155 |
|
T23 |
79 |
|
T24 |
648 |
| auto[1] |
4360550 |
1 |
|
|
T23 |
19 |
|
T25 |
818 |
|
T1 |
9039 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210349 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
555982 |
1 |
|
|
T25 |
122 |
|
T1 |
1215 |
|
T12 |
2559 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413416 |
1 |
|
|
T22 |
155 |
|
T23 |
79 |
|
T24 |
648 |
| auto[1] |
4352915 |
1 |
|
|
T23 |
19 |
|
T25 |
631 |
|
T1 |
8432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1901509 |
1 |
|
|
T23 |
8 |
|
T25 |
250 |
|
T1 |
3455 |
| auto[1] |
auto[0] |
auto[1] |
279136 |
1 |
|
|
T25 |
64 |
|
T1 |
585 |
|
T12 |
1458 |
| auto[1] |
auto[1] |
auto[0] |
1895424 |
1 |
|
|
T23 |
11 |
|
T25 |
259 |
|
T1 |
3762 |
| auto[1] |
auto[1] |
auto[1] |
276846 |
1 |
|
|
T25 |
58 |
|
T1 |
630 |
|
T12 |
1101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |