Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6433603 |
1 |
|
|
T22 |
155 |
|
T23 |
81 |
|
T24 |
648 |
| auto[1] |
4332728 |
1 |
|
|
T23 |
17 |
|
T25 |
974 |
|
T1 |
9144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10206299 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
560032 |
1 |
|
|
T25 |
156 |
|
T1 |
1352 |
|
T12 |
2349 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6387989 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4378342 |
1 |
|
|
T23 |
14 |
|
T25 |
879 |
|
T1 |
9308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1921673 |
1 |
|
|
T23 |
14 |
|
T25 |
357 |
|
T1 |
3579 |
| auto[1] |
auto[0] |
auto[1] |
282419 |
1 |
|
|
T25 |
72 |
|
T1 |
600 |
|
T12 |
1278 |
| auto[1] |
auto[1] |
auto[0] |
1896637 |
1 |
|
|
T25 |
366 |
|
T1 |
4377 |
|
T12 |
8458 |
| auto[1] |
auto[1] |
auto[1] |
277613 |
1 |
|
|
T25 |
84 |
|
T1 |
752 |
|
T12 |
1071 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |