Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6388635 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4377696 |
1 |
|
|
T23 |
24 |
|
T25 |
1052 |
|
T1 |
9034 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10209429 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
556902 |
1 |
|
|
T23 |
2 |
|
T25 |
133 |
|
T1 |
1431 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413519 |
1 |
|
|
T22 |
155 |
|
T23 |
77 |
|
T24 |
648 |
| auto[1] |
4352812 |
1 |
|
|
T23 |
21 |
|
T25 |
696 |
|
T1 |
9845 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1889929 |
1 |
|
|
T23 |
12 |
|
T25 |
250 |
|
T1 |
4331 |
| auto[1] |
auto[0] |
auto[1] |
276811 |
1 |
|
|
T23 |
1 |
|
T25 |
60 |
|
T1 |
689 |
| auto[1] |
auto[1] |
auto[0] |
1905981 |
1 |
|
|
T23 |
7 |
|
T25 |
313 |
|
T1 |
4083 |
| auto[1] |
auto[1] |
auto[1] |
280091 |
1 |
|
|
T23 |
1 |
|
T25 |
73 |
|
T1 |
742 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |