Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6414123 |
1 |
|
|
T22 |
155 |
|
T23 |
55 |
|
T24 |
648 |
| auto[1] |
4352208 |
1 |
|
|
T23 |
43 |
|
T25 |
964 |
|
T1 |
9410 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10208477 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
557854 |
1 |
|
|
T23 |
1 |
|
T25 |
135 |
|
T1 |
1332 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6409047 |
1 |
|
|
T22 |
155 |
|
T23 |
75 |
|
T24 |
648 |
| auto[1] |
4357284 |
1 |
|
|
T23 |
23 |
|
T25 |
704 |
|
T1 |
9087 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1902695 |
1 |
|
|
T23 |
7 |
|
T25 |
205 |
|
T1 |
3603 |
| auto[1] |
auto[0] |
auto[1] |
279671 |
1 |
|
|
T25 |
43 |
|
T1 |
629 |
|
T12 |
1178 |
| auto[1] |
auto[1] |
auto[0] |
1896735 |
1 |
|
|
T23 |
15 |
|
T25 |
364 |
|
T1 |
4152 |
| auto[1] |
auto[1] |
auto[1] |
278183 |
1 |
|
|
T23 |
1 |
|
T25 |
92 |
|
T1 |
703 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |