Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6398988 |
1 |
|
|
T22 |
155 |
|
T23 |
58 |
|
T24 |
648 |
| auto[1] |
4367343 |
1 |
|
|
T23 |
40 |
|
T25 |
1169 |
|
T1 |
8743 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930298 |
1 |
|
|
T22 |
155 |
|
T23 |
95 |
|
T24 |
648 |
| auto[1] |
1836033 |
1 |
|
|
T23 |
3 |
|
T25 |
362 |
|
T1 |
4019 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6410998 |
1 |
|
|
T22 |
155 |
|
T23 |
92 |
|
T24 |
648 |
| auto[1] |
4355333 |
1 |
|
|
T23 |
6 |
|
T25 |
769 |
|
T1 |
9806 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1253293 |
1 |
|
|
T23 |
2 |
|
T25 |
156 |
|
T1 |
3093 |
| auto[1] |
auto[0] |
auto[1] |
916843 |
1 |
|
|
T25 |
120 |
|
T1 |
2030 |
|
T12 |
3856 |
| auto[1] |
auto[1] |
auto[0] |
1266007 |
1 |
|
|
T23 |
1 |
|
T25 |
251 |
|
T1 |
2694 |
| auto[1] |
auto[1] |
auto[1] |
919190 |
1 |
|
|
T23 |
3 |
|
T25 |
242 |
|
T1 |
1989 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |