Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6408322 |
1 |
|
|
T22 |
155 |
|
T23 |
61 |
|
T24 |
648 |
| auto[1] |
4358009 |
1 |
|
|
T23 |
37 |
|
T25 |
788 |
|
T1 |
10221 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8938280 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
1828051 |
1 |
|
|
T23 |
2 |
|
T25 |
372 |
|
T1 |
3803 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6421841 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
4344490 |
1 |
|
|
T23 |
8 |
|
T25 |
735 |
|
T1 |
9507 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1252661 |
1 |
|
|
T23 |
6 |
|
T25 |
176 |
|
T1 |
2594 |
| auto[1] |
auto[0] |
auto[1] |
912329 |
1 |
|
|
T23 |
2 |
|
T25 |
184 |
|
T1 |
1656 |
| auto[1] |
auto[1] |
auto[0] |
1263778 |
1 |
|
|
T25 |
187 |
|
T1 |
3110 |
|
T12 |
6084 |
| auto[1] |
auto[1] |
auto[1] |
915722 |
1 |
|
|
T25 |
188 |
|
T1 |
2147 |
|
T12 |
4035 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |