Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400969 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4365362 |
1 |
|
|
T23 |
24 |
|
T25 |
885 |
|
T1 |
9296 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8924167 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
1842164 |
1 |
|
|
T23 |
2 |
|
T25 |
367 |
|
T1 |
4181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6386416 |
1 |
|
|
T22 |
155 |
|
T23 |
94 |
|
T24 |
648 |
| auto[1] |
4379915 |
1 |
|
|
T23 |
4 |
|
T25 |
763 |
|
T1 |
9646 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1262224 |
1 |
|
|
T23 |
2 |
|
T25 |
175 |
|
T1 |
2247 |
| auto[1] |
auto[0] |
auto[1] |
917150 |
1 |
|
|
T23 |
2 |
|
T25 |
197 |
|
T1 |
1880 |
| auto[1] |
auto[1] |
auto[0] |
1275527 |
1 |
|
|
T25 |
221 |
|
T1 |
3218 |
|
T12 |
5787 |
| auto[1] |
auto[1] |
auto[1] |
925014 |
1 |
|
|
T25 |
170 |
|
T1 |
2301 |
|
T12 |
3650 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |