Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412812 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4353519 |
1 |
|
|
T23 |
14 |
|
T25 |
765 |
|
T1 |
9532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940255 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
1826076 |
1 |
|
|
T25 |
414 |
|
T1 |
3773 |
|
T12 |
7801 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428119 |
1 |
|
|
T22 |
155 |
|
T23 |
94 |
|
T24 |
648 |
| auto[1] |
4338212 |
1 |
|
|
T23 |
4 |
|
T25 |
809 |
|
T1 |
9205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1262072 |
1 |
|
|
T23 |
4 |
|
T25 |
208 |
|
T1 |
2734 |
| auto[1] |
auto[0] |
auto[1] |
916217 |
1 |
|
|
T25 |
221 |
|
T1 |
1867 |
|
T12 |
4272 |
| auto[1] |
auto[1] |
auto[0] |
1250064 |
1 |
|
|
T25 |
187 |
|
T1 |
2698 |
|
T12 |
5629 |
| auto[1] |
auto[1] |
auto[1] |
909859 |
1 |
|
|
T25 |
193 |
|
T1 |
1906 |
|
T12 |
3529 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |