Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6407865 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4358466 |
1 |
|
|
T23 |
18 |
|
T25 |
762 |
|
T1 |
8496 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1888149 |
1 |
|
|
T23 |
14 |
|
T25 |
333 |
|
T1 |
3550 |
| auto[1] |
auto[0] |
auto[1] |
276045 |
1 |
|
|
T23 |
1 |
|
T25 |
82 |
|
T1 |
558 |
| auto[1] |
auto[1] |
auto[0] |
1913181 |
1 |
|
|
T23 |
3 |
|
T25 |
287 |
|
T1 |
3745 |
| auto[1] |
auto[1] |
auto[1] |
281091 |
1 |
|
|
T25 |
60 |
|
T1 |
643 |
|
T12 |
1241 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |