Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6433200 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4333131 |
1 |
|
|
T23 |
32 |
|
T25 |
810 |
|
T1 |
8627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8927719 |
1 |
|
|
T22 |
155 |
|
T23 |
94 |
|
T24 |
648 |
| auto[1] |
1838612 |
1 |
|
|
T23 |
4 |
|
T25 |
312 |
|
T1 |
3489 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413818 |
1 |
|
|
T22 |
155 |
|
T23 |
89 |
|
T24 |
648 |
| auto[1] |
4352513 |
1 |
|
|
T23 |
9 |
|
T25 |
655 |
|
T1 |
8151 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1265301 |
1 |
|
|
T23 |
4 |
|
T25 |
195 |
|
T1 |
2797 |
| auto[1] |
auto[0] |
auto[1] |
928410 |
1 |
|
|
T23 |
1 |
|
T25 |
171 |
|
T1 |
1977 |
| auto[1] |
auto[1] |
auto[0] |
1248600 |
1 |
|
|
T23 |
1 |
|
T25 |
148 |
|
T1 |
1865 |
| auto[1] |
auto[1] |
auto[1] |
910202 |
1 |
|
|
T23 |
3 |
|
T25 |
141 |
|
T1 |
1512 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |