Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6401994 |
1 |
|
|
T22 |
155 |
|
T23 |
62 |
|
T24 |
648 |
| auto[1] |
4364337 |
1 |
|
|
T23 |
36 |
|
T25 |
880 |
|
T1 |
9293 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944433 |
1 |
|
|
T22 |
155 |
|
T23 |
91 |
|
T24 |
648 |
| auto[1] |
1821898 |
1 |
|
|
T23 |
7 |
|
T25 |
496 |
|
T1 |
3894 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6441372 |
1 |
|
|
T22 |
155 |
|
T23 |
91 |
|
T24 |
648 |
| auto[1] |
4324959 |
1 |
|
|
T23 |
7 |
|
T25 |
1005 |
|
T1 |
9617 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1254884 |
1 |
|
|
T25 |
258 |
|
T1 |
3110 |
|
T12 |
6119 |
| auto[1] |
auto[0] |
auto[1] |
909849 |
1 |
|
|
T23 |
7 |
|
T25 |
239 |
|
T1 |
1973 |
| auto[1] |
auto[1] |
auto[0] |
1248177 |
1 |
|
|
T25 |
251 |
|
T1 |
2613 |
|
T12 |
6223 |
| auto[1] |
auto[1] |
auto[1] |
912049 |
1 |
|
|
T25 |
257 |
|
T1 |
1921 |
|
T12 |
3816 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |