Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6406232 |
1 |
|
|
T22 |
155 |
|
T23 |
75 |
|
T24 |
648 |
| auto[1] |
4360099 |
1 |
|
|
T23 |
23 |
|
T25 |
976 |
|
T1 |
9235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933727 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
1832604 |
1 |
|
|
T23 |
1 |
|
T25 |
398 |
|
T1 |
3792 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413186 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
4353145 |
1 |
|
|
T23 |
1 |
|
T25 |
847 |
|
T1 |
9008 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1260508 |
1 |
|
|
T25 |
203 |
|
T1 |
2431 |
|
T12 |
5972 |
| auto[1] |
auto[0] |
auto[1] |
914115 |
1 |
|
|
T23 |
1 |
|
T25 |
168 |
|
T1 |
1728 |
| auto[1] |
auto[1] |
auto[0] |
1260033 |
1 |
|
|
T25 |
246 |
|
T1 |
2785 |
|
T12 |
5839 |
| auto[1] |
auto[1] |
auto[1] |
918489 |
1 |
|
|
T25 |
230 |
|
T1 |
2064 |
|
T12 |
3723 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |