Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6426409 |
1 |
|
|
T22 |
155 |
|
T23 |
56 |
|
T24 |
648 |
| auto[1] |
4339922 |
1 |
|
|
T23 |
42 |
|
T25 |
705 |
|
T1 |
8997 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8938548 |
1 |
|
|
T22 |
155 |
|
T23 |
93 |
|
T24 |
648 |
| auto[1] |
1827783 |
1 |
|
|
T23 |
5 |
|
T25 |
329 |
|
T1 |
3715 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6427189 |
1 |
|
|
T22 |
155 |
|
T23 |
93 |
|
T24 |
648 |
| auto[1] |
4339142 |
1 |
|
|
T23 |
5 |
|
T25 |
636 |
|
T1 |
9199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1259708 |
1 |
|
|
T25 |
191 |
|
T1 |
2539 |
|
T12 |
6141 |
| auto[1] |
auto[0] |
auto[1] |
916366 |
1 |
|
|
T23 |
5 |
|
T25 |
178 |
|
T1 |
1830 |
| auto[1] |
auto[1] |
auto[0] |
1251651 |
1 |
|
|
T25 |
116 |
|
T1 |
2945 |
|
T12 |
6143 |
| auto[1] |
auto[1] |
auto[1] |
911417 |
1 |
|
|
T25 |
151 |
|
T1 |
1885 |
|
T12 |
4067 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |