Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416584 |
1 |
|
|
T22 |
155 |
|
T23 |
72 |
|
T24 |
648 |
| auto[1] |
4349747 |
1 |
|
|
T23 |
26 |
|
T25 |
927 |
|
T1 |
9389 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931417 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
1834914 |
1 |
|
|
T23 |
8 |
|
T25 |
380 |
|
T1 |
3961 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6406317 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
4360014 |
1 |
|
|
T23 |
8 |
|
T25 |
846 |
|
T1 |
9499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1270157 |
1 |
|
|
T25 |
174 |
|
T1 |
2786 |
|
T12 |
6285 |
| auto[1] |
auto[0] |
auto[1] |
923569 |
1 |
|
|
T23 |
8 |
|
T25 |
141 |
|
T1 |
1981 |
| auto[1] |
auto[1] |
auto[0] |
1254943 |
1 |
|
|
T25 |
292 |
|
T1 |
2752 |
|
T12 |
5484 |
| auto[1] |
auto[1] |
auto[1] |
911345 |
1 |
|
|
T25 |
239 |
|
T1 |
1980 |
|
T12 |
3548 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |