Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6424609 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4341722 |
1 |
|
|
T23 |
32 |
|
T25 |
1012 |
|
T1 |
8938 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933305 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
1833026 |
1 |
|
|
T23 |
8 |
|
T25 |
414 |
|
T1 |
3866 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6418126 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
4348205 |
1 |
|
|
T23 |
8 |
|
T25 |
799 |
|
T1 |
9164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1268754 |
1 |
|
|
T25 |
120 |
|
T1 |
2589 |
|
T12 |
5538 |
| auto[1] |
auto[0] |
auto[1] |
921359 |
1 |
|
|
T23 |
8 |
|
T25 |
151 |
|
T1 |
1838 |
| auto[1] |
auto[1] |
auto[0] |
1246425 |
1 |
|
|
T25 |
265 |
|
T1 |
2709 |
|
T12 |
6187 |
| auto[1] |
auto[1] |
auto[1] |
911667 |
1 |
|
|
T25 |
263 |
|
T1 |
2028 |
|
T12 |
3927 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |