Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400477 |
1 |
|
|
T22 |
155 |
|
T23 |
62 |
|
T24 |
648 |
| auto[1] |
4365854 |
1 |
|
|
T23 |
36 |
|
T25 |
1000 |
|
T1 |
9225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933407 |
1 |
|
|
T22 |
155 |
|
T23 |
89 |
|
T24 |
648 |
| auto[1] |
1832924 |
1 |
|
|
T23 |
9 |
|
T25 |
525 |
|
T1 |
3719 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6410532 |
1 |
|
|
T22 |
155 |
|
T23 |
86 |
|
T24 |
648 |
| auto[1] |
4355799 |
1 |
|
|
T23 |
12 |
|
T25 |
1011 |
|
T1 |
9024 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1257774 |
1 |
|
|
T23 |
3 |
|
T25 |
174 |
|
T1 |
2574 |
| auto[1] |
auto[0] |
auto[1] |
916620 |
1 |
|
|
T23 |
9 |
|
T25 |
189 |
|
T1 |
1885 |
| auto[1] |
auto[1] |
auto[0] |
1265101 |
1 |
|
|
T25 |
312 |
|
T1 |
2731 |
|
T12 |
5521 |
| auto[1] |
auto[1] |
auto[1] |
916304 |
1 |
|
|
T25 |
336 |
|
T1 |
1834 |
|
T12 |
3654 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |