Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430118 |
1 |
|
|
T22 |
155 |
|
T23 |
77 |
|
T24 |
648 |
| auto[1] |
4336213 |
1 |
|
|
T23 |
21 |
|
T25 |
804 |
|
T1 |
8146 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931389 |
1 |
|
|
T22 |
155 |
|
T23 |
98 |
|
T24 |
648 |
| auto[1] |
1834942 |
1 |
|
|
T25 |
518 |
|
T1 |
3887 |
|
T12 |
7697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6401035 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
4365296 |
1 |
|
|
T23 |
2 |
|
T25 |
1016 |
|
T1 |
9326 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1271304 |
1 |
|
|
T23 |
2 |
|
T25 |
269 |
|
T1 |
3007 |
| auto[1] |
auto[0] |
auto[1] |
921820 |
1 |
|
|
T25 |
260 |
|
T1 |
2153 |
|
T12 |
4159 |
| auto[1] |
auto[1] |
auto[0] |
1259050 |
1 |
|
|
T25 |
229 |
|
T1 |
2432 |
|
T12 |
5907 |
| auto[1] |
auto[1] |
auto[1] |
913122 |
1 |
|
|
T25 |
258 |
|
T1 |
1734 |
|
T12 |
3538 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |