Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6400574 |
1 |
|
|
T22 |
155 |
|
T23 |
70 |
|
T24 |
648 |
| auto[1] |
4365757 |
1 |
|
|
T23 |
28 |
|
T25 |
1036 |
|
T1 |
9307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10209251 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
557080 |
1 |
|
|
T23 |
1 |
|
T25 |
199 |
|
T1 |
1396 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413677 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4352654 |
1 |
|
|
T23 |
18 |
|
T25 |
1022 |
|
T1 |
9768 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1892923 |
1 |
|
|
T23 |
15 |
|
T25 |
302 |
|
T1 |
4327 |
| auto[1] |
auto[0] |
auto[1] |
277521 |
1 |
|
|
T25 |
73 |
|
T1 |
716 |
|
T12 |
1278 |
| auto[1] |
auto[1] |
auto[0] |
1902651 |
1 |
|
|
T23 |
2 |
|
T25 |
521 |
|
T1 |
4045 |
| auto[1] |
auto[1] |
auto[1] |
279559 |
1 |
|
|
T23 |
1 |
|
T25 |
126 |
|
T1 |
680 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |