Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6423619 |
1 |
|
|
T22 |
155 |
|
T23 |
80 |
|
T24 |
648 |
| auto[1] |
4342712 |
1 |
|
|
T23 |
18 |
|
T25 |
831 |
|
T1 |
9664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8947071 |
1 |
|
|
T22 |
155 |
|
T23 |
91 |
|
T24 |
648 |
| auto[1] |
1819260 |
1 |
|
|
T23 |
7 |
|
T25 |
418 |
|
T1 |
4134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6453332 |
1 |
|
|
T22 |
155 |
|
T23 |
91 |
|
T24 |
648 |
| auto[1] |
4312999 |
1 |
|
|
T23 |
7 |
|
T25 |
848 |
|
T1 |
10117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1240552 |
1 |
|
|
T25 |
231 |
|
T1 |
2697 |
|
T12 |
6094 |
| auto[1] |
auto[0] |
auto[1] |
907393 |
1 |
|
|
T23 |
7 |
|
T25 |
215 |
|
T1 |
1846 |
| auto[1] |
auto[1] |
auto[0] |
1253187 |
1 |
|
|
T25 |
199 |
|
T1 |
3286 |
|
T12 |
5891 |
| auto[1] |
auto[1] |
auto[1] |
911867 |
1 |
|
|
T25 |
203 |
|
T1 |
2288 |
|
T12 |
4212 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |