Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6422644 |
1 |
|
|
T22 |
155 |
|
T23 |
66 |
|
T24 |
648 |
| auto[1] |
4343687 |
1 |
|
|
T23 |
32 |
|
T25 |
786 |
|
T1 |
8536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8943309 |
1 |
|
|
T22 |
155 |
|
T23 |
91 |
|
T24 |
648 |
| auto[1] |
1823022 |
1 |
|
|
T23 |
7 |
|
T25 |
434 |
|
T1 |
3790 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6437288 |
1 |
|
|
T22 |
155 |
|
T23 |
88 |
|
T24 |
648 |
| auto[1] |
4329043 |
1 |
|
|
T23 |
10 |
|
T25 |
914 |
|
T1 |
8970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1254305 |
1 |
|
|
T23 |
2 |
|
T25 |
262 |
|
T1 |
2751 |
| auto[1] |
auto[0] |
auto[1] |
915669 |
1 |
|
|
T23 |
4 |
|
T25 |
231 |
|
T1 |
1987 |
| auto[1] |
auto[1] |
auto[0] |
1251716 |
1 |
|
|
T23 |
1 |
|
T25 |
218 |
|
T1 |
2429 |
| auto[1] |
auto[1] |
auto[1] |
907353 |
1 |
|
|
T23 |
3 |
|
T25 |
203 |
|
T1 |
1803 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |