Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6416826 |
1 |
|
|
T22 |
155 |
|
T23 |
68 |
|
T24 |
648 |
| auto[1] |
4349505 |
1 |
|
|
T23 |
30 |
|
T25 |
817 |
|
T1 |
9187 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210756 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
555575 |
1 |
|
|
T23 |
1 |
|
T25 |
116 |
|
T1 |
1217 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417935 |
1 |
|
|
T22 |
155 |
|
T23 |
90 |
|
T24 |
648 |
| auto[1] |
4348396 |
1 |
|
|
T23 |
8 |
|
T25 |
636 |
|
T1 |
8518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1897790 |
1 |
|
|
T23 |
7 |
|
T25 |
299 |
|
T1 |
3619 |
| auto[1] |
auto[0] |
auto[1] |
279175 |
1 |
|
|
T23 |
1 |
|
T25 |
69 |
|
T1 |
600 |
| auto[1] |
auto[1] |
auto[0] |
1895031 |
1 |
|
|
T25 |
221 |
|
T1 |
3682 |
|
T12 |
8910 |
| auto[1] |
auto[1] |
auto[1] |
276400 |
1 |
|
|
T25 |
47 |
|
T1 |
617 |
|
T12 |
1234 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |