Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6418778 |
1 |
|
|
T22 |
155 |
|
T23 |
44 |
|
T24 |
648 |
| auto[1] |
4347553 |
1 |
|
|
T23 |
54 |
|
T25 |
938 |
|
T1 |
8799 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10210094 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
556237 |
1 |
|
|
T23 |
1 |
|
T25 |
160 |
|
T1 |
1322 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6417329 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4349002 |
1 |
|
|
T23 |
14 |
|
T25 |
909 |
|
T1 |
9339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1897574 |
1 |
|
|
T25 |
394 |
|
T1 |
4014 |
|
T12 |
9246 |
| auto[1] |
auto[0] |
auto[1] |
277794 |
1 |
|
|
T25 |
83 |
|
T1 |
683 |
|
T12 |
1275 |
| auto[1] |
auto[1] |
auto[0] |
1895191 |
1 |
|
|
T23 |
13 |
|
T25 |
355 |
|
T1 |
4003 |
| auto[1] |
auto[1] |
auto[1] |
278443 |
1 |
|
|
T23 |
1 |
|
T25 |
77 |
|
T1 |
639 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |