Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6413047 |
1 |
|
|
T22 |
155 |
|
T23 |
61 |
|
T24 |
648 |
| auto[1] |
4353284 |
1 |
|
|
T23 |
37 |
|
T25 |
860 |
|
T1 |
9134 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10211435 |
1 |
|
|
T22 |
155 |
|
T23 |
96 |
|
T24 |
648 |
| auto[1] |
554896 |
1 |
|
|
T23 |
2 |
|
T25 |
146 |
|
T1 |
1246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6434765 |
1 |
|
|
T22 |
155 |
|
T23 |
74 |
|
T24 |
648 |
| auto[1] |
4331566 |
1 |
|
|
T23 |
24 |
|
T25 |
806 |
|
T1 |
8726 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1885439 |
1 |
|
|
T23 |
10 |
|
T25 |
303 |
|
T1 |
3827 |
| auto[1] |
auto[0] |
auto[1] |
277224 |
1 |
|
|
T25 |
67 |
|
T1 |
625 |
|
T12 |
1117 |
| auto[1] |
auto[1] |
auto[0] |
1891231 |
1 |
|
|
T23 |
12 |
|
T25 |
357 |
|
T1 |
3653 |
| auto[1] |
auto[1] |
auto[1] |
277672 |
1 |
|
|
T23 |
2 |
|
T25 |
79 |
|
T1 |
621 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |