Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6425051 |
1 |
|
|
T22 |
155 |
|
T23 |
59 |
|
T24 |
648 |
| auto[1] |
4341280 |
1 |
|
|
T23 |
39 |
|
T25 |
914 |
|
T1 |
8106 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10208992 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
557339 |
1 |
|
|
T23 |
1 |
|
T25 |
135 |
|
T1 |
1305 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6419678 |
1 |
|
|
T22 |
155 |
|
T23 |
87 |
|
T24 |
648 |
| auto[1] |
4346653 |
1 |
|
|
T23 |
11 |
|
T25 |
657 |
|
T1 |
9205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1903411 |
1 |
|
|
T23 |
3 |
|
T25 |
257 |
|
T1 |
4235 |
| auto[1] |
auto[0] |
auto[1] |
279545 |
1 |
|
|
T25 |
60 |
|
T1 |
727 |
|
T12 |
1135 |
| auto[1] |
auto[1] |
auto[0] |
1885903 |
1 |
|
|
T23 |
7 |
|
T25 |
265 |
|
T1 |
3665 |
| auto[1] |
auto[1] |
auto[1] |
277794 |
1 |
|
|
T23 |
1 |
|
T25 |
75 |
|
T1 |
578 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |