Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412266 |
1 |
|
|
T22 |
155 |
|
T23 |
78 |
|
T24 |
648 |
| auto[1] |
4354065 |
1 |
|
|
T23 |
20 |
|
T25 |
761 |
|
T1 |
10032 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10209481 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
556850 |
1 |
|
|
T23 |
1 |
|
T25 |
146 |
|
T1 |
1192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6412346 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4353985 |
1 |
|
|
T23 |
14 |
|
T25 |
814 |
|
T1 |
8685 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1901708 |
1 |
|
|
T23 |
4 |
|
T25 |
366 |
|
T1 |
3168 |
| auto[1] |
auto[0] |
auto[1] |
278296 |
1 |
|
|
T23 |
1 |
|
T25 |
81 |
|
T1 |
480 |
| auto[1] |
auto[1] |
auto[0] |
1895427 |
1 |
|
|
T23 |
9 |
|
T25 |
302 |
|
T1 |
4325 |
| auto[1] |
auto[1] |
auto[1] |
278554 |
1 |
|
|
T25 |
65 |
|
T1 |
712 |
|
T12 |
1093 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |