Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428870 |
1 |
|
|
T22 |
155 |
|
T23 |
70 |
|
T24 |
648 |
| auto[1] |
4337461 |
1 |
|
|
T23 |
28 |
|
T25 |
1095 |
|
T1 |
9542 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10213818 |
1 |
|
|
T22 |
155 |
|
T23 |
97 |
|
T24 |
648 |
| auto[1] |
552513 |
1 |
|
|
T23 |
1 |
|
T25 |
131 |
|
T1 |
1240 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6437461 |
1 |
|
|
T22 |
155 |
|
T23 |
84 |
|
T24 |
648 |
| auto[1] |
4328870 |
1 |
|
|
T23 |
14 |
|
T25 |
695 |
|
T1 |
8767 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1899135 |
1 |
|
|
T23 |
6 |
|
T25 |
202 |
|
T1 |
3495 |
| auto[1] |
auto[0] |
auto[1] |
277363 |
1 |
|
|
T25 |
45 |
|
T1 |
592 |
|
T12 |
1213 |
| auto[1] |
auto[1] |
auto[0] |
1877222 |
1 |
|
|
T23 |
7 |
|
T25 |
362 |
|
T1 |
4032 |
| auto[1] |
auto[1] |
auto[1] |
275150 |
1 |
|
|
T23 |
1 |
|
T25 |
86 |
|
T1 |
648 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |