Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 935
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T761 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3283188957 Aug 04 04:25:38 PM PDT 24 Aug 04 04:25:39 PM PDT 24 27815336 ps
T762 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2935617981 Aug 04 04:24:08 PM PDT 24 Aug 04 04:24:08 PM PDT 24 36345699 ps
T108 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1092080254 Aug 04 04:23:32 PM PDT 24 Aug 04 04:23:32 PM PDT 24 14794781 ps
T763 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.791937317 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:37 PM PDT 24 37767259 ps
T764 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1440744810 Aug 04 04:25:39 PM PDT 24 Aug 04 04:25:40 PM PDT 24 171834726 ps
T765 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1136149399 Aug 04 04:23:56 PM PDT 24 Aug 04 04:23:57 PM PDT 24 37625361 ps
T100 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1932420049 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:34 PM PDT 24 12060964 ps
T766 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1747839613 Aug 04 04:25:32 PM PDT 24 Aug 04 04:25:35 PM PDT 24 120678922 ps
T767 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2166914965 Aug 04 04:23:54 PM PDT 24 Aug 04 04:23:55 PM PDT 24 57154606 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4006889847 Aug 04 04:21:51 PM PDT 24 Aug 04 04:21:51 PM PDT 24 31140107 ps
T769 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1946558024 Aug 04 04:25:58 PM PDT 24 Aug 04 04:25:59 PM PDT 24 155537356 ps
T770 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2135722356 Aug 04 04:23:50 PM PDT 24 Aug 04 04:23:51 PM PDT 24 22551860 ps
T43 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.146316877 Aug 04 04:25:37 PM PDT 24 Aug 04 04:25:38 PM PDT 24 49827853 ps
T101 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1348533852 Aug 04 04:25:58 PM PDT 24 Aug 04 04:26:00 PM PDT 24 21185734 ps
T102 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.901374684 Aug 04 04:25:34 PM PDT 24 Aug 04 04:25:35 PM PDT 24 16930644 ps
T771 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3473871326 Aug 04 04:22:36 PM PDT 24 Aug 04 04:22:37 PM PDT 24 17635209 ps
T772 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3201529452 Aug 04 04:25:37 PM PDT 24 Aug 04 04:25:38 PM PDT 24 22712077 ps
T773 /workspace/coverage/cover_reg_top/27.gpio_intr_test.784520646 Aug 04 04:22:25 PM PDT 24 Aug 04 04:22:26 PM PDT 24 11920906 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3942157355 Aug 04 04:23:14 PM PDT 24 Aug 04 04:23:15 PM PDT 24 74616277 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2438122567 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 50173512 ps
T776 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.869854852 Aug 04 04:25:36 PM PDT 24 Aug 04 04:25:37 PM PDT 24 59209122 ps
T777 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3663412555 Aug 04 04:25:32 PM PDT 24 Aug 04 04:25:33 PM PDT 24 27579578 ps
T778 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2372444049 Aug 04 04:25:41 PM PDT 24 Aug 04 04:25:42 PM PDT 24 22894001 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3125304624 Aug 04 04:22:54 PM PDT 24 Aug 04 04:22:56 PM PDT 24 47221732 ps
T780 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1683664494 Aug 04 04:25:47 PM PDT 24 Aug 04 04:25:48 PM PDT 24 50107753 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1638589207 Aug 04 04:26:02 PM PDT 24 Aug 04 04:26:03 PM PDT 24 109100259 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3788549504 Aug 04 04:26:02 PM PDT 24 Aug 04 04:26:02 PM PDT 24 22862296 ps
T783 /workspace/coverage/cover_reg_top/36.gpio_intr_test.124431730 Aug 04 04:26:34 PM PDT 24 Aug 04 04:26:35 PM PDT 24 64179818 ps
T784 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.147829111 Aug 04 04:25:58 PM PDT 24 Aug 04 04:26:01 PM PDT 24 192959377 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3280694413 Aug 04 04:21:15 PM PDT 24 Aug 04 04:21:16 PM PDT 24 12620553 ps
T786 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3275790914 Aug 04 04:25:43 PM PDT 24 Aug 04 04:25:43 PM PDT 24 12438377 ps
T787 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3844040162 Aug 04 04:24:14 PM PDT 24 Aug 04 04:24:15 PM PDT 24 13591278 ps
T788 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4116879004 Aug 04 04:23:19 PM PDT 24 Aug 04 04:23:20 PM PDT 24 13848544 ps
T103 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1863032437 Aug 04 04:23:18 PM PDT 24 Aug 04 04:23:20 PM PDT 24 95632736 ps
T789 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3659000890 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:36 PM PDT 24 16306462 ps
T790 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.687060718 Aug 04 04:25:58 PM PDT 24 Aug 04 04:26:00 PM PDT 24 212931499 ps
T791 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3328192347 Aug 04 04:26:00 PM PDT 24 Aug 04 04:26:01 PM PDT 24 34264773 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1277382718 Aug 04 04:24:09 PM PDT 24 Aug 04 04:24:10 PM PDT 24 136355628 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1094060344 Aug 04 04:25:44 PM PDT 24 Aug 04 04:25:45 PM PDT 24 80461889 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.478873378 Aug 04 04:22:10 PM PDT 24 Aug 04 04:22:11 PM PDT 24 45185008 ps
T795 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1435110423 Aug 04 04:25:38 PM PDT 24 Aug 04 04:25:39 PM PDT 24 17910186 ps
T796 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1161084297 Aug 04 04:24:08 PM PDT 24 Aug 04 04:24:09 PM PDT 24 132499106 ps
T797 /workspace/coverage/cover_reg_top/18.gpio_intr_test.458365203 Aug 04 04:23:18 PM PDT 24 Aug 04 04:23:19 PM PDT 24 19786384 ps
T798 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3059148478 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:36 PM PDT 24 17059059 ps
T799 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3163000113 Aug 04 04:21:21 PM PDT 24 Aug 04 04:21:23 PM PDT 24 34119138 ps
T800 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1252044321 Aug 04 04:23:52 PM PDT 24 Aug 04 04:23:54 PM PDT 24 184494221 ps
T801 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2367800022 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:00 PM PDT 24 16460274 ps
T802 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2106357406 Aug 04 04:25:34 PM PDT 24 Aug 04 04:25:35 PM PDT 24 13572149 ps
T104 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3106663166 Aug 04 04:25:30 PM PDT 24 Aug 04 04:25:31 PM PDT 24 13328871 ps
T803 /workspace/coverage/cover_reg_top/49.gpio_intr_test.449871164 Aug 04 04:22:35 PM PDT 24 Aug 04 04:22:35 PM PDT 24 39002539 ps
T804 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1864061327 Aug 04 04:22:02 PM PDT 24 Aug 04 04:22:03 PM PDT 24 15593117 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3463314632 Aug 04 04:22:34 PM PDT 24 Aug 04 04:22:35 PM PDT 24 68259139 ps
T105 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1867009845 Aug 04 04:25:36 PM PDT 24 Aug 04 04:25:37 PM PDT 24 12634625 ps
T806 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2972943865 Aug 04 04:21:33 PM PDT 24 Aug 04 04:21:33 PM PDT 24 92398423 ps
T106 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2169939282 Aug 04 04:24:08 PM PDT 24 Aug 04 04:24:08 PM PDT 24 14953303 ps
T807 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2982576010 Aug 04 04:25:57 PM PDT 24 Aug 04 04:25:59 PM PDT 24 73473539 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1703432302 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:37 PM PDT 24 101898288 ps
T107 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2415146212 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:36 PM PDT 24 595548075 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3906295082 Aug 04 04:22:11 PM PDT 24 Aug 04 04:22:12 PM PDT 24 19534563 ps
T810 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3848119125 Aug 04 04:25:58 PM PDT 24 Aug 04 04:25:59 PM PDT 24 16731087 ps
T811 /workspace/coverage/cover_reg_top/8.gpio_intr_test.104059118 Aug 04 04:21:51 PM PDT 24 Aug 04 04:21:52 PM PDT 24 52561286 ps
T812 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.186112695 Aug 04 04:26:02 PM PDT 24 Aug 04 04:26:03 PM PDT 24 87122951 ps
T813 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3419389256 Aug 04 04:23:50 PM PDT 24 Aug 04 04:23:51 PM PDT 24 12505334 ps
T814 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2704267868 Aug 04 04:22:00 PM PDT 24 Aug 04 04:22:01 PM PDT 24 14746227 ps
T815 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2259012753 Aug 04 04:21:44 PM PDT 24 Aug 04 04:21:45 PM PDT 24 104858010 ps
T816 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2186847848 Aug 04 04:22:23 PM PDT 24 Aug 04 04:22:24 PM PDT 24 15843662 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2931481936 Aug 04 04:22:10 PM PDT 24 Aug 04 04:22:11 PM PDT 24 20456293 ps
T818 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3827296376 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:56 PM PDT 24 83279980 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2468759762 Aug 04 04:25:36 PM PDT 24 Aug 04 04:25:38 PM PDT 24 21748953 ps
T820 /workspace/coverage/cover_reg_top/23.gpio_intr_test.4013051624 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:57 PM PDT 24 31620541 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3329836014 Aug 04 04:23:22 PM PDT 24 Aug 04 04:23:23 PM PDT 24 40231481 ps
T822 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2735388128 Aug 04 04:25:58 PM PDT 24 Aug 04 04:25:58 PM PDT 24 18208770 ps
T823 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2081306718 Aug 04 04:24:14 PM PDT 24 Aug 04 04:24:17 PM PDT 24 210102721 ps
T824 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3146124489 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 16897195 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.528197776 Aug 04 04:22:22 PM PDT 24 Aug 04 04:22:23 PM PDT 24 47998255 ps
T826 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3280285070 Aug 04 04:22:32 PM PDT 24 Aug 04 04:22:32 PM PDT 24 40860136 ps
T827 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4224267475 Aug 04 04:22:44 PM PDT 24 Aug 04 04:22:44 PM PDT 24 14942599 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1891345365 Aug 04 04:23:56 PM PDT 24 Aug 04 04:23:57 PM PDT 24 75776508 ps
T829 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3628015123 Aug 04 04:21:53 PM PDT 24 Aug 04 04:21:54 PM PDT 24 12335836 ps
T830 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3600602035 Aug 04 04:22:50 PM PDT 24 Aug 04 04:22:51 PM PDT 24 13878942 ps
T831 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2359333871 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:55 PM PDT 24 47020137 ps
T832 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3044133664 Aug 04 04:25:42 PM PDT 24 Aug 04 04:25:43 PM PDT 24 177987788 ps
T833 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1791307692 Aug 04 04:26:30 PM PDT 24 Aug 04 04:26:31 PM PDT 24 17071359 ps
T834 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3465869969 Aug 04 04:26:25 PM PDT 24 Aug 04 04:26:26 PM PDT 24 50514891 ps
T835 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1269426829 Aug 04 04:21:55 PM PDT 24 Aug 04 04:21:56 PM PDT 24 109086619 ps
T836 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3120255539 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:56 PM PDT 24 177562746 ps
T837 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3005526055 Aug 04 04:23:57 PM PDT 24 Aug 04 04:23:58 PM PDT 24 579344238 ps
T838 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3892546332 Aug 04 04:24:14 PM PDT 24 Aug 04 04:24:15 PM PDT 24 59639300 ps
T839 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1165348865 Aug 04 04:25:47 PM PDT 24 Aug 04 04:25:47 PM PDT 24 320437811 ps
T840 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541467265 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:53 PM PDT 24 33246533 ps
T841 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1213761548 Aug 04 04:24:09 PM PDT 24 Aug 04 04:24:10 PM PDT 24 424933180 ps
T842 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.754909933 Aug 04 04:25:58 PM PDT 24 Aug 04 04:26:00 PM PDT 24 56749766 ps
T843 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2686802813 Aug 04 04:22:11 PM PDT 24 Aug 04 04:22:12 PM PDT 24 37753054 ps
T844 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3983176933 Aug 04 04:24:13 PM PDT 24 Aug 04 04:24:14 PM PDT 24 208805690 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3575582164 Aug 04 04:24:14 PM PDT 24 Aug 04 04:24:16 PM PDT 24 40480095 ps
T846 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2601556283 Aug 04 04:21:16 PM PDT 24 Aug 04 04:21:17 PM PDT 24 39048363 ps
T847 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.398223407 Aug 04 04:22:03 PM PDT 24 Aug 04 04:22:04 PM PDT 24 173636028 ps
T848 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111500754 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:58 PM PDT 24 77025156 ps
T849 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2327346350 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:00 PM PDT 24 147694044 ps
T850 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3815905948 Aug 04 04:22:02 PM PDT 24 Aug 04 04:22:03 PM PDT 24 42453821 ps
T851 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2887260135 Aug 04 04:26:05 PM PDT 24 Aug 04 04:26:06 PM PDT 24 56289630 ps
T852 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.663186866 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:35 PM PDT 24 67219767 ps
T853 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1098081 Aug 04 04:26:04 PM PDT 24 Aug 04 04:26:05 PM PDT 24 291160411 ps
T854 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.955797167 Aug 04 04:25:21 PM PDT 24 Aug 04 04:25:23 PM PDT 24 89798577 ps
T855 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1842618739 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:57 PM PDT 24 27177318 ps
T856 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2506278725 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 25749891 ps
T857 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376701833 Aug 04 04:25:41 PM PDT 24 Aug 04 04:25:43 PM PDT 24 43513208 ps
T858 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.687771938 Aug 04 04:25:47 PM PDT 24 Aug 04 04:25:48 PM PDT 24 158406484 ps
T859 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2202305015 Aug 04 04:23:27 PM PDT 24 Aug 04 04:23:28 PM PDT 24 413107773 ps
T860 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3405572105 Aug 04 04:23:10 PM PDT 24 Aug 04 04:23:11 PM PDT 24 82876833 ps
T861 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1748113574 Aug 04 04:25:58 PM PDT 24 Aug 04 04:26:00 PM PDT 24 26768189 ps
T862 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3909032353 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:00 PM PDT 24 65158436 ps
T863 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735300632 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:01 PM PDT 24 895105021 ps
T864 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4275340352 Aug 04 04:25:19 PM PDT 24 Aug 04 04:25:21 PM PDT 24 196868145 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3499718893 Aug 04 04:20:43 PM PDT 24 Aug 04 04:20:44 PM PDT 24 236927911 ps
T866 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.245856157 Aug 04 04:23:56 PM PDT 24 Aug 04 04:23:58 PM PDT 24 134907605 ps
T867 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63800624 Aug 04 04:24:10 PM PDT 24 Aug 04 04:24:11 PM PDT 24 148819712 ps
T868 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2912882739 Aug 04 04:23:18 PM PDT 24 Aug 04 04:23:20 PM PDT 24 557155373 ps
T869 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1172399890 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:58 PM PDT 24 158293104 ps
T870 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3819890636 Aug 04 04:25:48 PM PDT 24 Aug 04 04:25:49 PM PDT 24 26194198 ps
T871 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1108933321 Aug 04 04:23:53 PM PDT 24 Aug 04 04:23:54 PM PDT 24 63680305 ps
T872 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.307327709 Aug 04 04:24:07 PM PDT 24 Aug 04 04:24:08 PM PDT 24 148121258 ps
T873 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2932676782 Aug 04 04:25:59 PM PDT 24 Aug 04 04:26:00 PM PDT 24 198193111 ps
T874 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3528464001 Aug 04 04:22:10 PM PDT 24 Aug 04 04:22:11 PM PDT 24 97976506 ps
T875 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1923046606 Aug 04 04:21:18 PM PDT 24 Aug 04 04:21:20 PM PDT 24 87014851 ps
T876 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3679618867 Aug 04 04:26:00 PM PDT 24 Aug 04 04:26:01 PM PDT 24 94842872 ps
T877 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2978237837 Aug 04 04:24:05 PM PDT 24 Aug 04 04:24:06 PM PDT 24 82010295 ps
T878 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3645201804 Aug 04 04:22:43 PM PDT 24 Aug 04 04:22:44 PM PDT 24 199565928 ps
T879 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2844659160 Aug 04 04:25:57 PM PDT 24 Aug 04 04:25:58 PM PDT 24 32180438 ps
T880 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1883357209 Aug 04 04:22:29 PM PDT 24 Aug 04 04:22:30 PM PDT 24 482695438 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193827263 Aug 04 04:23:58 PM PDT 24 Aug 04 04:24:00 PM PDT 24 88786050 ps
T882 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3581737752 Aug 04 04:22:08 PM PDT 24 Aug 04 04:22:09 PM PDT 24 58215395 ps
T883 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2255197879 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:35 PM PDT 24 184985553 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1251601309 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:54 PM PDT 24 77325739 ps
T885 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1097201602 Aug 04 04:25:43 PM PDT 24 Aug 04 04:25:44 PM PDT 24 230615341 ps
T886 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.380321987 Aug 04 04:22:52 PM PDT 24 Aug 04 04:22:54 PM PDT 24 224947818 ps
T887 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2088811989 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:54 PM PDT 24 562888966 ps
T888 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.510777635 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:00 PM PDT 24 196555071 ps
T889 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292253080 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:35 PM PDT 24 147467690 ps
T890 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3984195489 Aug 04 04:24:09 PM PDT 24 Aug 04 04:24:10 PM PDT 24 104310683 ps
T891 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2685938780 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 108882093 ps
T892 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1109934309 Aug 04 04:21:36 PM PDT 24 Aug 04 04:21:37 PM PDT 24 51613221 ps
T893 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1429308603 Aug 04 04:23:57 PM PDT 24 Aug 04 04:23:58 PM PDT 24 129805822 ps
T894 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3567670683 Aug 04 04:23:52 PM PDT 24 Aug 04 04:23:53 PM PDT 24 185996801 ps
T895 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1387150661 Aug 04 04:20:56 PM PDT 24 Aug 04 04:20:58 PM PDT 24 248357893 ps
T896 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509084733 Aug 04 04:23:27 PM PDT 24 Aug 04 04:23:28 PM PDT 24 81626041 ps
T897 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.926630830 Aug 04 04:21:03 PM PDT 24 Aug 04 04:21:05 PM PDT 24 297057056 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852578563 Aug 04 04:21:51 PM PDT 24 Aug 04 04:21:52 PM PDT 24 36261595 ps
T899 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3804039389 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 279653925 ps
T900 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2276743182 Aug 04 04:25:54 PM PDT 24 Aug 04 04:25:55 PM PDT 24 32486231 ps
T901 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1138793216 Aug 04 04:23:03 PM PDT 24 Aug 04 04:23:04 PM PDT 24 55568602 ps
T902 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4281113076 Aug 04 04:25:47 PM PDT 24 Aug 04 04:25:48 PM PDT 24 54716497 ps
T903 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497322024 Aug 04 04:23:23 PM PDT 24 Aug 04 04:23:25 PM PDT 24 69217043 ps
T904 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471875589 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:01 PM PDT 24 340657072 ps
T905 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667769389 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:58 PM PDT 24 52685125 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3414202373 Aug 04 04:23:52 PM PDT 24 Aug 04 04:23:53 PM PDT 24 432477472 ps
T907 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2231010559 Aug 04 04:25:21 PM PDT 24 Aug 04 04:25:23 PM PDT 24 339008055 ps
T908 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3043892731 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:36 PM PDT 24 42495053 ps
T909 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716844102 Aug 04 04:22:11 PM PDT 24 Aug 04 04:22:13 PM PDT 24 230506820 ps
T910 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2794784153 Aug 04 04:21:31 PM PDT 24 Aug 04 04:21:32 PM PDT 24 30241274 ps
T911 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1459624191 Aug 04 04:24:10 PM PDT 24 Aug 04 04:24:12 PM PDT 24 164884453 ps
T912 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1528067339 Aug 04 04:23:13 PM PDT 24 Aug 04 04:23:15 PM PDT 24 299751446 ps
T913 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1659752185 Aug 04 04:21:26 PM PDT 24 Aug 04 04:21:27 PM PDT 24 72605433 ps
T914 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.561654438 Aug 04 04:24:08 PM PDT 24 Aug 04 04:24:09 PM PDT 24 332700201 ps
T915 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.716818809 Aug 04 04:21:30 PM PDT 24 Aug 04 04:21:31 PM PDT 24 32936446 ps
T916 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1623213568 Aug 04 04:25:55 PM PDT 24 Aug 04 04:25:56 PM PDT 24 71519863 ps
T917 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751662286 Aug 04 04:23:55 PM PDT 24 Aug 04 04:23:56 PM PDT 24 32421549 ps
T918 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2996334868 Aug 04 04:20:53 PM PDT 24 Aug 04 04:20:54 PM PDT 24 88541448 ps
T919 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2484013800 Aug 04 04:23:53 PM PDT 24 Aug 04 04:23:54 PM PDT 24 155054157 ps
T920 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3266860406 Aug 04 04:24:06 PM PDT 24 Aug 04 04:24:07 PM PDT 24 264092258 ps
T921 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.777785530 Aug 04 04:25:36 PM PDT 24 Aug 04 04:25:37 PM PDT 24 25708414 ps
T922 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.641788383 Aug 04 04:22:45 PM PDT 24 Aug 04 04:22:46 PM PDT 24 104669056 ps
T923 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.745409274 Aug 04 04:22:12 PM PDT 24 Aug 04 04:22:14 PM PDT 24 250328780 ps
T924 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2939038979 Aug 04 04:23:57 PM PDT 24 Aug 04 04:23:58 PM PDT 24 568102738 ps
T925 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399180785 Aug 04 04:25:47 PM PDT 24 Aug 04 04:25:48 PM PDT 24 81786572 ps
T926 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3567671983 Aug 04 04:21:51 PM PDT 24 Aug 04 04:21:52 PM PDT 24 704234732 ps
T927 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2674619260 Aug 04 04:23:05 PM PDT 24 Aug 04 04:23:06 PM PDT 24 47779540 ps
T928 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.300806215 Aug 04 04:24:12 PM PDT 24 Aug 04 04:24:13 PM PDT 24 50547396 ps
T929 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3927373497 Aug 04 04:23:31 PM PDT 24 Aug 04 04:23:32 PM PDT 24 361696075 ps
T930 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2813394946 Aug 04 04:23:59 PM PDT 24 Aug 04 04:24:00 PM PDT 24 174947369 ps
T931 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2004186200 Aug 04 04:23:57 PM PDT 24 Aug 04 04:23:58 PM PDT 24 117602335 ps
T932 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486063447 Aug 04 04:24:14 PM PDT 24 Aug 04 04:24:16 PM PDT 24 54757151 ps
T933 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855713571 Aug 04 04:23:19 PM PDT 24 Aug 04 04:23:20 PM PDT 24 45996281 ps
T934 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3900355219 Aug 04 04:22:13 PM PDT 24 Aug 04 04:22:15 PM PDT 24 78186766 ps
T935 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2557581276 Aug 04 04:25:51 PM PDT 24 Aug 04 04:25:52 PM PDT 24 325915277 ps

Test location /workspace/coverage/default/47.gpio_full_random.1645936941
Short name T23
Test name
Test status
Simulation time 1035700292 ps
CPU time 0.94 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 197336 kb
Host smart-ac6d5df1-7fed-418d-8a14-3d32536e3334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645936941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1645936941
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3312042303
Short name T24
Test name
Test status
Simulation time 44628667 ps
CPU time 1.66 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 196820 kb
Host smart-e5d644e8-5bf4-410d-b653-893d0ce890cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312042303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3312042303
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4092583259
Short name T56
Test name
Test status
Simulation time 54995477574 ps
CPU time 1449.02 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 05:00:54 PM PDT 24
Peak memory 198760 kb
Host smart-db9f9f20-cf6b-41c6-a16f-a4259da00ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4092583259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4092583259
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3194380163
Short name T2
Test name
Test status
Simulation time 1470839624 ps
CPU time 4.64 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:51 PM PDT 24
Peak memory 198484 kb
Host smart-f4458695-db01-4f9e-95e5-ad2df4471584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194380163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3194380163
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.507630661
Short name T33
Test name
Test status
Simulation time 157805671 ps
CPU time 1 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 215432 kb
Host smart-e95df813-9ac6-477e-9e65-dc0cef434071
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507630661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.507630661
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1365098341
Short name T31
Test name
Test status
Simulation time 445268165 ps
CPU time 1.38 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 197744 kb
Host smart-dab691bc-ce2d-4457-97ed-297f65812967
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365098341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1365098341
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/16.gpio_alert_test.468965433
Short name T180
Test name
Test status
Simulation time 15029876 ps
CPU time 0.57 seconds
Started Aug 04 04:36:49 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 194348 kb
Host smart-7c072f7d-e166-4501-a507-827afc324030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468965433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.468965433
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2656667726
Short name T82
Test name
Test status
Simulation time 94102109 ps
CPU time 0.72 seconds
Started Aug 04 04:23:56 PM PDT 24
Finished Aug 04 04:23:57 PM PDT 24
Peak memory 196240 kb
Host smart-7846860a-997b-4d16-9245-bed6632ad5f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656667726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2656667726
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1132376639
Short name T12
Test name
Test status
Simulation time 10796897942 ps
CPU time 67.56 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 198672 kb
Host smart-342e15d4-e33c-4bf3-8b93-a91a552127d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132376639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1132376639
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2357614280
Short name T113
Test name
Test status
Simulation time 23077595 ps
CPU time 0.7 seconds
Started Aug 04 04:25:37 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 193804 kb
Host smart-fb0304cd-7c6f-4968-96fc-b91f2492fbd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357614280 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2357614280
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3465869969
Short name T834
Test name
Test status
Simulation time 50514891 ps
CPU time 0.82 seconds
Started Aug 04 04:26:25 PM PDT 24
Finished Aug 04 04:26:26 PM PDT 24
Peak memory 198008 kb
Host smart-518eb7c1-abfb-4970-9d76-66e8e2eb76a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465869969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3465869969
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1094060344
Short name T793
Test name
Test status
Simulation time 80461889 ps
CPU time 1.08 seconds
Started Aug 04 04:25:44 PM PDT 24
Finished Aug 04 04:25:45 PM PDT 24
Peak memory 197684 kb
Host smart-4d12ef0e-2145-445d-99d4-dfa40aff40fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094060344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1094060344
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.559275662
Short name T744
Test name
Test status
Simulation time 1308980271 ps
CPU time 3.13 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 196036 kb
Host smart-f7d0d81b-5980-4e58-8233-e1c0ba24ffb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559275662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.559275662
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1648906055
Short name T80
Test name
Test status
Simulation time 48817795 ps
CPU time 0.66 seconds
Started Aug 04 04:22:33 PM PDT 24
Finished Aug 04 04:22:34 PM PDT 24
Peak memory 194972 kb
Host smart-456d15ac-0939-491c-a260-ad8e52e3c33a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648906055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1648906055
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3308563756
Short name T749
Test name
Test status
Simulation time 113645590 ps
CPU time 0.91 seconds
Started Aug 04 04:23:34 PM PDT 24
Finished Aug 04 04:23:35 PM PDT 24
Peak memory 198468 kb
Host smart-f12118fe-5ed2-4a16-b8f5-6f422ad1457d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308563756 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3308563756
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3419389256
Short name T813
Test name
Test status
Simulation time 12505334 ps
CPU time 0.62 seconds
Started Aug 04 04:23:50 PM PDT 24
Finished Aug 04 04:23:51 PM PDT 24
Peak memory 193900 kb
Host smart-7c7d020e-e0d9-4f3f-9894-14c852e810c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419389256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3419389256
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2931481936
Short name T817
Test name
Test status
Simulation time 20456293 ps
CPU time 0.63 seconds
Started Aug 04 04:22:10 PM PDT 24
Finished Aug 04 04:22:11 PM PDT 24
Peak memory 194336 kb
Host smart-464dfda2-cceb-40c0-a2ef-688fd140c7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931481936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2931481936
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1136149399
Short name T765
Test name
Test status
Simulation time 37625361 ps
CPU time 0.83 seconds
Started Aug 04 04:23:56 PM PDT 24
Finished Aug 04 04:23:57 PM PDT 24
Peak memory 196084 kb
Host smart-38c54ec2-1c56-4a6d-b397-96df1bfbc79e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136149399 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1136149399
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2192330898
Short name T745
Test name
Test status
Simulation time 34587673 ps
CPU time 0.86 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 198116 kb
Host smart-b0da6ec6-ca1e-45a6-bccb-172e008229ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192330898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2192330898
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1891345365
Short name T828
Test name
Test status
Simulation time 75776508 ps
CPU time 0.83 seconds
Started Aug 04 04:23:56 PM PDT 24
Finished Aug 04 04:23:57 PM PDT 24
Peak memory 196216 kb
Host smart-8c2f6853-3451-46fb-9600-511c27f0489b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891345365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1891345365
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1867009845
Short name T105
Test name
Test status
Simulation time 12634625 ps
CPU time 0.63 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 194992 kb
Host smart-7399a4b1-c544-482b-a6b8-8cab02748d13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867009845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1867009845
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3163000113
Short name T799
Test name
Test status
Simulation time 34119138 ps
CPU time 1.42 seconds
Started Aug 04 04:21:21 PM PDT 24
Finished Aug 04 04:21:23 PM PDT 24
Peak memory 198536 kb
Host smart-a511e0bd-31e8-4b3a-bc2f-ab79a8b21240
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163000113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3163000113
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2499419540
Short name T760
Test name
Test status
Simulation time 73753095 ps
CPU time 0.69 seconds
Started Aug 04 04:21:28 PM PDT 24
Finished Aug 04 04:21:29 PM PDT 24
Peak memory 195220 kb
Host smart-281ba2d3-6399-4074-b824-95708d02e493
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499419540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2499419540
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1752370093
Short name T718
Test name
Test status
Simulation time 24252634 ps
CPU time 1.07 seconds
Started Aug 04 04:25:42 PM PDT 24
Finished Aug 04 04:25:44 PM PDT 24
Peak memory 198652 kb
Host smart-07d1f6a2-ea06-4e28-88e6-a5ae93b9d8ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752370093 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1752370093
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1932420049
Short name T100
Test name
Test status
Simulation time 12060964 ps
CPU time 0.64 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:34 PM PDT 24
Peak memory 193596 kb
Host smart-8a25e037-161d-4cd6-a517-bbb28df9e018
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932420049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1932420049
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3275790914
Short name T786
Test name
Test status
Simulation time 12438377 ps
CPU time 0.59 seconds
Started Aug 04 04:25:43 PM PDT 24
Finished Aug 04 04:25:43 PM PDT 24
Peak memory 195052 kb
Host smart-4527ba21-0045-4101-9efc-5f97f8b98589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275790914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3275790914
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3942157355
Short name T774
Test name
Test status
Simulation time 74616277 ps
CPU time 0.79 seconds
Started Aug 04 04:23:14 PM PDT 24
Finished Aug 04 04:23:15 PM PDT 24
Peak memory 196512 kb
Host smart-d678d8a7-cbd6-4916-85fb-4104557d597a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942157355 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3942157355
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1537307699
Short name T734
Test name
Test status
Simulation time 795847713 ps
CPU time 2.05 seconds
Started Aug 04 04:26:21 PM PDT 24
Finished Aug 04 04:26:23 PM PDT 24
Peak memory 198532 kb
Host smart-217ced3f-f0d2-42a8-a54a-30e707c4b9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537307699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1537307699
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3140539186
Short name T754
Test name
Test status
Simulation time 23248544 ps
CPU time 0.76 seconds
Started Aug 04 04:26:03 PM PDT 24
Finished Aug 04 04:26:04 PM PDT 24
Peak memory 198004 kb
Host smart-a709e470-5c0b-4d8e-b143-ae90f4ba4f06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140539186 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3140539186
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4115287448
Short name T78
Test name
Test status
Simulation time 33413619 ps
CPU time 0.6 seconds
Started Aug 04 04:21:49 PM PDT 24
Finished Aug 04 04:21:50 PM PDT 24
Peak memory 194412 kb
Host smart-fe0ba101-e971-4c28-bffa-70005fcd86b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115287448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.4115287448
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.77263526
Short name T717
Test name
Test status
Simulation time 29833648 ps
CPU time 0.61 seconds
Started Aug 04 04:21:52 PM PDT 24
Finished Aug 04 04:21:52 PM PDT 24
Peak memory 194396 kb
Host smart-39d71291-9a0e-4ce1-a0f3-9bc2281134d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77263526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.77263526
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4006889847
Short name T768
Test name
Test status
Simulation time 31140107 ps
CPU time 0.73 seconds
Started Aug 04 04:21:51 PM PDT 24
Finished Aug 04 04:21:51 PM PDT 24
Peak memory 196000 kb
Host smart-a291dd58-6355-435c-ad3d-5800cd24e1fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006889847 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4006889847
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1891473837
Short name T714
Test name
Test status
Simulation time 19400176 ps
CPU time 0.95 seconds
Started Aug 04 04:25:39 PM PDT 24
Finished Aug 04 04:25:40 PM PDT 24
Peak memory 197404 kb
Host smart-593d2ede-bffe-49ca-9f51-29f19bbcaaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891473837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1891473837
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.328406105
Short name T40
Test name
Test status
Simulation time 370259808 ps
CPU time 1.63 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 198576 kb
Host smart-e124ef05-2403-4434-838f-6538884a4b8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328406105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.328406105
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.246592276
Short name T722
Test name
Test status
Simulation time 94520458 ps
CPU time 1.24 seconds
Started Aug 04 04:24:13 PM PDT 24
Finished Aug 04 04:24:14 PM PDT 24
Peak memory 198588 kb
Host smart-4753505f-ca8b-4212-913b-ee20136fb651
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246592276 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.246592276
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3628015123
Short name T829
Test name
Test status
Simulation time 12335836 ps
CPU time 0.59 seconds
Started Aug 04 04:21:53 PM PDT 24
Finished Aug 04 04:21:54 PM PDT 24
Peak memory 194976 kb
Host smart-fec00327-910c-4f3f-9e5d-df3ba519da6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628015123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3628015123
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3678849267
Short name T742
Test name
Test status
Simulation time 12248299 ps
CPU time 0.59 seconds
Started Aug 04 04:23:58 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 194396 kb
Host smart-86d74a7e-2c33-4c5c-8ace-dae68acb7e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678849267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3678849267
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.813252636
Short name T739
Test name
Test status
Simulation time 24577893 ps
CPU time 1.24 seconds
Started Aug 04 04:23:57 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 197636 kb
Host smart-cc62df7e-3b9d-439e-9c76-072213c821c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813252636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.813252636
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.146316877
Short name T43
Test name
Test status
Simulation time 49827853 ps
CPU time 0.81 seconds
Started Aug 04 04:25:37 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 197316 kb
Host smart-f6050b28-db1e-4760-8359-9d38b1e9020f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146316877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.146316877
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1269426829
Short name T835
Test name
Test status
Simulation time 109086619 ps
CPU time 0.72 seconds
Started Aug 04 04:21:55 PM PDT 24
Finished Aug 04 04:21:56 PM PDT 24
Peak memory 198488 kb
Host smart-06a533e9-79e0-4f52-8352-ebe667981c41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269426829 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1269426829
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3201529452
Short name T772
Test name
Test status
Simulation time 22712077 ps
CPU time 0.59 seconds
Started Aug 04 04:25:37 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 195400 kb
Host smart-1a596cb2-bfc4-4ef2-8b62-60535d8c1bbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201529452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3201529452
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.642049309
Short name T727
Test name
Test status
Simulation time 71661892 ps
CPU time 0.58 seconds
Started Aug 04 04:21:56 PM PDT 24
Finished Aug 04 04:21:57 PM PDT 24
Peak memory 194324 kb
Host smart-cd03fa40-1fbe-482a-a8b9-a61b1f81ff89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642049309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.642049309
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4063875580
Short name T114
Test name
Test status
Simulation time 44425315 ps
CPU time 0.89 seconds
Started Aug 04 04:24:06 PM PDT 24
Finished Aug 04 04:24:07 PM PDT 24
Peak memory 196756 kb
Host smart-8c8b6517-fe88-4ca7-842c-0abf5d6c64bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063875580 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4063875580
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1747839613
Short name T766
Test name
Test status
Simulation time 120678922 ps
CPU time 2.29 seconds
Started Aug 04 04:25:32 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 197556 kb
Host smart-b8e81964-8ed1-4b72-bb9f-b13090cbaba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747839613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1747839613
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1938653590
Short name T757
Test name
Test status
Simulation time 210459969 ps
CPU time 1.31 seconds
Started Aug 04 04:26:21 PM PDT 24
Finished Aug 04 04:26:22 PM PDT 24
Peak memory 198524 kb
Host smart-46e9cde1-d8dc-4b5a-976f-9761fc935307
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938653590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1938653590
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2699717347
Short name T730
Test name
Test status
Simulation time 21848606 ps
CPU time 0.81 seconds
Started Aug 04 04:26:22 PM PDT 24
Finished Aug 04 04:26:22 PM PDT 24
Peak memory 198352 kb
Host smart-ef2b099c-d345-4fd4-b67e-3ca1f22beb60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699717347 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2699717347
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2323162985
Short name T79
Test name
Test status
Simulation time 20876336 ps
CPU time 0.56 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 193492 kb
Host smart-c0ac01a1-adfe-4aa1-9e82-d0ee33d8ea6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323162985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2323162985
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1864061327
Short name T804
Test name
Test status
Simulation time 15593117 ps
CPU time 0.71 seconds
Started Aug 04 04:22:02 PM PDT 24
Finished Aug 04 04:22:03 PM PDT 24
Peak memory 195408 kb
Host smart-403639df-10db-4f36-814d-c7f88719bd70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864061327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1864061327
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3329836014
Short name T821
Test name
Test status
Simulation time 40231481 ps
CPU time 0.79 seconds
Started Aug 04 04:23:22 PM PDT 24
Finished Aug 04 04:23:23 PM PDT 24
Peak memory 196608 kb
Host smart-454a8b77-6891-4354-a07e-686a1ba7745e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329836014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3329836014
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2997816143
Short name T726
Test name
Test status
Simulation time 298973259 ps
CPU time 1.51 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 198600 kb
Host smart-66b36e9c-a45f-4244-8d1f-2d686a70f4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997816143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2997816143
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.557533014
Short name T29
Test name
Test status
Simulation time 148372302 ps
CPU time 1.12 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 198016 kb
Host smart-1a043bf1-a49d-4041-87db-2174ef941a51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557533014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.557533014
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3328192347
Short name T791
Test name
Test status
Simulation time 34264773 ps
CPU time 0.87 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 198128 kb
Host smart-8af26753-064d-411c-a2fb-1c41d8251a37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328192347 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3328192347
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2783453424
Short name T84
Test name
Test status
Simulation time 45639295 ps
CPU time 0.72 seconds
Started Aug 04 04:22:05 PM PDT 24
Finished Aug 04 04:22:05 PM PDT 24
Peak memory 196060 kb
Host smart-f424c9f9-6223-45c0-a6b2-93fab99573ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783453424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2783453424
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2704267868
Short name T814
Test name
Test status
Simulation time 14746227 ps
CPU time 0.62 seconds
Started Aug 04 04:22:00 PM PDT 24
Finished Aug 04 04:22:01 PM PDT 24
Peak memory 194988 kb
Host smart-14234d98-8494-48cf-adc6-0ad896b0fbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704267868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2704267868
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2166914965
Short name T767
Test name
Test status
Simulation time 57154606 ps
CPU time 0.87 seconds
Started Aug 04 04:23:54 PM PDT 24
Finished Aug 04 04:23:55 PM PDT 24
Peak memory 196052 kb
Host smart-e6b44717-e433-4e12-bda0-528579d9fb54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166914965 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2166914965
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1252044321
Short name T800
Test name
Test status
Simulation time 184494221 ps
CPU time 1.25 seconds
Started Aug 04 04:23:52 PM PDT 24
Finished Aug 04 04:23:54 PM PDT 24
Peak memory 197424 kb
Host smart-1a58c9c4-fe46-4ca8-8446-db954142246e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252044321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1252044321
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.924892050
Short name T759
Test name
Test status
Simulation time 146331195 ps
CPU time 1.02 seconds
Started Aug 04 04:22:01 PM PDT 24
Finished Aug 04 04:22:02 PM PDT 24
Peak memory 198424 kb
Host smart-c963302e-f6dd-43b0-a187-23724e8a2e20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924892050 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.924892050
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2169939282
Short name T106
Test name
Test status
Simulation time 14953303 ps
CPU time 0.67 seconds
Started Aug 04 04:24:08 PM PDT 24
Finished Aug 04 04:24:08 PM PDT 24
Peak memory 196008 kb
Host smart-9607c17d-078c-4505-8a2a-6d1bec046075
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169939282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2169939282
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.771588761
Short name T756
Test name
Test status
Simulation time 21437653 ps
CPU time 0.63 seconds
Started Aug 04 04:22:48 PM PDT 24
Finished Aug 04 04:22:48 PM PDT 24
Peak memory 194336 kb
Host smart-7ad0945b-46a0-4304-afb0-6efffbeb5dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771588761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.771588761
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1161084297
Short name T796
Test name
Test status
Simulation time 132499106 ps
CPU time 0.87 seconds
Started Aug 04 04:24:08 PM PDT 24
Finished Aug 04 04:24:09 PM PDT 24
Peak memory 196964 kb
Host smart-3ac0f6b0-6e9f-411f-b1bc-3fcd19d35ef5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161084297 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1161084297
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2982576010
Short name T807
Test name
Test status
Simulation time 73473539 ps
CPU time 1.48 seconds
Started Aug 04 04:25:57 PM PDT 24
Finished Aug 04 04:25:59 PM PDT 24
Peak memory 198496 kb
Host smart-406f9e82-0051-4306-bc36-21acadf8a803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982576010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2982576010
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1636982685
Short name T117
Test name
Test status
Simulation time 1066627870 ps
CPU time 1.96 seconds
Started Aug 04 04:22:48 PM PDT 24
Finished Aug 04 04:22:50 PM PDT 24
Peak memory 198612 kb
Host smart-4839e78d-5db0-4e48-9084-d3d54f60bfcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636982685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1636982685
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3990804906
Short name T752
Test name
Test status
Simulation time 66991674 ps
CPU time 0.91 seconds
Started Aug 04 04:24:08 PM PDT 24
Finished Aug 04 04:24:09 PM PDT 24
Peak memory 198452 kb
Host smart-060e0053-4061-492a-b20e-66e025b9c2af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990804906 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3990804906
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4116879004
Short name T788
Test name
Test status
Simulation time 13848544 ps
CPU time 0.64 seconds
Started Aug 04 04:23:19 PM PDT 24
Finished Aug 04 04:23:20 PM PDT 24
Peak memory 194276 kb
Host smart-edfea6b9-2fc7-4250-acc0-7dd2d69d5b00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116879004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4116879004
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2935617981
Short name T762
Test name
Test status
Simulation time 36345699 ps
CPU time 0.58 seconds
Started Aug 04 04:24:08 PM PDT 24
Finished Aug 04 04:24:08 PM PDT 24
Peak memory 194312 kb
Host smart-6e6d41db-185f-4094-af4a-23d3497a24c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935617981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2935617981
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.813224281
Short name T85
Test name
Test status
Simulation time 52762579 ps
CPU time 0.73 seconds
Started Aug 04 04:22:11 PM PDT 24
Finished Aug 04 04:22:12 PM PDT 24
Peak memory 196296 kb
Host smart-9c229054-ab82-48a7-a3bd-51dccc63e044
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813224281 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.813224281
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1547770692
Short name T733
Test name
Test status
Simulation time 320624359 ps
CPU time 1.51 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 198608 kb
Host smart-8058ee81-09ae-45b8-8d9e-928c40df8063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547770692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1547770692
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.687060718
Short name T790
Test name
Test status
Simulation time 212931499 ps
CPU time 1.3 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 198564 kb
Host smart-26088735-af5f-44f3-be5a-8f60307fc2e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687060718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.687060718
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.478873378
Short name T794
Test name
Test status
Simulation time 45185008 ps
CPU time 0.75 seconds
Started Aug 04 04:22:10 PM PDT 24
Finished Aug 04 04:22:11 PM PDT 24
Peak memory 198444 kb
Host smart-a43f789a-1dd7-4890-bb59-2f8e8e04aa5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478873378 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.478873378
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3906295082
Short name T809
Test name
Test status
Simulation time 19534563 ps
CPU time 0.63 seconds
Started Aug 04 04:22:11 PM PDT 24
Finished Aug 04 04:22:12 PM PDT 24
Peak memory 195012 kb
Host smart-c6fd8db9-5248-4695-aa95-56e9c029ab8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906295082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3906295082
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3600602035
Short name T830
Test name
Test status
Simulation time 13878942 ps
CPU time 0.6 seconds
Started Aug 04 04:22:50 PM PDT 24
Finished Aug 04 04:22:51 PM PDT 24
Peak memory 194364 kb
Host smart-56ada9f2-2c91-4b69-9a1b-bc323b26b4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600602035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3600602035
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.323774291
Short name T83
Test name
Test status
Simulation time 62575471 ps
CPU time 0.77 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 196840 kb
Host smart-465bc178-9f76-45d3-9a7d-b335132faa2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323774291 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.323774291
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3125304624
Short name T779
Test name
Test status
Simulation time 47221732 ps
CPU time 2.48 seconds
Started Aug 04 04:22:54 PM PDT 24
Finished Aug 04 04:22:56 PM PDT 24
Peak memory 198680 kb
Host smart-4c3eee36-d30b-4e41-b38d-87172ede5d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125304624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3125304624
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.527084589
Short name T118
Test name
Test status
Simulation time 231231823 ps
CPU time 1.09 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 198596 kb
Host smart-e5b05cb1-292b-4264-b333-01c3863e24fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527084589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.527084589
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.254485747
Short name T753
Test name
Test status
Simulation time 41242876 ps
CPU time 1.84 seconds
Started Aug 04 04:22:16 PM PDT 24
Finished Aug 04 04:22:18 PM PDT 24
Peak memory 198652 kb
Host smart-3d43a263-f963-4291-a4ac-b7443032f872
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254485747 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.254485747
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2171309024
Short name T87
Test name
Test status
Simulation time 56963289 ps
CPU time 0.64 seconds
Started Aug 04 04:22:21 PM PDT 24
Finished Aug 04 04:22:21 PM PDT 24
Peak memory 195260 kb
Host smart-548aa10e-5137-4b1a-8010-1a2b47c0ba5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171309024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2171309024
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.458365203
Short name T797
Test name
Test status
Simulation time 19786384 ps
CPU time 0.64 seconds
Started Aug 04 04:23:18 PM PDT 24
Finished Aug 04 04:23:19 PM PDT 24
Peak memory 195064 kb
Host smart-e00968f4-5004-4d91-8513-1666ec7c428c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458365203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.458365203
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4137116784
Short name T112
Test name
Test status
Simulation time 13557049 ps
CPU time 0.71 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:38 PM PDT 24
Peak memory 196340 kb
Host smart-7a777797-cb6e-4257-91cf-77194a89e2f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137116784 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4137116784
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1062321208
Short name T747
Test name
Test status
Simulation time 253388562 ps
CPU time 1.52 seconds
Started Aug 04 04:22:22 PM PDT 24
Finished Aug 04 04:22:23 PM PDT 24
Peak memory 199064 kb
Host smart-2a6b002d-7f2f-4c8b-ac1d-f46fb5cd3d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062321208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1062321208
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3668309084
Short name T738
Test name
Test status
Simulation time 71864149 ps
CPU time 1.11 seconds
Started Aug 04 04:25:37 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 197116 kb
Host smart-a86d697a-bb62-4515-8b30-40bf7a6cfb98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668309084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3668309084
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2917986911
Short name T721
Test name
Test status
Simulation time 69446190 ps
CPU time 0.91 seconds
Started Aug 04 04:22:23 PM PDT 24
Finished Aug 04 04:22:24 PM PDT 24
Peak memory 198488 kb
Host smart-7b0d9d7e-b69e-4650-aaf6-0bc917afd93d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917986911 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2917986911
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3106663166
Short name T104
Test name
Test status
Simulation time 13328871 ps
CPU time 0.65 seconds
Started Aug 04 04:25:30 PM PDT 24
Finished Aug 04 04:25:31 PM PDT 24
Peak memory 193596 kb
Host smart-1fe30963-9e0d-410c-a0a9-085dcf629371
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106663166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3106663166
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2038038718
Short name T758
Test name
Test status
Simulation time 33258887 ps
CPU time 0.61 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 194952 kb
Host smart-1f8ade98-669a-4302-b1a3-d7cf55b75c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038038718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2038038718
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2354469478
Short name T81
Test name
Test status
Simulation time 38001557 ps
CPU time 0.7 seconds
Started Aug 04 04:22:21 PM PDT 24
Finished Aug 04 04:22:21 PM PDT 24
Peak memory 195316 kb
Host smart-c00841c8-5169-404d-b712-ccaf64514713
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354469478 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2354469478
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.528197776
Short name T825
Test name
Test status
Simulation time 47998255 ps
CPU time 1.16 seconds
Started Aug 04 04:22:22 PM PDT 24
Finished Aug 04 04:22:23 PM PDT 24
Peak memory 198416 kb
Host smart-7645e02c-710c-4ab4-96bd-158a73a301d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528197776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.528197776
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1440744810
Short name T764
Test name
Test status
Simulation time 171834726 ps
CPU time 1.08 seconds
Started Aug 04 04:25:39 PM PDT 24
Finished Aug 04 04:25:40 PM PDT 24
Peak memory 198012 kb
Host smart-50d88390-d201-4ec2-a3cc-3c3cb6f175a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440744810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1440744810
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1348533852
Short name T101
Test name
Test status
Simulation time 21185734 ps
CPU time 0.63 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 194844 kb
Host smart-85aaa782-c4d1-49b0-951d-f675991f038c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348533852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1348533852
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2415146212
Short name T107
Test name
Test status
Simulation time 595548075 ps
CPU time 2.82 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 196388 kb
Host smart-e970d267-e1d4-471a-8928-3654e60e2f76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415146212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2415146212
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3788549504
Short name T782
Test name
Test status
Simulation time 22862296 ps
CPU time 0.59 seconds
Started Aug 04 04:26:02 PM PDT 24
Finished Aug 04 04:26:02 PM PDT 24
Peak memory 194952 kb
Host smart-b99008a6-6e9c-42ab-92b8-eace614c5b51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788549504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3788549504
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.600362602
Short name T732
Test name
Test status
Simulation time 89485584 ps
CPU time 1.01 seconds
Started Aug 04 04:22:53 PM PDT 24
Finished Aug 04 04:22:54 PM PDT 24
Peak memory 198528 kb
Host smart-f97dda4e-6540-435c-b928-c1671cbc6a35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600362602 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.600362602
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3280694413
Short name T785
Test name
Test status
Simulation time 12620553 ps
CPU time 0.57 seconds
Started Aug 04 04:21:15 PM PDT 24
Finished Aug 04 04:21:16 PM PDT 24
Peak memory 193404 kb
Host smart-3f5afccb-de0f-463d-9530-f346bdc2739b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280694413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3280694413
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.69866744
Short name T713
Test name
Test status
Simulation time 21747433 ps
CPU time 0.61 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 193528 kb
Host smart-627e2795-8fda-45b6-b172-bee28ef4f35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69866744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.69866744
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1277382718
Short name T792
Test name
Test status
Simulation time 136355628 ps
CPU time 0.81 seconds
Started Aug 04 04:24:09 PM PDT 24
Finished Aug 04 04:24:10 PM PDT 24
Peak memory 196852 kb
Host smart-e966c428-661f-48f2-bbac-f8f69b7c2c50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277382718 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1277382718
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.147829111
Short name T784
Test name
Test status
Simulation time 192959377 ps
CPU time 1.9 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 198588 kb
Host smart-7d0347c6-1210-4113-8a0a-5dec9f32512a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147829111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.147829111
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2031953559
Short name T41
Test name
Test status
Simulation time 272949807 ps
CPU time 1.11 seconds
Started Aug 04 04:22:27 PM PDT 24
Finished Aug 04 04:22:28 PM PDT 24
Peak memory 198576 kb
Host smart-14602c97-e129-4ed6-8030-466c6080347f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031953559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2031953559
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.383671132
Short name T724
Test name
Test status
Simulation time 46825985 ps
CPU time 0.58 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 193712 kb
Host smart-d35a5447-8c4f-46e4-a822-8e63eb433907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383671132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.383671132
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1292551575
Short name T723
Test name
Test status
Simulation time 14459454 ps
CPU time 0.58 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 193752 kb
Host smart-eb8f147b-a464-4c1c-87e5-8ee7e988f10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292551575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1292551575
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2133837027
Short name T743
Test name
Test status
Simulation time 18526790 ps
CPU time 0.6 seconds
Started Aug 04 04:25:39 PM PDT 24
Finished Aug 04 04:25:40 PM PDT 24
Peak memory 193180 kb
Host smart-21757a6e-17fd-4f6b-b43d-6f9c60fb8279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133837027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2133837027
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4013051624
Short name T820
Test name
Test status
Simulation time 31620541 ps
CPU time 0.63 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 195028 kb
Host smart-f0eba7a0-343b-46e3-a003-eeebeb0d6b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013051624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4013051624
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2359333871
Short name T831
Test name
Test status
Simulation time 47020137 ps
CPU time 0.6 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 194328 kb
Host smart-adbf641d-7307-4012-9225-d71f413a343c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359333871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2359333871
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1358516264
Short name T720
Test name
Test status
Simulation time 147558867 ps
CPU time 0.62 seconds
Started Aug 04 04:24:18 PM PDT 24
Finished Aug 04 04:24:19 PM PDT 24
Peak memory 194172 kb
Host smart-1d4e942a-7ee0-4aef-85bd-00a350c62418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358516264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1358516264
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2186847848
Short name T816
Test name
Test status
Simulation time 15843662 ps
CPU time 0.6 seconds
Started Aug 04 04:22:23 PM PDT 24
Finished Aug 04 04:22:24 PM PDT 24
Peak memory 194304 kb
Host smart-7c4ad121-2856-4f39-bb09-14a02b40cf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186847848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2186847848
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.784520646
Short name T773
Test name
Test status
Simulation time 11920906 ps
CPU time 0.62 seconds
Started Aug 04 04:22:25 PM PDT 24
Finished Aug 04 04:22:26 PM PDT 24
Peak memory 194388 kb
Host smart-efa6c4ff-51c5-4e43-bcb3-489ac7659667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784520646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.784520646
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2367800022
Short name T801
Test name
Test status
Simulation time 16460274 ps
CPU time 0.6 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 194336 kb
Host smart-5a28bc32-8890-4e65-9d58-21b56ec0e803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367800022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2367800022
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2735388128
Short name T822
Test name
Test status
Simulation time 18208770 ps
CPU time 0.58 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 194260 kb
Host smart-7fbbd80e-2a0a-44c8-81ba-54bbce48dce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735388128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2735388128
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2728671371
Short name T116
Test name
Test status
Simulation time 101451721 ps
CPU time 0.76 seconds
Started Aug 04 04:21:20 PM PDT 24
Finished Aug 04 04:21:20 PM PDT 24
Peak memory 196316 kb
Host smart-ef1a0858-6048-497b-8ff9-2f7061f1c42e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728671371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2728671371
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1863032437
Short name T103
Test name
Test status
Simulation time 95632736 ps
CPU time 1.52 seconds
Started Aug 04 04:23:18 PM PDT 24
Finished Aug 04 04:23:20 PM PDT 24
Peak memory 197472 kb
Host smart-fb1a8389-2c27-4313-b5ae-dc33c71da672
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863032437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1863032437
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.901374684
Short name T102
Test name
Test status
Simulation time 16930644 ps
CPU time 0.65 seconds
Started Aug 04 04:25:34 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194412 kb
Host smart-0ecdd9d8-ff2f-40a3-9d86-3929ae9a504f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901374684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.901374684
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.985727491
Short name T731
Test name
Test status
Simulation time 64631092 ps
CPU time 0.93 seconds
Started Aug 04 04:21:24 PM PDT 24
Finished Aug 04 04:21:25 PM PDT 24
Peak memory 198508 kb
Host smart-90ab904e-3bb4-4f29-8ab0-bf85b201499a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985727491 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.985727491
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1092080254
Short name T108
Test name
Test status
Simulation time 14794781 ps
CPU time 0.64 seconds
Started Aug 04 04:23:32 PM PDT 24
Finished Aug 04 04:23:32 PM PDT 24
Peak memory 195304 kb
Host smart-ddfab007-9f0f-4a6b-9780-365e40744bbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092080254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1092080254
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2106357406
Short name T802
Test name
Test status
Simulation time 13572149 ps
CPU time 0.59 seconds
Started Aug 04 04:25:34 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194056 kb
Host smart-ded9fab9-bbe8-4efd-9313-7536412b3bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106357406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2106357406
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1638589207
Short name T781
Test name
Test status
Simulation time 109100259 ps
CPU time 0.74 seconds
Started Aug 04 04:26:02 PM PDT 24
Finished Aug 04 04:26:03 PM PDT 24
Peak memory 197148 kb
Host smart-9ccd62c1-690c-4abd-99fa-2d2bc1d50b95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638589207 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1638589207
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.186112695
Short name T812
Test name
Test status
Simulation time 87122951 ps
CPU time 1.34 seconds
Started Aug 04 04:26:02 PM PDT 24
Finished Aug 04 04:26:03 PM PDT 24
Peak memory 198608 kb
Host smart-c4e12a6a-5c08-4a0b-8d06-940d01445b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186112695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.186112695
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1782836866
Short name T729
Test name
Test status
Simulation time 14210130 ps
CPU time 0.63 seconds
Started Aug 04 04:23:31 PM PDT 24
Finished Aug 04 04:23:32 PM PDT 24
Peak memory 194984 kb
Host smart-a842323b-5daf-4324-a526-7b11d889ccee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782836866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1782836866
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1791307692
Short name T833
Test name
Test status
Simulation time 17071359 ps
CPU time 0.57 seconds
Started Aug 04 04:26:30 PM PDT 24
Finished Aug 04 04:26:31 PM PDT 24
Peak memory 194260 kb
Host smart-0402c6cd-55b0-4899-8db6-29b9e50e9766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791307692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1791307692
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2372444049
Short name T778
Test name
Test status
Simulation time 22894001 ps
CPU time 0.64 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 193168 kb
Host smart-2bbb1ac0-a8e2-4306-91f1-c4651c9d8b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372444049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2372444049
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3280285070
Short name T826
Test name
Test status
Simulation time 40860136 ps
CPU time 0.58 seconds
Started Aug 04 04:22:32 PM PDT 24
Finished Aug 04 04:22:32 PM PDT 24
Peak memory 194304 kb
Host smart-da53a115-e29b-4c98-baec-45d6ca3cf49d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280285070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3280285070
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.982622889
Short name T712
Test name
Test status
Simulation time 28310312 ps
CPU time 0.58 seconds
Started Aug 04 04:26:26 PM PDT 24
Finished Aug 04 04:26:27 PM PDT 24
Peak memory 194904 kb
Host smart-9a95488f-55e7-488a-834c-3489e4662371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982622889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.982622889
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1949203782
Short name T746
Test name
Test status
Simulation time 50270403 ps
CPU time 0.61 seconds
Started Aug 04 04:26:19 PM PDT 24
Finished Aug 04 04:26:20 PM PDT 24
Peak memory 192696 kb
Host smart-a08ee8de-0dcc-466c-ac38-a45c1721ac64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949203782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1949203782
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.124431730
Short name T783
Test name
Test status
Simulation time 64179818 ps
CPU time 0.58 seconds
Started Aug 04 04:26:34 PM PDT 24
Finished Aug 04 04:26:35 PM PDT 24
Peak memory 194252 kb
Host smart-07f8f1c8-4b11-4c58-a2bf-e1911e2b7960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124431730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.124431730
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3848119125
Short name T810
Test name
Test status
Simulation time 16731087 ps
CPU time 0.61 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:25:59 PM PDT 24
Peak memory 194320 kb
Host smart-95b76ed3-2550-452c-a9f5-4a88562f38e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848119125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3848119125
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3960859537
Short name T740
Test name
Test status
Simulation time 17270827 ps
CPU time 0.64 seconds
Started Aug 04 04:26:19 PM PDT 24
Finished Aug 04 04:26:20 PM PDT 24
Peak memory 192788 kb
Host smart-a8935f1c-4e47-44ca-9ceb-cff1e8d4c243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960859537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3960859537
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3059148478
Short name T798
Test name
Test status
Simulation time 17059059 ps
CPU time 0.61 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 194800 kb
Host smart-ac1088a8-0934-431f-8493-274ddcf7f82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059148478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3059148478
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3827296376
Short name T818
Test name
Test status
Simulation time 83279980 ps
CPU time 0.78 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 196428 kb
Host smart-558050e4-0444-44fd-addc-43f5cb752ff3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827296376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3827296376
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2096273603
Short name T719
Test name
Test status
Simulation time 486966892 ps
CPU time 1.37 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 198480 kb
Host smart-82f2c0cc-bc24-4551-9da5-218312ea6742
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096273603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2096273603
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1435110423
Short name T795
Test name
Test status
Simulation time 17910186 ps
CPU time 0.65 seconds
Started Aug 04 04:25:38 PM PDT 24
Finished Aug 04 04:25:39 PM PDT 24
Peak memory 194324 kb
Host smart-85e3b8ee-27b8-4758-8995-1c047c8d5ddf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435110423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1435110423
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3283188957
Short name T761
Test name
Test status
Simulation time 27815336 ps
CPU time 0.77 seconds
Started Aug 04 04:25:38 PM PDT 24
Finished Aug 04 04:25:39 PM PDT 24
Peak memory 197256 kb
Host smart-b1d49b68-4f35-4f66-8d7b-0ff2d80dd1d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283188957 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3283188957
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.244430295
Short name T99
Test name
Test status
Simulation time 11545517 ps
CPU time 0.66 seconds
Started Aug 04 04:24:22 PM PDT 24
Finished Aug 04 04:24:22 PM PDT 24
Peak memory 195072 kb
Host smart-c3bc5ad8-4e12-4f08-8e74-610729683ab2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244430295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.244430295
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1072956301
Short name T725
Test name
Test status
Simulation time 20993469 ps
CPU time 0.61 seconds
Started Aug 04 04:22:56 PM PDT 24
Finished Aug 04 04:22:56 PM PDT 24
Peak memory 194392 kb
Host smart-b5c2299f-a039-4a54-891f-6123185864c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072956301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1072956301
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3463314632
Short name T805
Test name
Test status
Simulation time 68259139 ps
CPU time 0.83 seconds
Started Aug 04 04:22:34 PM PDT 24
Finished Aug 04 04:22:35 PM PDT 24
Peak memory 196880 kb
Host smart-6627454a-a882-48e2-a5f5-36c2f92c99ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463314632 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3463314632
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.684719227
Short name T716
Test name
Test status
Simulation time 79786976 ps
CPU time 1.59 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 198592 kb
Host smart-29f97196-ae6a-4aeb-8190-078f8c98b55a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684719227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.684719227
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2746927897
Short name T39
Test name
Test status
Simulation time 248096540 ps
CPU time 1.49 seconds
Started Aug 04 04:21:30 PM PDT 24
Finished Aug 04 04:21:32 PM PDT 24
Peak memory 198524 kb
Host smart-a0fbdfc3-c729-491f-bc8d-afed98c7ffbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746927897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2746927897
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1641505726
Short name T748
Test name
Test status
Simulation time 37893538 ps
CPU time 0.62 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 193844 kb
Host smart-02e40127-1b0f-471c-928c-5b4d12a4dafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641505726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1641505726
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2826566221
Short name T750
Test name
Test status
Simulation time 19194680 ps
CPU time 0.63 seconds
Started Aug 04 04:23:21 PM PDT 24
Finished Aug 04 04:23:22 PM PDT 24
Peak memory 194740 kb
Host smart-19ae372b-b532-43bd-baec-f767eba6d105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826566221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2826566221
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3018971657
Short name T751
Test name
Test status
Simulation time 21541120 ps
CPU time 0.59 seconds
Started Aug 04 04:22:33 PM PDT 24
Finished Aug 04 04:22:34 PM PDT 24
Peak memory 195312 kb
Host smart-a5b37a82-a0db-40a5-90d1-bfd50144e7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018971657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3018971657
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1683664494
Short name T780
Test name
Test status
Simulation time 50107753 ps
CPU time 0.58 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:48 PM PDT 24
Peak memory 194256 kb
Host smart-300ff352-875e-45e1-9459-eb05cce054d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683664494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1683664494
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4224267475
Short name T827
Test name
Test status
Simulation time 14942599 ps
CPU time 0.62 seconds
Started Aug 04 04:22:44 PM PDT 24
Finished Aug 04 04:22:44 PM PDT 24
Peak memory 194336 kb
Host smart-f8e43918-9246-4adf-97c3-c549d56f5df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224267475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4224267475
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3473871326
Short name T771
Test name
Test status
Simulation time 17635209 ps
CPU time 0.63 seconds
Started Aug 04 04:22:36 PM PDT 24
Finished Aug 04 04:22:37 PM PDT 24
Peak memory 193916 kb
Host smart-caee1909-5230-4998-b5f1-beb6bfefcd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473871326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3473871326
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3622865671
Short name T735
Test name
Test status
Simulation time 11415541 ps
CPU time 0.55 seconds
Started Aug 04 04:25:34 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194892 kb
Host smart-14641d96-5c31-4664-9790-4a4f8b196bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622865671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3622865671
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1489897643
Short name T755
Test name
Test status
Simulation time 15613768 ps
CPU time 0.63 seconds
Started Aug 04 04:25:46 PM PDT 24
Finished Aug 04 04:25:47 PM PDT 24
Peak memory 194908 kb
Host smart-585d012a-4331-484f-9a55-d669923958dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489897643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1489897643
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2530716217
Short name T736
Test name
Test status
Simulation time 18330891 ps
CPU time 0.66 seconds
Started Aug 04 04:25:19 PM PDT 24
Finished Aug 04 04:25:21 PM PDT 24
Peak memory 193912 kb
Host smart-f49c1093-2a1e-4318-9609-93023120422f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530716217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2530716217
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.449871164
Short name T803
Test name
Test status
Simulation time 39002539 ps
CPU time 0.62 seconds
Started Aug 04 04:22:35 PM PDT 24
Finished Aug 04 04:22:35 PM PDT 24
Peak memory 195016 kb
Host smart-3700f571-e405-41b5-84e7-cff321466cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449871164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.449871164
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2468759762
Short name T819
Test name
Test status
Simulation time 21748953 ps
CPU time 0.94 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 198380 kb
Host smart-59b65693-4370-4642-a36f-969b02bbb2d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468759762 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2468759762
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.39954934
Short name T88
Test name
Test status
Simulation time 21418659 ps
CPU time 0.61 seconds
Started Aug 04 04:23:20 PM PDT 24
Finished Aug 04 04:23:21 PM PDT 24
Peak memory 195308 kb
Host smart-adece283-c589-4297-9bc2-94557db77148
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39954934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_c
sr_rw.39954934
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2135722356
Short name T770
Test name
Test status
Simulation time 22551860 ps
CPU time 0.65 seconds
Started Aug 04 04:23:50 PM PDT 24
Finished Aug 04 04:23:51 PM PDT 24
Peak memory 194376 kb
Host smart-98899ec8-62a8-4972-ac2e-aaa913c1a502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135722356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2135722356
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2972943865
Short name T806
Test name
Test status
Simulation time 92398423 ps
CPU time 0.71 seconds
Started Aug 04 04:21:33 PM PDT 24
Finished Aug 04 04:21:33 PM PDT 24
Peak memory 195504 kb
Host smart-d091509d-8ef5-4a3e-a338-2c07eb7c7103
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972943865 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2972943865
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.869854852
Short name T776
Test name
Test status
Simulation time 59209122 ps
CPU time 0.94 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 198244 kb
Host smart-e2cae131-3c5b-445b-bf45-b0e84aa25135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869854852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.869854852
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2094549195
Short name T42
Test name
Test status
Simulation time 293251711 ps
CPU time 1.2 seconds
Started Aug 04 04:22:04 PM PDT 24
Finished Aug 04 04:22:06 PM PDT 24
Peak memory 198636 kb
Host smart-6af55c93-0c1a-4613-a7c8-18ff9466e83d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094549195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2094549195
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2767629022
Short name T737
Test name
Test status
Simulation time 89669969 ps
CPU time 1.02 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 198560 kb
Host smart-db543ca5-a932-4cf6-8a27-2b57b169fa07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767629022 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2767629022
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3659000890
Short name T789
Test name
Test status
Simulation time 16306462 ps
CPU time 0.72 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 194028 kb
Host smart-6eb27a3b-b111-4026-aca2-56b80634317c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659000890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3659000890
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3844040162
Short name T787
Test name
Test status
Simulation time 13591278 ps
CPU time 0.6 seconds
Started Aug 04 04:24:14 PM PDT 24
Finished Aug 04 04:24:15 PM PDT 24
Peak memory 194252 kb
Host smart-27d16d14-65fa-4233-9834-a40d4c974ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844040162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3844040162
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1719600014
Short name T115
Test name
Test status
Simulation time 94076269 ps
CPU time 0.76 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 194940 kb
Host smart-177280db-f154-444b-a425-dce036a0eaf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719600014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1719600014
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.967016366
Short name T715
Test name
Test status
Simulation time 46835601 ps
CPU time 2.2 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:01 PM PDT 24
Peak memory 197720 kb
Host smart-e4a4cc41-e35e-4461-833b-819a3bafb534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967016366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.967016366
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1703432302
Short name T808
Test name
Test status
Simulation time 101898288 ps
CPU time 1.37 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 196752 kb
Host smart-9bdce8dd-0011-477d-b3dd-453113dd28d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703432302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1703432302
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2636268047
Short name T741
Test name
Test status
Simulation time 70163694 ps
CPU time 0.78 seconds
Started Aug 04 04:25:38 PM PDT 24
Finished Aug 04 04:25:39 PM PDT 24
Peak memory 197560 kb
Host smart-98120fec-48ab-467c-a90c-8a8557baa627
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636268047 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2636268047
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3146124489
Short name T824
Test name
Test status
Simulation time 16897195 ps
CPU time 0.6 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 195512 kb
Host smart-320e4ccc-1be3-470d-b6ec-03bdfc31c8f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146124489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3146124489
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2438122567
Short name T775
Test name
Test status
Simulation time 50173512 ps
CPU time 0.59 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 194312 kb
Host smart-da55939f-d589-419b-8f74-518530d0eb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438122567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2438122567
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2766271983
Short name T111
Test name
Test status
Simulation time 142350891 ps
CPU time 0.85 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 197748 kb
Host smart-0a9526c3-c820-46ec-aae4-53aa1aa1f773
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766271983 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2766271983
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2081306718
Short name T823
Test name
Test status
Simulation time 210102721 ps
CPU time 2.94 seconds
Started Aug 04 04:24:14 PM PDT 24
Finished Aug 04 04:24:17 PM PDT 24
Peak memory 198588 kb
Host smart-9c197557-0a65-46df-b938-3b366daefb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081306718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2081306718
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1521579977
Short name T32
Test name
Test status
Simulation time 200388068 ps
CPU time 0.88 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 198312 kb
Host smart-dd1e4049-3001-4cad-a448-78bbdba78ca9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521579977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1521579977
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2259012753
Short name T815
Test name
Test status
Simulation time 104858010 ps
CPU time 0.89 seconds
Started Aug 04 04:21:44 PM PDT 24
Finished Aug 04 04:21:45 PM PDT 24
Peak memory 198416 kb
Host smart-7178e883-9c99-4767-b0eb-07198b21915b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259012753 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2259012753
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2550077444
Short name T86
Test name
Test status
Simulation time 11849169 ps
CPU time 0.6 seconds
Started Aug 04 04:25:53 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 195016 kb
Host smart-dd820db6-27a4-4a42-865a-8ac511fa0632
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550077444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2550077444
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.104059118
Short name T811
Test name
Test status
Simulation time 52561286 ps
CPU time 0.64 seconds
Started Aug 04 04:21:51 PM PDT 24
Finished Aug 04 04:21:52 PM PDT 24
Peak memory 194780 kb
Host smart-1fdb25cc-9660-4f0f-9ae1-1992ec3886fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104059118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.104059118
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3852763335
Short name T109
Test name
Test status
Simulation time 126288023 ps
CPU time 0.73 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 196604 kb
Host smart-9d733dd7-3a94-491e-be9a-db36d3bd26d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852763335 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3852763335
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.791937317
Short name T763
Test name
Test status
Simulation time 37767259 ps
CPU time 1.81 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 198660 kb
Host smart-865ec2bd-15f8-471a-8061-1359f6096798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791937317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.791937317
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4239987452
Short name T30
Test name
Test status
Simulation time 949167185 ps
CPU time 1.13 seconds
Started Aug 04 04:21:45 PM PDT 24
Finished Aug 04 04:21:46 PM PDT 24
Peak memory 198624 kb
Host smart-f1dd3081-55dc-4288-9a6c-42e61b1f2ba4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239987452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4239987452
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3044133664
Short name T832
Test name
Test status
Simulation time 177987788 ps
CPU time 0.86 seconds
Started Aug 04 04:25:42 PM PDT 24
Finished Aug 04 04:25:43 PM PDT 24
Peak memory 197940 kb
Host smart-2fa6c155-af6a-4c01-afdb-6bc65a025ba3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044133664 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3044133664
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3652825355
Short name T89
Test name
Test status
Simulation time 60790856 ps
CPU time 0.56 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 193820 kb
Host smart-b5ac8bea-f0b7-4f1a-afb6-009c4290e844
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652825355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3652825355
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3663412555
Short name T777
Test name
Test status
Simulation time 27579578 ps
CPU time 0.65 seconds
Started Aug 04 04:25:32 PM PDT 24
Finished Aug 04 04:25:33 PM PDT 24
Peak memory 193220 kb
Host smart-7ab33859-fd2f-42d4-88ac-d28ca7d60538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663412555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3663412555
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.542684230
Short name T110
Test name
Test status
Simulation time 31513210 ps
CPU time 0.79 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 196624 kb
Host smart-35a29fa7-b26b-4839-af86-4b7d1c9f914d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542684230 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.542684230
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3512308265
Short name T728
Test name
Test status
Simulation time 116705926 ps
CPU time 2.12 seconds
Started Aug 04 04:23:20 PM PDT 24
Finished Aug 04 04:23:22 PM PDT 24
Peak memory 199060 kb
Host smart-ee975eb4-89fc-4fd4-82c3-52af1b7d9a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512308265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3512308265
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1946558024
Short name T769
Test name
Test status
Simulation time 155537356 ps
CPU time 1.15 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:25:59 PM PDT 24
Peak memory 198524 kb
Host smart-01efc792-4c5a-43b1-b412-7048d2898e41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946558024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1946558024
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3315154371
Short name T402
Test name
Test status
Simulation time 13914926 ps
CPU time 0.6 seconds
Started Aug 04 04:36:32 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 194628 kb
Host smart-cc51897d-0121-4959-a0b1-8cd1e842560a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315154371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3315154371
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.242767955
Short name T646
Test name
Test status
Simulation time 39906596 ps
CPU time 0.85 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 197432 kb
Host smart-e0209ad9-4232-4f64-8309-ec4fcaceb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242767955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.242767955
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3896239638
Short name T640
Test name
Test status
Simulation time 732484948 ps
CPU time 3.81 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:30 PM PDT 24
Peak memory 196192 kb
Host smart-2dbe7125-d030-47de-9b6f-698108334889
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896239638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3896239638
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.922573671
Short name T349
Test name
Test status
Simulation time 50115805 ps
CPU time 0.76 seconds
Started Aug 04 04:36:30 PM PDT 24
Finished Aug 04 04:36:31 PM PDT 24
Peak memory 196408 kb
Host smart-cffba477-7b7b-4ffb-ac4e-9a1a782c823f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922573671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.922573671
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3598559968
Short name T693
Test name
Test status
Simulation time 260767055 ps
CPU time 1.1 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 196384 kb
Host smart-4ccfcce2-b1e3-4bfa-a0db-b44cdd34cf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598559968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3598559968
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.948004134
Short name T301
Test name
Test status
Simulation time 73715441 ps
CPU time 2.87 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 198652 kb
Host smart-b0a8a5e1-de3f-464c-9f2c-d3f052709345
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948004134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.948004134
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.362515846
Short name T606
Test name
Test status
Simulation time 483846367 ps
CPU time 2.52 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 198568 kb
Host smart-a3e1e034-2aba-42b5-a1a3-1a6801495263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362515846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.362515846
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.146444794
Short name T149
Test name
Test status
Simulation time 108043803 ps
CPU time 0.96 seconds
Started Aug 04 04:36:21 PM PDT 24
Finished Aug 04 04:36:22 PM PDT 24
Peak memory 196552 kb
Host smart-7595c3eb-b8fa-42e1-a1c8-063c989c4a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146444794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.146444794
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3976363863
Short name T555
Test name
Test status
Simulation time 18082703 ps
CPU time 0.73 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:25 PM PDT 24
Peak memory 195924 kb
Host smart-3d290a4a-7151-41a8-bad6-91ccbd498b87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976363863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3976363863
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1599418932
Short name T523
Test name
Test status
Simulation time 23014868 ps
CPU time 1.06 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 196928 kb
Host smart-32f360bc-855b-4beb-a186-472c37d49033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599418932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1599418932
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3602707026
Short name T35
Test name
Test status
Simulation time 86295687 ps
CPU time 0.78 seconds
Started Aug 04 04:36:21 PM PDT 24
Finished Aug 04 04:36:22 PM PDT 24
Peak memory 215340 kb
Host smart-d6413a46-17d2-40e8-bea0-22bc815318ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602707026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3602707026
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1379627702
Short name T549
Test name
Test status
Simulation time 352532764 ps
CPU time 1.4 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 197304 kb
Host smart-f675d4a2-c025-4dc5-a2db-12477e7946b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379627702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1379627702
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4211382257
Short name T143
Test name
Test status
Simulation time 62158310 ps
CPU time 1.17 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 196292 kb
Host smart-695b3435-9c99-4810-bc29-924b9fff37f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211382257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4211382257
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4000145992
Short name T586
Test name
Test status
Simulation time 14641133 ps
CPU time 0.55 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 194608 kb
Host smart-582e6409-2b55-40b7-98b8-c4f42b642dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000145992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4000145992
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.76518281
Short name T542
Test name
Test status
Simulation time 20240565 ps
CPU time 0.66 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 194648 kb
Host smart-abe482fb-71c4-4998-bfb3-86259480c04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76518281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.76518281
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.197365796
Short name T153
Test name
Test status
Simulation time 1815629767 ps
CPU time 26.83 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 197576 kb
Host smart-260b3e38-85e5-41aa-8749-ca1fc8f975a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197365796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.197365796
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3782103186
Short name T209
Test name
Test status
Simulation time 33499576 ps
CPU time 0.72 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 196888 kb
Host smart-d9e52052-f646-4ff7-9301-17ffbaeb0b85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782103186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3782103186
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1998679077
Short name T90
Test name
Test status
Simulation time 361339175 ps
CPU time 1.45 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 197508 kb
Host smart-d36712a2-4a50-4883-8667-b42325d49a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998679077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1998679077
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.731311898
Short name T174
Test name
Test status
Simulation time 180171607 ps
CPU time 1.49 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 197396 kb
Host smart-1580429e-c1e8-4375-acb2-4a9c3b404b46
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731311898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.731311898
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.402743899
Short name T423
Test name
Test status
Simulation time 126188645 ps
CPU time 1.4 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 196244 kb
Host smart-4364a2c4-58b1-4580-9eb8-649a68b9ea98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402743899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.402743899
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1489744297
Short name T220
Test name
Test status
Simulation time 39897469 ps
CPU time 0.83 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 197768 kb
Host smart-e35a0e89-01d8-4fab-ab63-09856234145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489744297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1489744297
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2345607889
Short name T703
Test name
Test status
Simulation time 114960111 ps
CPU time 1.14 seconds
Started Aug 04 04:36:29 PM PDT 24
Finished Aug 04 04:36:31 PM PDT 24
Peak memory 197836 kb
Host smart-46cf0697-19d9-4c78-97c1-e9004553c259
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345607889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2345607889
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.615522557
Short name T515
Test name
Test status
Simulation time 440321712 ps
CPU time 2.18 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 198492 kb
Host smart-50d4d282-9c07-40a7-b5a7-e3e6d2e8885e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615522557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.615522557
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2421469518
Short name T34
Test name
Test status
Simulation time 104894125 ps
CPU time 0.85 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 214312 kb
Host smart-e0bc8dbb-e106-4b83-918c-88d8308bda8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421469518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2421469518
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2834574562
Short name T377
Test name
Test status
Simulation time 197363572 ps
CPU time 1.07 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 196836 kb
Host smart-760dd8d1-4000-4c3e-8791-a31b0c8fd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834574562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2834574562
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1762477122
Short name T124
Test name
Test status
Simulation time 106978595 ps
CPU time 0.87 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 195772 kb
Host smart-7c6df1ab-1da4-4dbc-8401-e40489e48360
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762477122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1762477122
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2545932808
Short name T1
Test name
Test status
Simulation time 6558433859 ps
CPU time 34.2 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 198720 kb
Host smart-d733b5ba-2591-478b-9d42-b344686e6f8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545932808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2545932808
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1871811770
Short name T51
Test name
Test status
Simulation time 98551052959 ps
CPU time 2404.04 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 05:16:32 PM PDT 24
Peak memory 198856 kb
Host smart-c46b7ab4-8f39-4f64-869e-6073e6da9924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1871811770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1871811770
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2326729405
Short name T695
Test name
Test status
Simulation time 11785440 ps
CPU time 0.55 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 195020 kb
Host smart-7a7b42f0-6779-446d-9629-493e355ca821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326729405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2326729405
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.403474649
Short name T647
Test name
Test status
Simulation time 22663940 ps
CPU time 0.69 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 195172 kb
Host smart-f4f272e8-cc94-4b7e-b2b1-d6467d5f3b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403474649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.403474649
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3957311308
Short name T233
Test name
Test status
Simulation time 214925184 ps
CPU time 5.83 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 197132 kb
Host smart-b11d94f1-829d-4bc0-858e-b8e31b7a572d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957311308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3957311308
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3524736352
Short name T416
Test name
Test status
Simulation time 31820648 ps
CPU time 0.69 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 196968 kb
Host smart-1dfbf7b9-cb51-4a7b-b5c0-61cfb9aaf91e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524736352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3524736352
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.80093893
Short name T656
Test name
Test status
Simulation time 52805778 ps
CPU time 0.83 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 197120 kb
Host smart-9947df43-5253-4713-8ce1-2a4acbfaab2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80093893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.80093893
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3182072680
Short name T218
Test name
Test status
Simulation time 72791690 ps
CPU time 1.42 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 196760 kb
Host smart-54a24cb7-27af-4bb8-a326-c097e746905f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182072680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3182072680
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4193957609
Short name T357
Test name
Test status
Simulation time 137008354 ps
CPU time 2.69 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 197108 kb
Host smart-4b11dc4d-0cff-407f-b346-60c4b7fb5488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193957609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4193957609
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1894030334
Short name T588
Test name
Test status
Simulation time 312547945 ps
CPU time 0.77 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 196648 kb
Host smart-9e4bec93-f400-45de-aac4-6166632b7bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894030334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1894030334
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2351291760
Short name T642
Test name
Test status
Simulation time 31791520 ps
CPU time 0.8 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196820 kb
Host smart-bd48279d-eb4b-4df9-809a-2ab131f0b67f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351291760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2351291760
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2254381335
Short name T612
Test name
Test status
Simulation time 98409161 ps
CPU time 1.56 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 198428 kb
Host smart-6ce5f2d9-7423-4a87-9186-1f9c6873b3d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254381335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2254381335
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3903336129
Short name T528
Test name
Test status
Simulation time 59450611 ps
CPU time 1.12 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196396 kb
Host smart-bf216d64-7737-4b7f-9daa-883b8640086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903336129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3903336129
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4191435647
Short name T308
Test name
Test status
Simulation time 162409556 ps
CPU time 1.15 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 196400 kb
Host smart-7432ba18-9704-4761-a608-07009ebccbcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191435647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4191435647
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.18975629
Short name T19
Test name
Test status
Simulation time 21516740853 ps
CPU time 113.26 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:38:33 PM PDT 24
Peak memory 198556 kb
Host smart-bea82fda-c171-4144-9d32-9a7e525e27c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gp
io_stress_all.18975629
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3148210472
Short name T91
Test name
Test status
Simulation time 53026388 ps
CPU time 0.55 seconds
Started Aug 04 04:37:01 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 194376 kb
Host smart-37215bd9-0cb2-4bb6-bb7e-f45f9a3bcf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148210472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3148210472
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3736825
Short name T22
Test name
Test status
Simulation time 111177494 ps
CPU time 0.91 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 196392 kb
Host smart-404acac4-c534-470f-9f1b-2d8652624875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3736825
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.340503606
Short name T177
Test name
Test status
Simulation time 223435588 ps
CPU time 5.78 seconds
Started Aug 04 04:36:50 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 197356 kb
Host smart-5ef45a41-b054-4cc3-99b3-fda0a09d7b14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340503606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.340503606
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.333471064
Short name T294
Test name
Test status
Simulation time 145299992 ps
CPU time 0.76 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196436 kb
Host smart-fe86cf5a-2b81-4ad1-a445-dbabb0676922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333471064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.333471064
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3656851484
Short name T73
Test name
Test status
Simulation time 134969504 ps
CPU time 0.94 seconds
Started Aug 04 04:36:55 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 196200 kb
Host smart-a11b513b-2b02-4731-af18-17c86f76250f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656851484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3656851484
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2927882911
Short name T299
Test name
Test status
Simulation time 184846152 ps
CPU time 1.95 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 196956 kb
Host smart-4dadb7b0-235e-4f61-9945-80b46313691d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927882911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2927882911
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1558696530
Short name T230
Test name
Test status
Simulation time 102160596 ps
CPU time 3.01 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:37:22 PM PDT 24
Peak memory 198504 kb
Host smart-fc3273eb-4f11-4133-a8ad-903f138540cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558696530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1558696530
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1771919614
Short name T539
Test name
Test status
Simulation time 75363682 ps
CPU time 0.91 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 197124 kb
Host smart-2a171cdf-3c82-4ced-88ed-10650e937053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771919614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1771919614
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3255465260
Short name T330
Test name
Test status
Simulation time 350851761 ps
CPU time 1.11 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 196380 kb
Host smart-c0d7cb24-ac39-474c-a2f0-f2a7a53dc57f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255465260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3255465260
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.4289245071
Short name T362
Test name
Test status
Simulation time 855197999 ps
CPU time 4.93 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:53 PM PDT 24
Peak memory 198428 kb
Host smart-b1e9b23c-b224-4c74-b335-4b6d45e76d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289245071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.4289245071
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3249739478
Short name T476
Test name
Test status
Simulation time 72034356 ps
CPU time 1.03 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:03 PM PDT 24
Peak memory 196268 kb
Host smart-d40c6bbc-c2ae-4607-96fd-d0b5da339095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249739478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3249739478
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2768741012
Short name T94
Test name
Test status
Simulation time 676624050 ps
CPU time 1.27 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 197324 kb
Host smart-ff8f8246-5311-4273-bd8c-54cf226c5ed2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768741012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2768741012
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2481378506
Short name T72
Test name
Test status
Simulation time 104767391163 ps
CPU time 181.63 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:39:43 PM PDT 24
Peak memory 192512 kb
Host smart-76975431-066a-4349-9b0f-ab3af675c339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481378506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2481378506
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1206766091
Short name T456
Test name
Test status
Simulation time 11090046 ps
CPU time 0.58 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 194496 kb
Host smart-0fa7407a-a9d9-415c-bc3b-584c295ea3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206766091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1206766091
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1285218780
Short name T533
Test name
Test status
Simulation time 90304348 ps
CPU time 0.8 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 197728 kb
Host smart-de8647fe-78bf-4f1c-bb4b-c1904934dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285218780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1285218780
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2655087123
Short name T125
Test name
Test status
Simulation time 122307305 ps
CPU time 6.1 seconds
Started Aug 04 04:36:56 PM PDT 24
Finished Aug 04 04:37:02 PM PDT 24
Peak memory 198432 kb
Host smart-80a00708-e774-48b4-b05d-0b80ef56e662
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655087123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2655087123
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3394291436
Short name T470
Test name
Test status
Simulation time 37809713 ps
CPU time 0.61 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:09 PM PDT 24
Peak memory 194784 kb
Host smart-58c51ffb-06b6-4fba-9ba2-ce664a2cae5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394291436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3394291436
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2429030059
Short name T370
Test name
Test status
Simulation time 268082594 ps
CPU time 1.19 seconds
Started Aug 04 04:36:58 PM PDT 24
Finished Aug 04 04:36:59 PM PDT 24
Peak memory 197576 kb
Host smart-eca4c7fa-5b0b-4282-a6ed-68eb8f311b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429030059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2429030059
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2131406290
Short name T236
Test name
Test status
Simulation time 59609730 ps
CPU time 1.28 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 198396 kb
Host smart-124cffd5-c1e7-497c-80fd-c77e11096746
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131406290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2131406290
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1894986530
Short name T191
Test name
Test status
Simulation time 55435337 ps
CPU time 1.3 seconds
Started Aug 04 04:36:58 PM PDT 24
Finished Aug 04 04:36:59 PM PDT 24
Peak memory 196304 kb
Host smart-452fd9b5-d5f6-48ca-a755-799295b7756c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894986530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1894986530
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3540555819
Short name T184
Test name
Test status
Simulation time 188265540 ps
CPU time 0.73 seconds
Started Aug 04 04:36:56 PM PDT 24
Finished Aug 04 04:36:57 PM PDT 24
Peak memory 195920 kb
Host smart-59394109-f7b4-4774-956d-97ef4093a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540555819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3540555819
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.532898372
Short name T350
Test name
Test status
Simulation time 64146779 ps
CPU time 0.8 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 196988 kb
Host smart-3d88dd30-45f1-43d7-8164-fdb8a9253c5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532898372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.532898372
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3984229684
Short name T616
Test name
Test status
Simulation time 47683260 ps
CPU time 2.13 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 198432 kb
Host smart-2a3b6cd5-f2c8-409b-b45a-3853c290f5ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984229684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3984229684
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2299939389
Short name T471
Test name
Test status
Simulation time 158311486 ps
CPU time 1.07 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 197064 kb
Host smart-6752cfa4-1205-42ad-8757-08df0a59faaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299939389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2299939389
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.656843443
Short name T587
Test name
Test status
Simulation time 34548143 ps
CPU time 0.76 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196364 kb
Host smart-dd2238be-f27e-4a9d-826e-766cc4d2e9db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656843443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.656843443
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2592933181
Short name T511
Test name
Test status
Simulation time 76934736013 ps
CPU time 208.3 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:40:19 PM PDT 24
Peak memory 198652 kb
Host smart-8460ddeb-84f9-483c-9706-d32016447c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592933181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2592933181
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2494688627
Short name T58
Test name
Test status
Simulation time 293752345466 ps
CPU time 1662.6 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 05:04:24 PM PDT 24
Peak memory 198752 kb
Host smart-7d01f830-2324-475c-b65f-e62e428b7aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2494688627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2494688627
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3087063441
Short name T421
Test name
Test status
Simulation time 77817189 ps
CPU time 0.55 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 194404 kb
Host smart-4d6a5e5f-e03a-4c67-a6c7-07434735701a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087063441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3087063441
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1512353477
Short name T62
Test name
Test status
Simulation time 30050893 ps
CPU time 0.72 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 194672 kb
Host smart-2fa3e03b-c40a-4206-a088-f495802e929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512353477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1512353477
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.652297432
Short name T650
Test name
Test status
Simulation time 2934852532 ps
CPU time 14.25 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 198604 kb
Host smart-bc91ad61-d82c-4421-9762-bc0519334f90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652297432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.652297432
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2486927523
Short name T538
Test name
Test status
Simulation time 48318276 ps
CPU time 0.75 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 196968 kb
Host smart-58976a55-d271-4f72-80ff-c11f06ea7700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486927523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2486927523
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1985984113
Short name T454
Test name
Test status
Simulation time 137577498 ps
CPU time 0.86 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 196612 kb
Host smart-128d07f2-fc5f-4e2b-9c45-ed4ec2220c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985984113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1985984113
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.163040044
Short name T121
Test name
Test status
Simulation time 1094053857 ps
CPU time 3.61 seconds
Started Aug 04 04:37:01 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 198604 kb
Host smart-46718b03-3c3f-4705-b402-cb6ca04475f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163040044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.163040044
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.367019607
Short name T680
Test name
Test status
Simulation time 223728000 ps
CPU time 3.23 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 197628 kb
Host smart-8567e3e8-c3af-42ed-8d92-b35d125fb532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367019607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
367019607
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1894669415
Short name T611
Test name
Test status
Simulation time 59704600 ps
CPU time 1.23 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 197464 kb
Host smart-72b74ef5-2c0b-4b34-b714-86699b4f3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894669415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1894669415
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3329674417
Short name T293
Test name
Test status
Simulation time 187961729 ps
CPU time 0.74 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 195856 kb
Host smart-824e298b-ab16-4456-abca-90bb02abe6be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329674417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3329674417
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.24867967
Short name T10
Test name
Test status
Simulation time 904825377 ps
CPU time 2.99 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 198436 kb
Host smart-5e020354-af61-4357-bb60-825704a503e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24867967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand
om_long_reg_writes_reg_reads.24867967
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4238228595
Short name T397
Test name
Test status
Simulation time 165536804 ps
CPU time 1.08 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 197080 kb
Host smart-40030231-42ef-43f9-97d1-6de917eafcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238228595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4238228595
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.912737051
Short name T387
Test name
Test status
Simulation time 101432736 ps
CPU time 0.89 seconds
Started Aug 04 04:36:49 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 195632 kb
Host smart-d3d6db86-b240-4357-bcf9-0180fbb7e7ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912737051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.912737051
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.261809974
Short name T246
Test name
Test status
Simulation time 26880599930 ps
CPU time 156.34 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:39:22 PM PDT 24
Peak memory 198612 kb
Host smart-1b04f3b6-4295-4ca2-9b39-fad2aef8f680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261809974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.261809974
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.327096311
Short name T318
Test name
Test status
Simulation time 46225482 ps
CPU time 0.57 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 195376 kb
Host smart-be15cf6f-6409-4bb6-b2c4-492267c11a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327096311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.327096311
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1880095175
Short name T126
Test name
Test status
Simulation time 54712136 ps
CPU time 0.86 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:36:55 PM PDT 24
Peak memory 196388 kb
Host smart-99629c7e-c509-41e4-b064-45139b9e08dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880095175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1880095175
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.56107355
Short name T333
Test name
Test status
Simulation time 1225726392 ps
CPU time 19.37 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 197444 kb
Host smart-6642bc21-cdae-457a-aca1-e22a01ea9fc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stress
.56107355
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3578218072
Short name T649
Test name
Test status
Simulation time 53468042 ps
CPU time 0.92 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 198292 kb
Host smart-7e639a01-5cfb-435e-89be-af3816b33807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578218072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3578218072
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.240969726
Short name T202
Test name
Test status
Simulation time 171595571 ps
CPU time 1.21 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 197240 kb
Host smart-1c4dac48-55df-4cf3-9fe7-4324034c6812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240969726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.240969726
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3951233950
Short name T373
Test name
Test status
Simulation time 454266673 ps
CPU time 2.02 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 198812 kb
Host smart-9428efdc-f51e-4a27-9b22-9f86bfdb3262
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951233950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3951233950
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4140218653
Short name T277
Test name
Test status
Simulation time 174813003 ps
CPU time 3.28 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 198516 kb
Host smart-0013b72c-31d2-4f09-a6f5-a78677e0c0d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140218653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4140218653
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3911681124
Short name T269
Test name
Test status
Simulation time 281076036 ps
CPU time 1.27 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 198548 kb
Host smart-8d51c437-129a-41cf-889d-b44a5127ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911681124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3911681124
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2141870277
Short name T569
Test name
Test status
Simulation time 32197934 ps
CPU time 0.77 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196048 kb
Host smart-511000bd-e597-48d7-b350-a3333ee3480d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141870277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2141870277
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1454965274
Short name T5
Test name
Test status
Simulation time 126220018 ps
CPU time 1.66 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 198400 kb
Host smart-7c67494d-4613-4992-9567-32da714698cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454965274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1454965274
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2362490035
Short name T644
Test name
Test status
Simulation time 174291455 ps
CPU time 0.97 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 196292 kb
Host smart-9003d6b3-7c2a-4261-9a1f-1af968519e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362490035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2362490035
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.318175196
Short name T196
Test name
Test status
Simulation time 238068546 ps
CPU time 0.69 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 194664 kb
Host smart-a6426498-3ddb-49d7-8aba-be2d5d9b520f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318175196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.318175196
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.429419814
Short name T486
Test name
Test status
Simulation time 11836370243 ps
CPU time 109.03 seconds
Started Aug 04 04:36:58 PM PDT 24
Finished Aug 04 04:38:52 PM PDT 24
Peak memory 198592 kb
Host smart-79ccc0a3-423f-424f-9869-d1cc3ac033f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429419814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.429419814
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1051088471
Short name T527
Test name
Test status
Simulation time 44192124591 ps
CPU time 977.62 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:53:06 PM PDT 24
Peak memory 198252 kb
Host smart-a9503d92-f3ac-48a6-a5f0-0c19c967e270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1051088471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1051088471
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2713750532
Short name T432
Test name
Test status
Simulation time 29926394 ps
CPU time 0.55 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 195056 kb
Host smart-0d3d923d-a065-4979-b02c-b786a553c09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713750532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2713750532
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.664379121
Short name T391
Test name
Test status
Simulation time 20732485 ps
CPU time 0.72 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 195780 kb
Host smart-12ca6b98-d7a8-4649-b45c-9d82597bca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664379121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.664379121
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2514820234
Short name T96
Test name
Test status
Simulation time 2133631338 ps
CPU time 15.07 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:37:08 PM PDT 24
Peak memory 197256 kb
Host smart-55f26924-59e6-412a-bbbc-d3b2e847b88a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514820234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2514820234
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2718100665
Short name T21
Test name
Test status
Simulation time 242771012 ps
CPU time 0.8 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196276 kb
Host smart-4bb17d84-6c99-4e27-8917-7133b7537573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718100665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2718100665
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.815965464
Short name T296
Test name
Test status
Simulation time 359175357 ps
CPU time 1.39 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 196244 kb
Host smart-7b1745e1-5e0b-4432-aba0-6643a425960f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815965464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.815965464
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3824793741
Short name T652
Test name
Test status
Simulation time 25181822 ps
CPU time 1.15 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:36 PM PDT 24
Peak memory 197840 kb
Host smart-0e02d57a-4879-4d93-a617-a5a1317924aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824793741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3824793741
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1187666357
Short name T548
Test name
Test status
Simulation time 605208848 ps
CPU time 2.88 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:51 PM PDT 24
Peak memory 198556 kb
Host smart-fd777859-5194-466c-afc1-d08cc58320c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187666357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1187666357
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4287376331
Short name T204
Test name
Test status
Simulation time 21640649 ps
CPU time 0.83 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:53 PM PDT 24
Peak memory 196584 kb
Host smart-84136262-7644-4cb3-bed7-a6e3a5a784a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287376331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4287376331
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.496061474
Short name T290
Test name
Test status
Simulation time 33181609 ps
CPU time 0.85 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 197864 kb
Host smart-0db817aa-4401-469d-a37d-59412dda7b32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496061474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.496061474
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3103979857
Short name T53
Test name
Test status
Simulation time 77910463 ps
CPU time 2.81 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 198440 kb
Host smart-f751e06f-7491-46c3-9301-cd769a0e4714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103979857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3103979857
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3379384844
Short name T609
Test name
Test status
Simulation time 383157542 ps
CPU time 1.28 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:51 PM PDT 24
Peak memory 197192 kb
Host smart-53487003-ad01-476b-abe3-22b851511f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379384844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3379384844
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1260330740
Short name T142
Test name
Test status
Simulation time 54374281 ps
CPU time 0.76 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 195692 kb
Host smart-de78c8dd-4a01-4e4b-a948-6da6cd431920
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260330740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1260330740
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1689086103
Short name T254
Test name
Test status
Simulation time 774049400 ps
CPU time 17.04 seconds
Started Aug 04 04:36:49 PM PDT 24
Finished Aug 04 04:37:06 PM PDT 24
Peak memory 198548 kb
Host smart-cf52926e-99d8-4a4e-8177-a4ec1661bb46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689086103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1689086103
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3994857254
Short name T673
Test name
Test status
Simulation time 68548831333 ps
CPU time 1313.31 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:58:45 PM PDT 24
Peak memory 198872 kb
Host smart-e3dc728d-5587-4a7e-a054-ae0001beaeff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3994857254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3994857254
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2353660168
Short name T550
Test name
Test status
Simulation time 158769992 ps
CPU time 0.94 seconds
Started Aug 04 04:36:55 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 197132 kb
Host smart-fe8160bc-998e-4c67-9e20-47f4d994438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353660168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2353660168
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3718732806
Short name T390
Test name
Test status
Simulation time 1688722180 ps
CPU time 24.48 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 198488 kb
Host smart-691951c6-87e3-4600-8f97-9868c7a750cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718732806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3718732806
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2690293747
Short name T579
Test name
Test status
Simulation time 56092623 ps
CPU time 0.75 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 196192 kb
Host smart-b47bec36-82f1-497b-9a24-b05450fcffe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690293747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2690293747
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4284785862
Short name T146
Test name
Test status
Simulation time 519831154 ps
CPU time 0.95 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 196488 kb
Host smart-a9eada7a-6ecc-4bda-95a6-e954ad9b7f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284785862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4284785862
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2015499877
Short name T169
Test name
Test status
Simulation time 211884969 ps
CPU time 1.36 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:02 PM PDT 24
Peak memory 197220 kb
Host smart-329c2f18-3c2f-4736-b447-fe8911e2266f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015499877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2015499877
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2784282233
Short name T382
Test name
Test status
Simulation time 137963442 ps
CPU time 1.12 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 197216 kb
Host smart-2c10eebd-25f7-46a0-9d77-5e5832cea1a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784282233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2784282233
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2894604862
Short name T165
Test name
Test status
Simulation time 102675630 ps
CPU time 1.08 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:09 PM PDT 24
Peak memory 196516 kb
Host smart-98a44240-c7af-4306-90e8-81f54f0d3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894604862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2894604862
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3614230123
Short name T485
Test name
Test status
Simulation time 29287410 ps
CPU time 0.78 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:36:52 PM PDT 24
Peak memory 195788 kb
Host smart-cf2bfe5d-02ce-43ca-84aa-26b64add748e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614230123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3614230123
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1910820052
Short name T154
Test name
Test status
Simulation time 468081309 ps
CPU time 5.09 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 198456 kb
Host smart-5a52fca7-8e63-4ec6-b3cc-715ce3ab4271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910820052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1910820052
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3412007704
Short name T193
Test name
Test status
Simulation time 161160815 ps
CPU time 0.82 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 195760 kb
Host smart-e1be2916-b36c-4002-ac14-a005539bcc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412007704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3412007704
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3659406577
Short name T194
Test name
Test status
Simulation time 63567531 ps
CPU time 1.21 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:36:55 PM PDT 24
Peak memory 196132 kb
Host smart-272dadfe-0835-4ca8-8374-c0edc26f9738
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659406577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3659406577
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.848503831
Short name T623
Test name
Test status
Simulation time 7067807603 ps
CPU time 89.84 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:38:23 PM PDT 24
Peak memory 198644 kb
Host smart-21905fdd-49cd-480c-b077-f83a0bf5ff04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848503831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.848503831
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3853613819
Short name T93
Test name
Test status
Simulation time 11193136 ps
CPU time 0.58 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 194340 kb
Host smart-675975d3-b714-43fa-b007-aa659803eb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853613819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3853613819
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3883582234
Short name T691
Test name
Test status
Simulation time 29824165 ps
CPU time 0.78 seconds
Started Aug 04 04:37:05 PM PDT 24
Finished Aug 04 04:37:06 PM PDT 24
Peak memory 195692 kb
Host smart-a80e41e1-3a65-4ecc-9564-e22dc30fc59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883582234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3883582234
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4192575566
Short name T398
Test name
Test status
Simulation time 1630959273 ps
CPU time 14.96 seconds
Started Aug 04 04:37:05 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 197324 kb
Host smart-dfa42d73-d78d-4b57-a922-e3c5f70c8aeb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192575566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4192575566
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2967379373
Short name T139
Test name
Test status
Simulation time 106801080 ps
CPU time 0.7 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 196996 kb
Host smart-bde08c9e-5752-49c2-b5d7-c5e36b185b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967379373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2967379373
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3540128568
Short name T63
Test name
Test status
Simulation time 108023747 ps
CPU time 1.41 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 197456 kb
Host smart-d2365456-92f9-415c-a252-a28dd2adfc06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540128568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3540128568
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1091403750
Short name T447
Test name
Test status
Simulation time 36579268 ps
CPU time 1.43 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 196520 kb
Host smart-f3dd309f-af79-4b7d-8685-410ebd6fb33e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091403750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1091403750
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3759485841
Short name T289
Test name
Test status
Simulation time 97538083 ps
CPU time 2.23 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 198552 kb
Host smart-40c83ef4-30bb-4e9b-8b5a-f3c4b69c9ac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759485841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3759485841
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1048223692
Short name T297
Test name
Test status
Simulation time 108954709 ps
CPU time 1.07 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 196448 kb
Host smart-666802c2-2855-4f0c-9f91-d087cb3bc36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048223692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1048223692
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2701325576
Short name T429
Test name
Test status
Simulation time 110744307 ps
CPU time 0.74 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:53 PM PDT 24
Peak memory 196680 kb
Host smart-9beb23d6-f817-4248-8ed6-afa49e64b992
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701325576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2701325576
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2501531812
Short name T181
Test name
Test status
Simulation time 306097011 ps
CPU time 3.43 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 198492 kb
Host smart-7a0366f7-4795-41fb-9a0a-7b41078a5778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501531812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2501531812
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2228846285
Short name T243
Test name
Test status
Simulation time 35350456 ps
CPU time 0.8 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:03 PM PDT 24
Peak memory 195720 kb
Host smart-178f2b29-b65e-4276-a839-45ef26aa4649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228846285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2228846285
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2892947544
Short name T168
Test name
Test status
Simulation time 171277994 ps
CPU time 0.93 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 196744 kb
Host smart-5d35c48d-d570-41cf-a63b-c1289120c49c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892947544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2892947544
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3178170635
Short name T18
Test name
Test status
Simulation time 26687507425 ps
CPU time 155.74 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:40:02 PM PDT 24
Peak memory 198660 kb
Host smart-e47aae6a-6d2f-4b0b-bc50-b97ebb44cbbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178170635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3178170635
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2669081221
Short name T526
Test name
Test status
Simulation time 14074669 ps
CPU time 0.55 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 194496 kb
Host smart-3eb27e24-4bfb-479b-813b-207226aab03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669081221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2669081221
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2770442059
Short name T276
Test name
Test status
Simulation time 21638276 ps
CPU time 0.66 seconds
Started Aug 04 04:36:57 PM PDT 24
Finished Aug 04 04:36:57 PM PDT 24
Peak memory 194592 kb
Host smart-f6ca9410-4330-4655-a253-d01c6adf03b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770442059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2770442059
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2558688050
Short name T320
Test name
Test status
Simulation time 6226046627 ps
CPU time 15.95 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 197484 kb
Host smart-beb98188-03c9-4364-8424-a42df0013481
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558688050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2558688050
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1687742861
Short name T699
Test name
Test status
Simulation time 89563932 ps
CPU time 0.62 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 195032 kb
Host smart-6cd98343-56b7-4dbe-a6a1-899a12d82d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687742861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1687742861
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.509122045
Short name T215
Test name
Test status
Simulation time 107491441 ps
CPU time 1.41 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 197508 kb
Host smart-a73e2c7b-06d9-4fef-bb1c-2082206fe028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509122045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.509122045
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.764397022
Short name T77
Test name
Test status
Simulation time 47226761 ps
CPU time 1.82 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 198372 kb
Host smart-130e9824-2feb-4467-9483-4a0aba44e725
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764397022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.764397022
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2250299997
Short name T385
Test name
Test status
Simulation time 292335961 ps
CPU time 2.26 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 197672 kb
Host smart-06d1354c-8c81-4484-ac01-36f7b66ff729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250299997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2250299997
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3863400714
Short name T560
Test name
Test status
Simulation time 129650690 ps
CPU time 1.16 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:36:53 PM PDT 24
Peak memory 197556 kb
Host smart-23c28a28-3717-46a5-831d-501d98512d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863400714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3863400714
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3403263556
Short name T334
Test name
Test status
Simulation time 41486159 ps
CPU time 0.88 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 196512 kb
Host smart-7d4de48d-d500-440d-a890-6ccc29868915
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403263556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3403263556
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1929079755
Short name T445
Test name
Test status
Simulation time 374640527 ps
CPU time 4.7 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 198488 kb
Host smart-b3d37792-b16b-4757-b720-a1e1e8f9f395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929079755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1929079755
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1775868958
Short name T547
Test name
Test status
Simulation time 140841870 ps
CPU time 1.33 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:09 PM PDT 24
Peak memory 197176 kb
Host smart-6c863969-35cb-4005-a197-d1e903cc3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775868958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1775868958
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2237488042
Short name T222
Test name
Test status
Simulation time 76616452 ps
CPU time 1.42 seconds
Started Aug 04 04:36:55 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 198496 kb
Host smart-8b22be60-5c31-44ac-957a-f89562eccbe7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237488042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2237488042
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1286532714
Short name T9
Test name
Test status
Simulation time 55766015736 ps
CPU time 165.52 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:39:45 PM PDT 24
Peak memory 198980 kb
Host smart-23b2bbbe-01a0-4171-8e16-83ead4d4c52a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286532714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1286532714
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.153377083
Short name T60
Test name
Test status
Simulation time 194078488233 ps
CPU time 695.14 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:48:23 PM PDT 24
Peak memory 206988 kb
Host smart-1c1f5bdd-b433-4d83-bbd4-d9c9bfaa81ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=153377083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.153377083
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2516342300
Short name T499
Test name
Test status
Simulation time 60402413 ps
CPU time 0.6 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 194732 kb
Host smart-4cf8eec6-9753-4479-9995-4f8e0f067ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516342300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2516342300
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1032371261
Short name T530
Test name
Test status
Simulation time 31917786 ps
CPU time 0.75 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196660 kb
Host smart-8e54fa23-acbf-4bb6-b23f-d8c56ac83408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032371261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1032371261
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3816383683
Short name T270
Test name
Test status
Simulation time 451607591 ps
CPU time 6.53 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 197360 kb
Host smart-64269e42-3a9f-43c3-ae6e-c1cbb05b8f41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816383683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3816383683
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.574647680
Short name T624
Test name
Test status
Simulation time 79530385 ps
CPU time 0.76 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 196452 kb
Host smart-ce7eb8ce-df54-428f-a32e-588848fe76c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574647680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.574647680
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3993021459
Short name T401
Test name
Test status
Simulation time 1140749113 ps
CPU time 1.28 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 196916 kb
Host smart-83b83813-61a8-4f62-ae41-f1285f9be05c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993021459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3993021459
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1844669246
Short name T314
Test name
Test status
Simulation time 32863169 ps
CPU time 1.32 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 197000 kb
Host smart-94183366-5d4d-4fe6-b3f5-2f15dc9d1cca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844669246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1844669246
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1482436819
Short name T282
Test name
Test status
Simulation time 291945854 ps
CPU time 1.8 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:20 PM PDT 24
Peak memory 196748 kb
Host smart-bfac0096-4699-4aa9-b3c2-6587e43cad9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482436819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1482436819
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3380744723
Short name T155
Test name
Test status
Simulation time 61515775 ps
CPU time 1.03 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:08 PM PDT 24
Peak memory 196464 kb
Host smart-63986f2f-b5d2-488e-a7c2-50c838072eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380744723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3380744723
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3294410457
Short name T448
Test name
Test status
Simulation time 115902677 ps
CPU time 0.94 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 196484 kb
Host smart-780ebdf8-5e49-4613-b06b-0b30c29a1bf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294410457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3294410457
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2614282077
Short name T671
Test name
Test status
Simulation time 356058695 ps
CPU time 3.89 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 198460 kb
Host smart-0d35e011-8125-4937-a4da-9d46cdea701e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614282077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2614282077
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2228891715
Short name T324
Test name
Test status
Simulation time 215357155 ps
CPU time 1.06 seconds
Started Aug 04 04:36:58 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 196292 kb
Host smart-85b99d31-e122-4b2f-bbc1-de83fae2db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228891715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2228891715
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.443969739
Short name T472
Test name
Test status
Simulation time 72992320 ps
CPU time 1.09 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:36:52 PM PDT 24
Peak memory 197248 kb
Host smart-2112ab07-25be-4007-96f0-2b0b1e803994
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443969739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.443969739
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2219161159
Short name T347
Test name
Test status
Simulation time 9341276769 ps
CPU time 94.52 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:38:43 PM PDT 24
Peak memory 192316 kb
Host smart-eab6ed8d-0038-4efc-8ab3-e14de8e29242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219161159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2219161159
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4179641282
Short name T580
Test name
Test status
Simulation time 34188415 ps
CPU time 0.56 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 195056 kb
Host smart-42ffb0e7-405d-4fc2-a2bc-a08802cd3733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179641282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4179641282
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.939448144
Short name T344
Test name
Test status
Simulation time 109179886 ps
CPU time 0.81 seconds
Started Aug 04 04:36:18 PM PDT 24
Finished Aug 04 04:36:19 PM PDT 24
Peak memory 195732 kb
Host smart-b04e8c4d-4eb3-4003-bbef-794157c49f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939448144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.939448144
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3541506315
Short name T475
Test name
Test status
Simulation time 1378767545 ps
CPU time 11.6 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 195960 kb
Host smart-b30eb418-63e8-47ef-8724-78204bd221dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541506315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3541506315
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.42514659
Short name T700
Test name
Test status
Simulation time 70826081 ps
CPU time 1.03 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 197148 kb
Host smart-56df634a-1da8-491e-a18f-baec9febe280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.42514659
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4186085787
Short name T493
Test name
Test status
Simulation time 24595310 ps
CPU time 0.73 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:28 PM PDT 24
Peak memory 195868 kb
Host smart-feaeb47e-17dc-4a9e-ac48-353ed858650d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186085787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4186085787
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1779095356
Short name T441
Test name
Test status
Simulation time 87666991 ps
CPU time 3.3 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 198696 kb
Host smart-ea4af338-def9-47d5-849a-f7bfb6a6d35a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779095356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1779095356
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1493987578
Short name T710
Test name
Test status
Simulation time 470415296 ps
CPU time 3.02 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 198608 kb
Host smart-b81a6206-b4e9-41de-8ceb-10b19eab61e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493987578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1493987578
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3792355283
Short name T280
Test name
Test status
Simulation time 97739489 ps
CPU time 0.65 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:36 PM PDT 24
Peak memory 194656 kb
Host smart-95722542-11e4-4ce5-9192-8bd77c04a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792355283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3792355283
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3471775325
Short name T554
Test name
Test status
Simulation time 24747643 ps
CPU time 0.89 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 196472 kb
Host smart-6ecf96b1-f360-4987-a670-a7c856b5c4f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471775325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3471775325
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4228695297
Short name T553
Test name
Test status
Simulation time 665135821 ps
CPU time 2.61 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 198776 kb
Host smart-60139f8a-e560-4d62-9bc7-5526f967620e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228695297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4228695297
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.4177758160
Short name T256
Test name
Test status
Simulation time 52686919 ps
CPU time 0.94 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 196900 kb
Host smart-7004a063-04ba-4d6a-868b-e4b32b2abf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177758160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4177758160
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3194986792
Short name T396
Test name
Test status
Simulation time 111741888 ps
CPU time 1.34 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 196700 kb
Host smart-1600cd7b-465b-4f3f-8aa6-a287d070369c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194986792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3194986792
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3882204809
Short name T619
Test name
Test status
Simulation time 10785783302 ps
CPU time 71.76 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 198612 kb
Host smart-18403e6f-c0f0-457c-93d2-35a4caf479d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882204809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3882204809
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3744598409
Short name T229
Test name
Test status
Simulation time 12270471 ps
CPU time 0.58 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 194356 kb
Host smart-6f4e28eb-7bd8-48b4-8f3e-22caff2fff34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744598409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3744598409
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.801042718
Short name T630
Test name
Test status
Simulation time 41589515 ps
CPU time 0.67 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 195100 kb
Host smart-eb7e36a5-b4f1-4443-b32f-4a8302069d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801042718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.801042718
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3528932259
Short name T137
Test name
Test status
Simulation time 306158116 ps
CPU time 14.62 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 196012 kb
Host smart-93827cfb-f48e-4f2b-b01c-dd4b69b987ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528932259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3528932259
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2638793725
Short name T487
Test name
Test status
Simulation time 53196954 ps
CPU time 0.83 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196416 kb
Host smart-2e1f87c6-24f0-4425-bc47-79347054d4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638793725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2638793725
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.927820536
Short name T264
Test name
Test status
Simulation time 33111280 ps
CPU time 0.75 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 195964 kb
Host smart-b8dd1bdb-c7de-4141-a918-81d9bbefaa5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927820536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.927820536
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3838432804
Short name T664
Test name
Test status
Simulation time 190151185 ps
CPU time 2.01 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 198540 kb
Host smart-f4b803c6-7676-47c9-b2d0-a6c9936df468
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838432804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3838432804
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2179764239
Short name T306
Test name
Test status
Simulation time 96213422 ps
CPU time 1.9 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:37:06 PM PDT 24
Peak memory 196592 kb
Host smart-e9052fea-c3d2-4b00-bddf-f8f9c64c8b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179764239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2179764239
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2818375459
Short name T302
Test name
Test status
Simulation time 57482687 ps
CPU time 0.8 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:37:20 PM PDT 24
Peak memory 197120 kb
Host smart-567212f8-4ffc-4284-9274-4e64280f049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818375459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2818375459
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3641438618
Short name T171
Test name
Test status
Simulation time 17853774 ps
CPU time 0.64 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 195400 kb
Host smart-d97eacfe-52e3-4b4f-9d12-85b2a44d7bef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641438618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3641438618
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1272667158
Short name T522
Test name
Test status
Simulation time 356334860 ps
CPU time 2.76 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:03 PM PDT 24
Peak memory 198528 kb
Host smart-62f44a01-d012-478c-a585-a2553c4e9b8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272667158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1272667158
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2129984314
Short name T520
Test name
Test status
Simulation time 47940593 ps
CPU time 0.78 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 195664 kb
Host smart-d8925589-6e82-451b-86f6-03e26196c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129984314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2129984314
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2158703031
Short name T145
Test name
Test status
Simulation time 114436944 ps
CPU time 0.95 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:36:57 PM PDT 24
Peak memory 197052 kb
Host smart-894be572-592b-4686-b6ca-08e9306aa49d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158703031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2158703031
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1770401814
Short name T132
Test name
Test status
Simulation time 4825714097 ps
CPU time 59.03 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:38:03 PM PDT 24
Peak memory 198652 kb
Host smart-a315616a-96a9-4bd8-b6bc-5277eb8c370e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770401814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1770401814
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3398178189
Short name T708
Test name
Test status
Simulation time 79486273 ps
CPU time 0.56 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 193184 kb
Host smart-5056fd91-a193-4657-9224-d5c7e1b10b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398178189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3398178189
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3459974990
Short name T69
Test name
Test status
Simulation time 56900641 ps
CPU time 0.62 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 194412 kb
Host smart-6a029794-c4ca-45d4-b7fe-8b29d7a3764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459974990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3459974990
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2882711135
Short name T160
Test name
Test status
Simulation time 517958982 ps
CPU time 6.63 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 197388 kb
Host smart-cf642266-b259-4a26-85b4-eabd9dd1a585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882711135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2882711135
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3598444969
Short name T128
Test name
Test status
Simulation time 368567006 ps
CPU time 1 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 197104 kb
Host smart-b2185cf7-1846-4cc2-81b6-a8b60529cb11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598444969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3598444969
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4070821134
Short name T239
Test name
Test status
Simulation time 176092712 ps
CPU time 1.17 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 196956 kb
Host smart-815faada-5487-439e-b37d-ba40fcad12dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070821134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4070821134
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2357306072
Short name T278
Test name
Test status
Simulation time 229339820 ps
CPU time 2.15 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 198624 kb
Host smart-599259f2-1230-4067-b327-5f0f55a01b76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357306072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2357306072
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3714536027
Short name T25
Test name
Test status
Simulation time 407570836 ps
CPU time 2.05 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 197504 kb
Host smart-e1484c1a-1e17-4ed5-89a6-5063146a7f0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714536027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3714536027
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.838206911
Short name T238
Test name
Test status
Simulation time 83119505 ps
CPU time 0.75 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 195804 kb
Host smart-0bf0029b-6aff-4cf8-a2af-f123fbe5e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838206911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.838206911
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.291166079
Short name T16
Test name
Test status
Simulation time 152617635 ps
CPU time 0.98 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 196440 kb
Host smart-7d89b933-f5aa-4bcb-9f87-2b1af46c3c9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291166079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.291166079
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1484614390
Short name T610
Test name
Test status
Simulation time 98127590 ps
CPU time 4.06 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 198500 kb
Host smart-9450a60a-1789-4f5e-9ae0-6989fedea36f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484614390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1484614390
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.801645023
Short name T629
Test name
Test status
Simulation time 117433666 ps
CPU time 0.94 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 196544 kb
Host smart-3eb97f13-c2ee-44e1-a31e-ee7d1823ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801645023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.801645023
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.281812645
Short name T310
Test name
Test status
Simulation time 106578170 ps
CPU time 1.1 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 196144 kb
Host smart-52586df7-f2a1-4476-859a-d16c369a9278
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281812645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.281812645
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1422724860
Short name T561
Test name
Test status
Simulation time 31672490486 ps
CPU time 118.18 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:39:12 PM PDT 24
Peak memory 198688 kb
Host smart-ea06bfae-836e-4d19-8cc5-b6d2b2841521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422724860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1422724860
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1234183733
Short name T283
Test name
Test status
Simulation time 13015154 ps
CPU time 0.6 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 194544 kb
Host smart-11aec4ad-7bf6-4587-9778-e11263c3488e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234183733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1234183733
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2828533629
Short name T381
Test name
Test status
Simulation time 106327635 ps
CPU time 0.83 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:07 PM PDT 24
Peak memory 196944 kb
Host smart-ac109a12-a2f8-4b86-bea6-89530a1649d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828533629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2828533629
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3871135451
Short name T152
Test name
Test status
Simulation time 1526228646 ps
CPU time 11.29 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 197212 kb
Host smart-16d54432-2398-4b23-9cb4-974ab8c91149
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871135451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3871135451
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2040707172
Short name T343
Test name
Test status
Simulation time 323234976 ps
CPU time 0.93 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:22 PM PDT 24
Peak memory 198116 kb
Host smart-aa009181-db17-4cee-9a2f-0f78f6d2c300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040707172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2040707172
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4180745766
Short name T361
Test name
Test status
Simulation time 342445012 ps
CPU time 1.29 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 198504 kb
Host smart-7fef3b4f-a8ac-4bed-82a7-9c546a958145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180745766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4180745766
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1535555397
Short name T178
Test name
Test status
Simulation time 185305938 ps
CPU time 3.52 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 198504 kb
Host smart-f804ecf7-9a91-4bdb-bb90-a3c811f3098a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535555397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1535555397
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3858530758
Short name T489
Test name
Test status
Simulation time 119947731 ps
CPU time 2 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 197416 kb
Host smart-4489ef74-708d-44a6-890f-219a045521a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858530758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3858530758
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1272305974
Short name T158
Test name
Test status
Simulation time 60378509 ps
CPU time 1.22 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 197568 kb
Host smart-1e4b2276-9e64-4c67-be27-842dbfd4cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272305974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1272305974
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1865285974
Short name T399
Test name
Test status
Simulation time 323007328 ps
CPU time 1 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 196496 kb
Host smart-b6022d85-3a2e-4a23-b4d6-b0340588a130
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865285974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1865285974
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2217299785
Short name T67
Test name
Test status
Simulation time 562655082 ps
CPU time 2.75 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 198500 kb
Host smart-f6cb3970-e387-4402-950a-7b6ab5aef405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217299785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2217299785
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3841204120
Short name T625
Test name
Test status
Simulation time 119152062 ps
CPU time 0.78 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 196704 kb
Host smart-c1b05331-0a61-418b-8ec0-980aa4368e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841204120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3841204120
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.430990406
Short name T426
Test name
Test status
Simulation time 30457628 ps
CPU time 0.99 seconds
Started Aug 04 04:36:52 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 196720 kb
Host smart-b9693633-4bb4-4de8-b1df-ae7687649761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430990406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.430990406
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3741001182
Short name T221
Test name
Test status
Simulation time 22937264662 ps
CPU time 79.2 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:38:29 PM PDT 24
Peak memory 192588 kb
Host smart-4135087c-0c3a-4374-a867-93f0a29a54b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741001182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3741001182
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3371211278
Short name T37
Test name
Test status
Simulation time 30391950 ps
CPU time 0.56 seconds
Started Aug 04 04:37:01 PM PDT 24
Finished Aug 04 04:37:02 PM PDT 24
Peak memory 194488 kb
Host smart-b1c2a109-b689-4f83-8c34-a0176832c19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371211278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3371211278
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.137440774
Short name T478
Test name
Test status
Simulation time 82328685 ps
CPU time 0.82 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 195900 kb
Host smart-bec6eeb8-48e6-4418-b174-f5453ee8c1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137440774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.137440774
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.755220641
Short name T417
Test name
Test status
Simulation time 1754944753 ps
CPU time 20.86 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 197532 kb
Host smart-109a375d-4754-4c4c-b16a-88d74b8081de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755220641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.755220641
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.742587364
Short name T704
Test name
Test status
Simulation time 99011829 ps
CPU time 0.9 seconds
Started Aug 04 04:36:51 PM PDT 24
Finished Aug 04 04:36:52 PM PDT 24
Peak memory 198380 kb
Host smart-463513c9-48c0-4664-a7dc-6dbdf8a3fe9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742587364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.742587364
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2471523240
Short name T261
Test name
Test status
Simulation time 69672943 ps
CPU time 1.36 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:02 PM PDT 24
Peak memory 196508 kb
Host smart-65bc52bc-4fa1-4eb0-ae75-c8091584d05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471523240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2471523240
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1697121210
Short name T120
Test name
Test status
Simulation time 21871949 ps
CPU time 0.9 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:03 PM PDT 24
Peak memory 197068 kb
Host smart-14ff031e-d209-436c-880d-7db7016338f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697121210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1697121210
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3785919009
Short name T13
Test name
Test status
Simulation time 461429970 ps
CPU time 1.87 seconds
Started Aug 04 04:37:07 PM PDT 24
Finished Aug 04 04:37:09 PM PDT 24
Peak memory 196656 kb
Host smart-a9c0a849-4f9c-4bf3-b343-38016dedadb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785919009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3785919009
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1968985781
Short name T571
Test name
Test status
Simulation time 65086430 ps
CPU time 1.35 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 197452 kb
Host smart-e73ce66c-940a-413b-9a7e-45c19b42f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968985781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1968985781
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.711622088
Short name T144
Test name
Test status
Simulation time 156573588 ps
CPU time 1.01 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 196260 kb
Host smart-da166ce3-aae5-4822-a56f-1a0e9f8ccc6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711622088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.711622088
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1386394329
Short name T544
Test name
Test status
Simulation time 88082621 ps
CPU time 1.81 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 198472 kb
Host smart-e55e6a5d-2aae-4eed-8de1-32eb5b2daebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386394329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1386394329
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2204331963
Short name T187
Test name
Test status
Simulation time 196799403 ps
CPU time 0.95 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 196964 kb
Host smart-b6f0e7fe-bb0b-4667-82bf-618703121ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204331963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2204331963
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3399896578
Short name T405
Test name
Test status
Simulation time 100532712 ps
CPU time 0.96 seconds
Started Aug 04 04:36:57 PM PDT 24
Finished Aug 04 04:36:58 PM PDT 24
Peak memory 196232 kb
Host smart-352c411a-9146-4a9c-9317-32d7db2fb848
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399896578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3399896578
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3718780241
Short name T635
Test name
Test status
Simulation time 11975927054 ps
CPU time 150.17 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:39:35 PM PDT 24
Peak memory 198664 kb
Host smart-f6ddab22-568c-4a3f-8e5a-fbc7f734f8eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718780241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3718780241
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.611611038
Short name T676
Test name
Test status
Simulation time 137634400610 ps
CPU time 788.07 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:50:19 PM PDT 24
Peak memory 198900 kb
Host smart-84d32dd0-a66b-47e4-aad0-39fc099d52e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=611611038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.611611038
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.463109215
Short name T525
Test name
Test status
Simulation time 21800204 ps
CPU time 0.56 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 195216 kb
Host smart-041ccef0-76fd-4120-b0dc-f3baa04b3462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463109215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.463109215
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1873080901
Short name T403
Test name
Test status
Simulation time 21732558 ps
CPU time 0.77 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 195764 kb
Host smart-e2b0a5cf-6f8b-4009-a995-eb006bf20ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873080901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1873080901
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.167851443
Short name T504
Test name
Test status
Simulation time 248923071 ps
CPU time 8.15 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 198484 kb
Host smart-dc08a2ce-098e-4cef-96da-ff3af4869074
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167851443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.167851443
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2035931544
Short name T591
Test name
Test status
Simulation time 46737418 ps
CPU time 0.64 seconds
Started Aug 04 04:37:01 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 194660 kb
Host smart-dde21cca-4c1a-46c6-86e0-bed6f897b435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035931544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2035931544
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.570742308
Short name T655
Test name
Test status
Simulation time 52271972 ps
CPU time 1.28 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 198516 kb
Host smart-e4eeade8-f7a3-45e6-b647-9cad37e33160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570742308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.570742308
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1626671797
Short name T465
Test name
Test status
Simulation time 74228181 ps
CPU time 2.12 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:08 PM PDT 24
Peak memory 196768 kb
Host smart-bab10f1c-82ea-490e-a06c-c9165502dc46
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626671797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1626671797
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1880458623
Short name T199
Test name
Test status
Simulation time 189724741 ps
CPU time 1.09 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 195928 kb
Host smart-c11b22f2-62ad-48e4-a5e4-36e3b4117f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880458623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1880458623
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3143251505
Short name T431
Test name
Test status
Simulation time 130362142 ps
CPU time 1.1 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 196520 kb
Host smart-d920bfe2-4735-4d60-be55-db9f9874cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143251505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3143251505
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2086322375
Short name T479
Test name
Test status
Simulation time 114976342 ps
CPU time 1.18 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 197572 kb
Host smart-fadcf033-2c13-48c5-bbc7-7dd684329a9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086322375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2086322375
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1213845015
Short name T459
Test name
Test status
Simulation time 134651538 ps
CPU time 5.6 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 198512 kb
Host smart-0e39df19-21a9-4ad9-a72a-f7967cdc7863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213845015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1213845015
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2093100587
Short name T337
Test name
Test status
Simulation time 155091730 ps
CPU time 1.19 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 197360 kb
Host smart-7cc59bd4-9149-410a-a3be-a2bbad1a027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093100587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2093100587
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.129709483
Short name T507
Test name
Test status
Simulation time 330700842 ps
CPU time 1.31 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 196984 kb
Host smart-c49f68fc-f0a6-412a-a86c-f36d10de8780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129709483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.129709483
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2644782833
Short name T631
Test name
Test status
Simulation time 7164913811 ps
CPU time 114.09 seconds
Started Aug 04 04:37:04 PM PDT 24
Finished Aug 04 04:38:58 PM PDT 24
Peak memory 198584 kb
Host smart-0cda3c07-dcba-4438-ac39-8c81b84af469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644782833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2644782833
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2605855359
Short name T36
Test name
Test status
Simulation time 14124192 ps
CPU time 0.57 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 194440 kb
Host smart-bdf98fca-5331-4461-ac0d-c0b27c74bc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605855359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2605855359
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1053355030
Short name T326
Test name
Test status
Simulation time 597870940 ps
CPU time 0.79 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 195928 kb
Host smart-cf4bdd33-bf8c-4bdd-b6e2-f1ad601ab384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053355030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1053355030
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.985636995
Short name T529
Test name
Test status
Simulation time 1413572733 ps
CPU time 10.08 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 197064 kb
Host smart-0b35da2a-9fa2-476f-b29f-08ffbdb68644
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985636995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.985636995
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3957415919
Short name T322
Test name
Test status
Simulation time 35419836 ps
CPU time 0.65 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:09 PM PDT 24
Peak memory 195704 kb
Host smart-be6eabff-b76a-4a23-a484-0cd3fd1688bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957415919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3957415919
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2712380194
Short name T581
Test name
Test status
Simulation time 381159826 ps
CPU time 0.9 seconds
Started Aug 04 04:37:00 PM PDT 24
Finished Aug 04 04:37:01 PM PDT 24
Peak memory 196468 kb
Host smart-b048cee9-f025-4111-be82-3251767270ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712380194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2712380194
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3823147863
Short name T273
Test name
Test status
Simulation time 112041281 ps
CPU time 1.31 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 198504 kb
Host smart-7e7b04ba-0fb5-4acf-b4b4-3c5b7689c143
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823147863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3823147863
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3549434123
Short name T354
Test name
Test status
Simulation time 667232579 ps
CPU time 3.18 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 198484 kb
Host smart-ed9e2920-428a-402c-a3d7-fdf3d5a00477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549434123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3549434123
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2768468624
Short name T684
Test name
Test status
Simulation time 77285308 ps
CPU time 0.86 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 197288 kb
Host smart-b329945d-f14a-4a7d-8923-6590603f8ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768468624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2768468624
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.618133588
Short name T368
Test name
Test status
Simulation time 79240458 ps
CPU time 0.68 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 196616 kb
Host smart-06291b89-adbd-49d2-94ff-29df263c38da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618133588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.618133588
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3275674002
Short name T286
Test name
Test status
Simulation time 96881924 ps
CPU time 2.15 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:19 PM PDT 24
Peak memory 198424 kb
Host smart-e937c4dc-ec75-4736-8c32-9c03736d8e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275674002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3275674002
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3203233796
Short name T140
Test name
Test status
Simulation time 57466329 ps
CPU time 1.14 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 196700 kb
Host smart-19bebef5-0211-4506-bddd-3a38eb87b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203233796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3203233796
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2748452652
Short name T414
Test name
Test status
Simulation time 66318322 ps
CPU time 1.06 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:36:55 PM PDT 24
Peak memory 196144 kb
Host smart-0fd4d2a5-0fd4-4f0a-bfa2-adc246858113
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748452652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2748452652
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2065543528
Short name T123
Test name
Test status
Simulation time 54371699392 ps
CPU time 222.22 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:40:36 PM PDT 24
Peak memory 198668 kb
Host smart-c9f5aca0-f1c0-43ae-92d8-4834bb4a9d23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065543528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2065543528
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2661054502
Short name T573
Test name
Test status
Simulation time 14473965 ps
CPU time 0.6 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:22 PM PDT 24
Peak memory 195080 kb
Host smart-e13a8d4a-79de-47cb-89f0-06aaf9f014cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661054502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2661054502
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1568377706
Short name T384
Test name
Test status
Simulation time 66020395 ps
CPU time 0.86 seconds
Started Aug 04 04:36:56 PM PDT 24
Finished Aug 04 04:36:57 PM PDT 24
Peak memory 196804 kb
Host smart-bf92bf65-31ff-443c-b828-413dbc1013fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568377706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1568377706
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2369734158
Short name T48
Test name
Test status
Simulation time 1211995056 ps
CPU time 3.82 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 197216 kb
Host smart-cd7d9340-dad2-4a3e-b880-b1ed81818403
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369734158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2369734158
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1480434498
Short name T645
Test name
Test status
Simulation time 75310909 ps
CPU time 0.88 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 197356 kb
Host smart-8e4483df-28de-411b-8e34-ed1a39456041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480434498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1480434498
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.420655791
Short name T551
Test name
Test status
Simulation time 57193361 ps
CPU time 0.63 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:36:55 PM PDT 24
Peak memory 194664 kb
Host smart-3206fe78-1b07-4edb-92ca-2bb6d80ce0c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420655791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.420655791
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2884635983
Short name T513
Test name
Test status
Simulation time 76212199 ps
CPU time 1.6 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 197128 kb
Host smart-e1d6806e-a3f7-405e-a027-f4341a7a3848
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884635983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2884635983
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4193394099
Short name T303
Test name
Test status
Simulation time 1155504788 ps
CPU time 2.52 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 196364 kb
Host smart-5b670c92-e267-4f90-a4da-af773fc3794e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193394099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4193394099
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2861435759
Short name T412
Test name
Test status
Simulation time 56621576 ps
CPU time 1.19 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 196280 kb
Host smart-02da0e3e-b6c8-4c96-85ae-c4d3c0418ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861435759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2861435759
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2638722022
Short name T574
Test name
Test status
Simulation time 82001827 ps
CPU time 0.97 seconds
Started Aug 04 04:36:53 PM PDT 24
Finished Aug 04 04:36:54 PM PDT 24
Peak memory 197060 kb
Host smart-a53f8628-ff43-4575-a823-574ecdebd603
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638722022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2638722022
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.618479292
Short name T163
Test name
Test status
Simulation time 350668985 ps
CPU time 4.08 seconds
Started Aug 04 04:37:07 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 198432 kb
Host smart-226046da-ecc6-48d3-88d6-c0d5e5cfdfa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618479292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.618479292
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.263880896
Short name T678
Test name
Test status
Simulation time 49917171 ps
CPU time 0.99 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 196336 kb
Host smart-75f946cc-746a-454e-bd44-7b75895d8365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263880896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.263880896
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2519110578
Short name T599
Test name
Test status
Simulation time 479443793 ps
CPU time 1.29 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 197608 kb
Host smart-3b86779d-b254-443d-847e-7ae1f350d632
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519110578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2519110578
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3111632587
Short name T379
Test name
Test status
Simulation time 9490874578 ps
CPU time 70.21 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:38:30 PM PDT 24
Peak memory 198776 kb
Host smart-6dabb101-3586-4204-90f2-82bf0176a9f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111632587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3111632587
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.49959568
Short name T59
Test name
Test status
Simulation time 307886885874 ps
CPU time 775.74 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:50:16 PM PDT 24
Peak memory 198784 kb
Host smart-4bdc8cc4-d60d-4c2a-ab9d-7fdf9d6a6ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=49959568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.49959568
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.542678865
Short name T689
Test name
Test status
Simulation time 55440370 ps
CPU time 0.55 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 195056 kb
Host smart-8b841934-457f-405b-b79f-c4182f83e53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542678865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.542678865
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3901396265
Short name T274
Test name
Test status
Simulation time 43289228 ps
CPU time 0.57 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 194288 kb
Host smart-9f6d3128-a32d-4973-976c-8ef5f90b66a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901396265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3901396265
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3350683908
Short name T240
Test name
Test status
Simulation time 205284547 ps
CPU time 9.57 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 196944 kb
Host smart-dfe3c23e-ffd4-4bdc-9b65-093188eaa6b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350683908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3350683908
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1989914028
Short name T474
Test name
Test status
Simulation time 58262961 ps
CPU time 0.92 seconds
Started Aug 04 04:37:02 PM PDT 24
Finished Aug 04 04:37:03 PM PDT 24
Peak memory 198352 kb
Host smart-bc7e4199-9722-412e-9ac3-40ebedb16b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989914028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1989914028
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.474310370
Short name T133
Test name
Test status
Simulation time 319667443 ps
CPU time 1.35 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 198572 kb
Host smart-478cf8d3-1fc0-4cb2-b933-b02445ac6c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474310370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.474310370
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.820321492
Short name T346
Test name
Test status
Simulation time 144013888 ps
CPU time 1.58 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 198540 kb
Host smart-73675578-1984-446a-99b0-6d537e0dbcaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820321492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.820321492
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1310732769
Short name T615
Test name
Test status
Simulation time 108054179 ps
CPU time 0.92 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 195828 kb
Host smart-fcc16086-8948-4c98-bc34-15f94942184a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310732769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1310732769
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.131349828
Short name T70
Test name
Test status
Simulation time 101860456 ps
CPU time 0.87 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 196944 kb
Host smart-268d5737-49f2-40fc-b37a-48cc130ed42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131349828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.131349828
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3932340646
Short name T212
Test name
Test status
Simulation time 208937563 ps
CPU time 1.17 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 197508 kb
Host smart-4afa00d7-4a7b-419c-8a8e-9da53576c84e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932340646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3932340646
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3132805918
Short name T628
Test name
Test status
Simulation time 320985505 ps
CPU time 5.16 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 198488 kb
Host smart-815d0ddd-14a5-4685-a48e-fcb9a8dd5703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132805918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3132805918
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3174842736
Short name T147
Test name
Test status
Simulation time 180145557 ps
CPU time 1.28 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 197240 kb
Host smart-6319df3b-6a62-4dbd-a4a4-672e8ae7cce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174842736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3174842736
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.850101506
Short name T604
Test name
Test status
Simulation time 391673739 ps
CPU time 1.15 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 196236 kb
Host smart-79618a13-44f2-4396-8412-14e6550b4202
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850101506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.850101506
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.26489849
Short name T135
Test name
Test status
Simulation time 2502765009 ps
CPU time 32.82 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 198604 kb
Host smart-8812d8bf-384a-4b6b-ae40-3b8e0f26987b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gp
io_stress_all.26489849
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1574590356
Short name T540
Test name
Test status
Simulation time 14652243 ps
CPU time 0.58 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:19 PM PDT 24
Peak memory 194536 kb
Host smart-656bbc50-1229-4888-9692-a5727422761b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574590356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1574590356
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2760493726
Short name T605
Test name
Test status
Simulation time 60312870 ps
CPU time 0.61 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 194488 kb
Host smart-e9fafffd-f148-489b-b5ba-b626336c5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760493726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2760493726
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1497110906
Short name T444
Test name
Test status
Simulation time 1046116199 ps
CPU time 13.92 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 196100 kb
Host smart-7b33b9e8-f042-4382-83b1-415c478a473a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497110906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1497110906
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.179011151
Short name T519
Test name
Test status
Simulation time 78404245 ps
CPU time 1 seconds
Started Aug 04 04:37:10 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 198196 kb
Host smart-2cb83cd5-c982-489d-a3a4-f0e25f377e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179011151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.179011151
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3829528199
Short name T668
Test name
Test status
Simulation time 63079039 ps
CPU time 1.03 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 197020 kb
Host smart-c2cf7c32-59b0-4016-b525-9c517f5f64c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829528199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3829528199
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2921067568
Short name T211
Test name
Test status
Simulation time 89290377 ps
CPU time 3.28 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:19 PM PDT 24
Peak memory 198468 kb
Host smart-5be0afd8-0d97-43cf-acc4-149998fd7c7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921067568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2921067568
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.236201792
Short name T129
Test name
Test status
Simulation time 430648407 ps
CPU time 2.64 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 197720 kb
Host smart-e1126481-4178-40f7-b610-6f394acfd260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236201792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
236201792
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.635570141
Short name T562
Test name
Test status
Simulation time 21343134 ps
CPU time 0.9 seconds
Started Aug 04 04:36:59 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 196432 kb
Host smart-3d9cac5a-a687-4260-857a-f330b87976a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635570141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.635570141
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2993449106
Short name T161
Test name
Test status
Simulation time 24650767 ps
CPU time 0.71 seconds
Started Aug 04 04:37:05 PM PDT 24
Finished Aug 04 04:37:06 PM PDT 24
Peak memory 196572 kb
Host smart-7504a29e-4563-40fe-b5e4-e8a44c77c019
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993449106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2993449106
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1379815059
Short name T567
Test name
Test status
Simulation time 533627318 ps
CPU time 6.02 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 198444 kb
Host smart-470cadd6-834d-43e6-9b9c-b65b9ead7e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379815059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1379815059
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2420102352
Short name T482
Test name
Test status
Simulation time 73352303 ps
CPU time 1.29 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:17 PM PDT 24
Peak memory 197032 kb
Host smart-021ed375-f991-4b52-9ff1-cbd7eddd2237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420102352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2420102352
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1889272369
Short name T76
Test name
Test status
Simulation time 65929429 ps
CPU time 1.21 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:07 PM PDT 24
Peak memory 196728 kb
Host smart-4e3b44b5-ee05-4983-a0ef-97b01ce464db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889272369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1889272369
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3991087228
Short name T583
Test name
Test status
Simulation time 3370629875 ps
CPU time 38.54 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:50 PM PDT 24
Peak memory 198660 kb
Host smart-e63a4a4b-5565-4fff-afa2-d447bfe3a459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991087228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3991087228
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3867904941
Short name T400
Test name
Test status
Simulation time 16809042 ps
CPU time 0.61 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:23 PM PDT 24
Peak memory 195316 kb
Host smart-8df5a33f-2f99-4111-ac38-23902df8aea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867904941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3867904941
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2746983863
Short name T263
Test name
Test status
Simulation time 179276127 ps
CPU time 1 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 196976 kb
Host smart-35c5c283-f892-44d9-a5c7-23a73b0136f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746983863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2746983863
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1485817054
Short name T578
Test name
Test status
Simulation time 1773648569 ps
CPU time 22.82 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 197604 kb
Host smart-3326f626-5f1b-4ce1-ab51-2f67495cf586
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485817054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1485817054
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1378736035
Short name T503
Test name
Test status
Simulation time 81421488 ps
CPU time 0.69 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:19 PM PDT 24
Peak memory 195172 kb
Host smart-2f311d92-cd55-408d-8ef5-adfed2d11422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378736035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1378736035
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2670803565
Short name T521
Test name
Test status
Simulation time 245869681 ps
CPU time 1.28 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 196528 kb
Host smart-69b9416b-5efe-4694-beb7-5b7fa638bc80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670803565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2670803565
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3552279615
Short name T600
Test name
Test status
Simulation time 277474148 ps
CPU time 2.83 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 198604 kb
Host smart-860b0362-e860-44ce-88e8-70bc04e2ac5a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552279615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3552279615
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3154398756
Short name T198
Test name
Test status
Simulation time 100818916 ps
CPU time 3.01 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 197616 kb
Host smart-febf181a-9958-4728-b478-115ed21b100f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154398756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3154398756
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1103671024
Short name T257
Test name
Test status
Simulation time 42171051 ps
CPU time 1 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 197216 kb
Host smart-2f007e46-ac7a-4761-94e6-28c4de9ad85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103671024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1103671024
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1367162299
Short name T307
Test name
Test status
Simulation time 169323295 ps
CPU time 1.13 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 196448 kb
Host smart-d5683849-65c1-4431-a407-85f3cc2edf2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367162299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1367162299
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1038367946
Short name T259
Test name
Test status
Simulation time 767482112 ps
CPU time 5.75 seconds
Started Aug 04 04:37:06 PM PDT 24
Finished Aug 04 04:37:11 PM PDT 24
Peak memory 198576 kb
Host smart-5fe1420f-c53f-409e-8c96-15f4d8a69206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038367946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1038367946
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.768051001
Short name T449
Test name
Test status
Simulation time 40172583 ps
CPU time 0.92 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 197756 kb
Host smart-bc5d357d-3375-438a-9862-6f733808a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768051001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.768051001
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2564923482
Short name T323
Test name
Test status
Simulation time 48395393 ps
CPU time 1.01 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 196052 kb
Host smart-a6e6517a-755f-49ba-af49-82de2c8413aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564923482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2564923482
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2435162559
Short name T687
Test name
Test status
Simulation time 11475196318 ps
CPU time 160.71 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:40:00 PM PDT 24
Peak memory 198652 kb
Host smart-5c7ad568-e268-429f-bbab-7fcd11f6dc28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435162559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2435162559
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2078493534
Short name T677
Test name
Test status
Simulation time 30337753 ps
CPU time 0.56 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 194328 kb
Host smart-a69e35c4-7fed-4c05-946f-40fe75e6a6e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078493534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2078493534
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3167597571
Short name T559
Test name
Test status
Simulation time 571159925 ps
CPU time 0.85 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 195720 kb
Host smart-9346a2de-98f5-4e56-88fd-4e2a5d2e6e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167597571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3167597571
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2238904907
Short name T311
Test name
Test status
Simulation time 401965802 ps
CPU time 21.6 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 197364 kb
Host smart-f0598883-52e0-4404-8a94-5066773f1562
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238904907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2238904907
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.375137855
Short name T707
Test name
Test status
Simulation time 90792855 ps
CPU time 1.04 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 197124 kb
Host smart-9f3162b2-f7f9-4cfc-8680-bcddd3560d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375137855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.375137855
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.4265257311
Short name T488
Test name
Test status
Simulation time 192422556 ps
CPU time 1.1 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 197012 kb
Host smart-3deb0938-3e83-4e1f-9809-c44b08f1b566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265257311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.4265257311
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2056072512
Short name T698
Test name
Test status
Simulation time 175005948 ps
CPU time 1.72 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 197660 kb
Host smart-93457f40-13fc-42d4-b786-499544c78a13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056072512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2056072512
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2485163175
Short name T508
Test name
Test status
Simulation time 87027478 ps
CPU time 2 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 197152 kb
Host smart-b3ed5205-48c0-45c3-ad2f-bb58893837dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485163175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2485163175
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4221611237
Short name T275
Test name
Test status
Simulation time 55635689 ps
CPU time 1.11 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:36 PM PDT 24
Peak memory 197568 kb
Host smart-4c4ad3a8-e95f-4615-84f8-789cfb370c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221611237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4221611237
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.340691137
Short name T312
Test name
Test status
Simulation time 82069852 ps
CPU time 0.84 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 196888 kb
Host smart-a79f6b22-437c-4081-ace2-a7c351bd4d72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340691137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.340691137
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2001764911
Short name T251
Test name
Test status
Simulation time 1602819381 ps
CPU time 3.25 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 198476 kb
Host smart-36b39caa-f784-4279-a8d9-dc5443807f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001764911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2001764911
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.899677228
Short name T45
Test name
Test status
Simulation time 553721119 ps
CPU time 1.02 seconds
Started Aug 04 04:36:29 PM PDT 24
Finished Aug 04 04:36:30 PM PDT 24
Peak memory 215400 kb
Host smart-ecaaa586-c0d7-476a-9a07-8e7cc49706cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899677228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.899677228
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2078806089
Short name T338
Test name
Test status
Simulation time 274187016 ps
CPU time 1.27 seconds
Started Aug 04 04:36:33 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 197292 kb
Host smart-0af8af69-e66c-4d4f-9d27-08e292180883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078806089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2078806089
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2426011120
Short name T463
Test name
Test status
Simulation time 37944815 ps
CPU time 1 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 196096 kb
Host smart-aaa9026f-f334-4b0e-8ae7-b323a8304a08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426011120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2426011120
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2356110163
Short name T317
Test name
Test status
Simulation time 9600027492 ps
CPU time 127.57 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:38:31 PM PDT 24
Peak memory 198620 kb
Host smart-e5021fcd-35d2-4641-9dc6-f96a371a89ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356110163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2356110163
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.594519836
Short name T258
Test name
Test status
Simulation time 14486381 ps
CPU time 0.58 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 195192 kb
Host smart-5661740c-55a6-4e90-ac4f-2572f062142e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594519836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.594519836
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1302623309
Short name T506
Test name
Test status
Simulation time 329628461 ps
CPU time 0.63 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 194532 kb
Host smart-ec08c06d-ef84-4ca4-9cfe-3dfc11fc7e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302623309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1302623309
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2840797898
Short name T593
Test name
Test status
Simulation time 534001055 ps
CPU time 7.46 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 197344 kb
Host smart-a54ebbbf-3906-4874-9489-9c0fceab8c81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840797898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2840797898
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.4054978885
Short name T659
Test name
Test status
Simulation time 441520012 ps
CPU time 1.07 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 197172 kb
Host smart-7507785f-cf05-4ecd-bb60-5bf48f8343b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054978885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4054978885
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1266491132
Short name T328
Test name
Test status
Simulation time 22202846 ps
CPU time 0.8 seconds
Started Aug 04 04:37:13 PM PDT 24
Finished Aug 04 04:37:14 PM PDT 24
Peak memory 195772 kb
Host smart-a58e7697-3fae-4971-ae58-b0af367a814f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266491132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1266491132
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3737682143
Short name T709
Test name
Test status
Simulation time 76578041 ps
CPU time 2.97 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 198536 kb
Host smart-741c6599-e360-48a4-8976-3015c2c25e72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737682143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3737682143
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2632423633
Short name T288
Test name
Test status
Simulation time 159831404 ps
CPU time 2.89 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 197720 kb
Host smart-50b7ad3a-77eb-4f29-bae8-8407d3b2b294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632423633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2632423633
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.697832413
Short name T214
Test name
Test status
Simulation time 75885675 ps
CPU time 0.68 seconds
Started Aug 04 04:37:09 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 195480 kb
Host smart-94131cbc-c157-4651-b746-72c7a2d76c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697832413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.697832413
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1404733241
Short name T457
Test name
Test status
Simulation time 50023014 ps
CPU time 1.02 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:16 PM PDT 24
Peak memory 197028 kb
Host smart-accfd284-9561-4e5d-8b0c-936766a744e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404733241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1404733241
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1548632278
Short name T575
Test name
Test status
Simulation time 120782068 ps
CPU time 2.78 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:20 PM PDT 24
Peak memory 198472 kb
Host smart-1355bd97-8113-48ee-a833-22927519fcf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548632278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1548632278
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.643310499
Short name T566
Test name
Test status
Simulation time 55891545 ps
CPU time 0.94 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 196228 kb
Host smart-1d988495-7550-440a-a05a-362672e12064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643310499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.643310499
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1869691652
Short name T341
Test name
Test status
Simulation time 103490722 ps
CPU time 0.98 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 196216 kb
Host smart-ed0a52de-5aa9-45cd-8d8a-0c4dc58da530
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869691652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1869691652
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4101070067
Short name T696
Test name
Test status
Simulation time 34301299817 ps
CPU time 232.72 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:41:11 PM PDT 24
Peak memory 198644 kb
Host smart-01a67f0d-1f0d-49b1-b678-bca9564f9754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101070067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4101070067
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2383568132
Short name T701
Test name
Test status
Simulation time 14277637 ps
CPU time 0.6 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 195136 kb
Host smart-203f30b0-db9c-4a1b-80bc-979daab65986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383568132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2383568132
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1787047909
Short name T374
Test name
Test status
Simulation time 76531688 ps
CPU time 0.69 seconds
Started Aug 04 04:37:17 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 195640 kb
Host smart-a1b152df-74ae-483d-a5fa-c001f893a9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787047909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1787047909
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2102675703
Short name T201
Test name
Test status
Simulation time 1196408929 ps
CPU time 24.84 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 197348 kb
Host smart-5d928334-f47c-4767-8d2d-c97aca22c555
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102675703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2102675703
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.910256445
Short name T131
Test name
Test status
Simulation time 581347509 ps
CPU time 0.9 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 197644 kb
Host smart-4673c3fc-513c-4c0c-9f1c-81f69ab67f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910256445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.910256445
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2978105376
Short name T365
Test name
Test status
Simulation time 30393201 ps
CPU time 0.73 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:37:20 PM PDT 24
Peak memory 195800 kb
Host smart-efcdf776-6669-43fe-b614-414c809af08a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978105376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2978105376
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3279141477
Short name T210
Test name
Test status
Simulation time 78067759 ps
CPU time 3.05 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 198696 kb
Host smart-23c040df-54a0-4c9e-b0ee-81d90cd435dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279141477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3279141477
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1341408308
Short name T584
Test name
Test status
Simulation time 184262305 ps
CPU time 2.76 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 197204 kb
Host smart-28615290-19e7-488c-b51d-4b7da2db4f1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341408308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1341408308
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3227607764
Short name T483
Test name
Test status
Simulation time 94776422 ps
CPU time 0.95 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 196572 kb
Host smart-fe05bc06-fd15-4cc7-b013-d4555ce529a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227607764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3227607764
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2098076565
Short name T327
Test name
Test status
Simulation time 222850670 ps
CPU time 1.12 seconds
Started Aug 04 04:37:11 PM PDT 24
Finished Aug 04 04:37:12 PM PDT 24
Peak memory 196596 kb
Host smart-8568ed3c-cd02-4e62-96b9-9b8de3649875
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098076565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2098076565
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1023933745
Short name T225
Test name
Test status
Simulation time 432027000 ps
CPU time 4.47 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 198456 kb
Host smart-9c5fa002-d8df-4714-994f-6ed8dfa00a8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023933745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1023933745
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.587169545
Short name T437
Test name
Test status
Simulation time 470399422 ps
CPU time 1.57 seconds
Started Aug 04 04:37:16 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 197240 kb
Host smart-dce756d0-1734-4d6b-9fe7-06015047035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587169545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.587169545
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3038879929
Short name T376
Test name
Test status
Simulation time 138658788 ps
CPU time 1.14 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:32 PM PDT 24
Peak memory 196104 kb
Host smart-64576904-727b-4231-8caf-ad353d18072b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038879929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3038879929
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3044250133
Short name T458
Test name
Test status
Simulation time 17887279565 ps
CPU time 138.63 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:39:39 PM PDT 24
Peak memory 198648 kb
Host smart-096211e5-973c-4134-a09b-f1f0e434d97b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044250133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3044250133
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.228783805
Short name T26
Test name
Test status
Simulation time 130192868130 ps
CPU time 775.91 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:50:33 PM PDT 24
Peak memory 198724 kb
Host smart-569b93d7-6f0d-4bc0-a6bf-e9deae29f6be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=228783805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.228783805
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.441661376
Short name T469
Test name
Test status
Simulation time 33886421 ps
CPU time 0.58 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:22 PM PDT 24
Peak memory 194388 kb
Host smart-d6716320-264b-4c3c-89a1-8f895333425f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441661376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.441661376
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1313508424
Short name T183
Test name
Test status
Simulation time 113183815 ps
CPU time 0.82 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:32 PM PDT 24
Peak memory 195796 kb
Host smart-a59240e5-d850-4496-b8c6-e8dab3b10b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313508424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1313508424
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2557457152
Short name T498
Test name
Test status
Simulation time 1645180240 ps
CPU time 13.87 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 196012 kb
Host smart-8f2d8ee7-9011-4323-8b26-90b827310d76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557457152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2557457152
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2820975720
Short name T207
Test name
Test status
Simulation time 52609146 ps
CPU time 0.92 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 197480 kb
Host smart-edf9b427-b971-4e26-b5fb-e48a3455c703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820975720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2820975720
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2446698844
Short name T675
Test name
Test status
Simulation time 219536184 ps
CPU time 0.88 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 196128 kb
Host smart-e828c692-1b11-41fe-8f7b-921cc31f3cb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446698844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2446698844
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1250926435
Short name T408
Test name
Test status
Simulation time 211829522 ps
CPU time 2.51 seconds
Started Aug 04 04:37:22 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 198784 kb
Host smart-51eb1844-524a-42e5-9eb0-0a51b140e440
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250926435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1250926435
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.86460584
Short name T451
Test name
Test status
Simulation time 415664175 ps
CPU time 3.35 seconds
Started Aug 04 04:37:15 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 198496 kb
Host smart-3bd17c2a-e93b-438a-bbe1-171b2ca1267d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86460584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.86460584
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2073122553
Short name T281
Test name
Test status
Simulation time 225441619 ps
CPU time 0.77 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 195892 kb
Host smart-4c3f5694-70af-43f3-8839-35bc6945cb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073122553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2073122553
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1893162282
Short name T252
Test name
Test status
Simulation time 43237537 ps
CPU time 0.85 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 196264 kb
Host smart-0b6ee118-2274-4099-baa2-392750b409cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893162282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1893162282
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3503376575
Short name T353
Test name
Test status
Simulation time 115129055 ps
CPU time 2.78 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 198760 kb
Host smart-b6e7427b-85dd-484a-9020-ea1f465ba422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503376575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3503376575
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3399751026
Short name T532
Test name
Test status
Simulation time 163052250 ps
CPU time 1.29 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:23 PM PDT 24
Peak memory 196020 kb
Host smart-58e4d1d7-6f87-408c-92cd-934a0ae04dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399751026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3399751026
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2259764073
Short name T692
Test name
Test status
Simulation time 150277299 ps
CPU time 1.16 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 197056 kb
Host smart-58b37dcb-94dd-48c2-96ca-e256f20f551b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259764073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2259764073
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.859071248
Short name T363
Test name
Test status
Simulation time 20245381978 ps
CPU time 129.78 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:39:39 PM PDT 24
Peak memory 198560 kb
Host smart-91ca3848-ad83-4514-923d-00694b70c30c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859071248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.859071248
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2271640800
Short name T47
Test name
Test status
Simulation time 14792766 ps
CPU time 0.56 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 195076 kb
Host smart-400e091e-11b5-4bbf-ad66-4379e45787d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271640800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2271640800
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.463262668
Short name T620
Test name
Test status
Simulation time 113254945 ps
CPU time 0.73 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 195732 kb
Host smart-f471277c-5899-4c80-b629-b8cf912cae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463262668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.463262668
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1281156035
Short name T98
Test name
Test status
Simulation time 140104940 ps
CPU time 3.76 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 195932 kb
Host smart-c3d5f560-4536-40ec-bb3e-d5451ef24c1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281156035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1281156035
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2437566465
Short name T75
Test name
Test status
Simulation time 19785314 ps
CPU time 0.61 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 194816 kb
Host smart-6b96514d-8404-4f7d-b273-f3bf492355a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437566465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2437566465
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.550875714
Short name T61
Test name
Test status
Simulation time 67329620 ps
CPU time 1.11 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 197212 kb
Host smart-6e4f6903-7d07-4cdf-8a75-e8a5542b2085
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550875714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.550875714
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.748071995
Short name T446
Test name
Test status
Simulation time 110702630 ps
CPU time 1.25 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 197304 kb
Host smart-3eca9959-6de3-4fa2-bf69-d6587905b7ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748071995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.748071995
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1839497086
Short name T663
Test name
Test status
Simulation time 293772519 ps
CPU time 1.92 seconds
Started Aug 04 04:37:43 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 197308 kb
Host smart-5dfaf3d7-bbee-4c13-9ffa-0f9ca4b4250f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839497086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1839497086
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.372548473
Short name T613
Test name
Test status
Simulation time 47777251 ps
CPU time 1.03 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 197060 kb
Host smart-633bbf66-bca1-4e07-beee-43fb7fb36839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372548473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.372548473
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3511737490
Short name T309
Test name
Test status
Simulation time 20258754 ps
CPU time 0.85 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 197204 kb
Host smart-19344e63-8362-4ea3-a3e6-bb105df4922f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511737490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3511737490
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2722800246
Short name T702
Test name
Test status
Simulation time 459251063 ps
CPU time 6.19 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 198388 kb
Host smart-af1be328-ca90-42f4-a6e3-97476b6491a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722800246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2722800246
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.781753106
Short name T213
Test name
Test status
Simulation time 47341184 ps
CPU time 0.98 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 196232 kb
Host smart-b3f3868c-505e-4b4b-b7c8-69b7495f211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781753106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.781753106
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1843071452
Short name T466
Test name
Test status
Simulation time 208312539 ps
CPU time 0.88 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 195916 kb
Host smart-cc7d7ae9-2500-402c-b466-5cf900e0c99f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843071452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1843071452
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.279538386
Short name T543
Test name
Test status
Simulation time 2858103211 ps
CPU time 30.65 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:57 PM PDT 24
Peak memory 198692 kb
Host smart-65450f01-4e1f-4aea-9be9-e7e4c17b0ecc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279538386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.279538386
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3414370572
Short name T284
Test name
Test status
Simulation time 41526211 ps
CPU time 0.58 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 194576 kb
Host smart-c3298913-e1ff-4ddc-a69b-81af12dd0392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414370572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3414370572
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3456244907
Short name T345
Test name
Test status
Simulation time 16346419 ps
CPU time 0.63 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 195056 kb
Host smart-8b1de00d-6528-40a2-bda1-1082bb6737d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456244907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3456244907
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2522188276
Short name T95
Test name
Test status
Simulation time 2965464691 ps
CPU time 24.98 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 197504 kb
Host smart-f897a295-cb7d-4355-b561-175c74a2c1fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522188276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2522188276
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1106850696
Short name T244
Test name
Test status
Simulation time 145866519 ps
CPU time 0.76 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 196184 kb
Host smart-0b1502cd-afce-48c2-9b26-d71bdbd7cfa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106850696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1106850696
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2945238741
Short name T531
Test name
Test status
Simulation time 92399335 ps
CPU time 1.15 seconds
Started Aug 04 04:37:19 PM PDT 24
Finished Aug 04 04:37:20 PM PDT 24
Peak memory 197120 kb
Host smart-f8c2fabd-f8fa-4982-9475-ab1e7ee3e3ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945238741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2945238741
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2729273005
Short name T355
Test name
Test status
Simulation time 66532812 ps
CPU time 1.55 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 198700 kb
Host smart-8a04f86b-18c9-4130-81b1-ff310c3e9820
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729273005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2729273005
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2452853000
Short name T415
Test name
Test status
Simulation time 168929405 ps
CPU time 2.43 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 197544 kb
Host smart-68a2e6db-302b-49eb-af1b-91f2b7a17ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452853000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2452853000
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3913385747
Short name T392
Test name
Test status
Simulation time 207712443 ps
CPU time 1.25 seconds
Started Aug 04 04:37:21 PM PDT 24
Finished Aug 04 04:37:23 PM PDT 24
Peak memory 198500 kb
Host smart-9630c349-2b20-4cf5-938e-1bfe09492f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913385747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3913385747
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.184302860
Short name T394
Test name
Test status
Simulation time 28763525 ps
CPU time 1.03 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 196452 kb
Host smart-ed8a3351-0e75-4a85-883b-efd172faedad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184302860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.184302860
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2808311469
Short name T97
Test name
Test status
Simulation time 894612926 ps
CPU time 5.03 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 198480 kb
Host smart-486d4928-ae07-4088-9e18-d0c551add239
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808311469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2808311469
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3556445309
Short name T92
Test name
Test status
Simulation time 48582574 ps
CPU time 1.19 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 196264 kb
Host smart-960e7459-5711-4adb-8710-976fb4f0cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556445309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3556445309
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.893887564
Short name T369
Test name
Test status
Simulation time 1747768620 ps
CPU time 1.34 seconds
Started Aug 04 04:37:22 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 197184 kb
Host smart-e1f7a766-5abd-4c31-80e5-0bb38123bff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893887564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.893887564
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.764922151
Short name T3
Test name
Test status
Simulation time 19123480621 ps
CPU time 48.06 seconds
Started Aug 04 04:37:18 PM PDT 24
Finished Aug 04 04:38:06 PM PDT 24
Peak memory 198600 kb
Host smart-ed4581cb-da68-4343-a4d8-547c2b228493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764922151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.764922151
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1510547955
Short name T27
Test name
Test status
Simulation time 6867310711 ps
CPU time 205.43 seconds
Started Aug 04 04:37:22 PM PDT 24
Finished Aug 04 04:40:48 PM PDT 24
Peak memory 198816 kb
Host smart-16bf6d3a-e721-47b4-816d-b71d8533b68a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1510547955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1510547955
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3317062054
Short name T182
Test name
Test status
Simulation time 16078250 ps
CPU time 0.58 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 194632 kb
Host smart-631f8637-dea4-4c9e-b1b1-5d6ba694b125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317062054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3317062054
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2332266341
Short name T383
Test name
Test status
Simulation time 92230927 ps
CPU time 0.72 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 195568 kb
Host smart-eaadf85c-b1ea-4e30-b0e5-53481fa3db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332266341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2332266341
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.50959632
Short name T304
Test name
Test status
Simulation time 230338302 ps
CPU time 6.27 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 197156 kb
Host smart-7bc7ddbf-84ce-4b43-aaf3-16a39d93f3c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50959632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress
.50959632
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3890504678
Short name T711
Test name
Test status
Simulation time 44491943 ps
CPU time 0.74 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 196308 kb
Host smart-26d91097-65c3-430a-914d-cab15975be00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890504678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3890504678
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2866935379
Short name T219
Test name
Test status
Simulation time 80580691 ps
CPU time 0.67 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 195464 kb
Host smart-568c1320-b831-44e0-bd76-8a12730925fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866935379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2866935379
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.454616590
Short name T537
Test name
Test status
Simulation time 64279104 ps
CPU time 0.93 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 196556 kb
Host smart-4aae204e-d6dc-4f87-bfd7-061feb2b90a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454616590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.454616590
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.647905724
Short name T359
Test name
Test status
Simulation time 306791791 ps
CPU time 3.19 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:32 PM PDT 24
Peak memory 196352 kb
Host smart-feb36969-9790-4210-8ce4-49e1a467e6ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647905724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
647905724
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3262430857
Short name T340
Test name
Test status
Simulation time 36352247 ps
CPU time 0.81 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 195964 kb
Host smart-1b2bcb46-db1d-4bce-87a5-568391f42621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262430857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3262430857
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1097201306
Short name T455
Test name
Test status
Simulation time 62597429 ps
CPU time 1.23 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 198520 kb
Host smart-d0ca5e2a-2a46-4f2e-bb43-ff1ca9f2adb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097201306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1097201306
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1676906826
Short name T608
Test name
Test status
Simulation time 250262962 ps
CPU time 4.02 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 198484 kb
Host smart-c9694937-2b65-4e25-8255-ac8c1d5f8990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676906826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1676906826
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2366027726
Short name T159
Test name
Test status
Simulation time 80806863 ps
CPU time 1.3 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 196136 kb
Host smart-cc1062de-4099-4e91-9eec-3da905f729d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366027726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2366027726
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.530043362
Short name T342
Test name
Test status
Simulation time 103391491 ps
CPU time 0.92 seconds
Started Aug 04 04:37:20 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 196880 kb
Host smart-cd1667dc-48a6-4e9f-805c-62bda538d7ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530043362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.530043362
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2188875816
Short name T665
Test name
Test status
Simulation time 1846607108 ps
CPU time 41.64 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:38:14 PM PDT 24
Peak memory 198644 kb
Host smart-1b1430a9-4957-4abb-98c9-5ada63e36a8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188875816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2188875816
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1049602825
Short name T577
Test name
Test status
Simulation time 15380377 ps
CPU time 0.56 seconds
Started Aug 04 04:37:22 PM PDT 24
Finished Aug 04 04:37:23 PM PDT 24
Peak memory 194444 kb
Host smart-30638c58-be3d-4c7c-9e5e-ab0dca79409e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049602825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1049602825
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1553499062
Short name T68
Test name
Test status
Simulation time 28307769 ps
CPU time 0.82 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:32 PM PDT 24
Peak memory 196784 kb
Host smart-0b2356c2-70ef-4d49-b09b-bc6be8001ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553499062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1553499062
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.872561098
Short name T697
Test name
Test status
Simulation time 1032953607 ps
CPU time 11.31 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 197404 kb
Host smart-9ac02010-85c6-416d-a663-bdd46f6362fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872561098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.872561098
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1129430147
Short name T627
Test name
Test status
Simulation time 46419227 ps
CPU time 0.64 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:32 PM PDT 24
Peak memory 194888 kb
Host smart-acc0414f-440a-4e99-a8d6-3ad388b4d542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129430147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1129430147
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1515616266
Short name T249
Test name
Test status
Simulation time 61611492 ps
CPU time 1.11 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 197608 kb
Host smart-4cfc1b91-395f-41aa-b40e-1f2e4050c290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515616266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1515616266
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3652394727
Short name T435
Test name
Test status
Simulation time 87261598 ps
CPU time 3.26 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 197012 kb
Host smart-271a7649-2f76-4151-bc41-ec0194d5efaa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652394727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3652394727
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2721640415
Short name T271
Test name
Test status
Simulation time 34425963 ps
CPU time 0.91 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 194976 kb
Host smart-c6adb2b7-3034-46cc-8fb7-0c2e06d52d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721640415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2721640415
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.983193532
Short name T683
Test name
Test status
Simulation time 80911046 ps
CPU time 0.95 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 196484 kb
Host smart-4024d2c2-daf0-4068-afd1-8fafc8e06b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983193532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.983193532
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2680890672
Short name T564
Test name
Test status
Simulation time 569548521 ps
CPU time 1.2 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 197524 kb
Host smart-c6d22db3-f665-41b5-b432-14c535cd4770
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680890672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2680890672
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.985366851
Short name T491
Test name
Test status
Simulation time 617931577 ps
CPU time 5.67 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 198456 kb
Host smart-3523dc28-1b48-438b-8206-e19d2fe0c5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985366851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.985366851
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.134018298
Short name T419
Test name
Test status
Simulation time 517969468 ps
CPU time 0.91 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 197744 kb
Host smart-71d3863e-74d6-4923-a98e-3a246b85bb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134018298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.134018298
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2233813593
Short name T150
Test name
Test status
Simulation time 199309438 ps
CPU time 0.78 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 196400 kb
Host smart-e7f4fae7-70b3-4eba-8d71-0cc152623908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233813593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2233813593
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4131936295
Short name T356
Test name
Test status
Simulation time 34084649497 ps
CPU time 166.85 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:40:22 PM PDT 24
Peak memory 198672 kb
Host smart-79565c6d-589d-4414-8073-d34ac8765e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131936295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4131936295
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2500569948
Short name T364
Test name
Test status
Simulation time 12373135 ps
CPU time 0.59 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 194356 kb
Host smart-a40e50dd-767a-45a7-a594-fc4ad7834057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500569948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2500569948
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.382059631
Short name T164
Test name
Test status
Simulation time 17841195 ps
CPU time 0.65 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 194356 kb
Host smart-33e1618f-9ab3-4ab0-8dbe-f07cf3e758b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382059631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.382059631
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.743664249
Short name T192
Test name
Test status
Simulation time 929785555 ps
CPU time 27.12 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:59 PM PDT 24
Peak memory 198416 kb
Host smart-1e8550cf-fba7-4d9a-9d24-250bba634e0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743664249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.743664249
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3344551519
Short name T6
Test name
Test status
Simulation time 368491324 ps
CPU time 1.01 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:37:29 PM PDT 24
Peak memory 198188 kb
Host smart-9357bd6e-534b-4eba-9eba-7ef960244092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344551519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3344551519
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.907733265
Short name T517
Test name
Test status
Simulation time 58569751 ps
CPU time 1.02 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 196972 kb
Host smart-cb530dfe-b7e3-4c35-9936-8ef6fafe4bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907733265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.907733265
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2918836947
Short name T410
Test name
Test status
Simulation time 489643444 ps
CPU time 2.04 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 198500 kb
Host smart-359f0e74-2bf6-4450-9851-49f0724826a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918836947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2918836947
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1598844370
Short name T351
Test name
Test status
Simulation time 146780197 ps
CPU time 2.75 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 196984 kb
Host smart-76c4b2c1-d318-4ad4-b05a-13462b06195c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598844370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1598844370
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1653925261
Short name T688
Test name
Test status
Simulation time 83576559 ps
CPU time 0.89 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 197260 kb
Host smart-0564f668-388a-49dd-b093-03901170ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653925261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1653925261
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1725090524
Short name T188
Test name
Test status
Simulation time 114922956 ps
CPU time 1 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 196520 kb
Host smart-9d034a33-5298-4ed7-8667-85fb5a51bfd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725090524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1725090524
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2067074944
Short name T637
Test name
Test status
Simulation time 526146243 ps
CPU time 4.04 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:49 PM PDT 24
Peak memory 198388 kb
Host smart-41822d9a-e08d-42f8-b95c-3e6459d28b96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067074944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2067074944
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2951904566
Short name T156
Test name
Test status
Simulation time 32777881 ps
CPU time 0.81 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 196412 kb
Host smart-6f02bec5-4842-4215-b6aa-ecffc6a81b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951904566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2951904566
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.640458944
Short name T231
Test name
Test status
Simulation time 125089422 ps
CPU time 1.15 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:26 PM PDT 24
Peak memory 196204 kb
Host smart-8a09b412-02e8-4bef-8d80-feeb66e6b78e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640458944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.640458944
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4125959852
Short name T638
Test name
Test status
Simulation time 20814894425 ps
CPU time 64.27 seconds
Started Aug 04 04:37:28 PM PDT 24
Finished Aug 04 04:38:32 PM PDT 24
Peak memory 198616 kb
Host smart-4ca5a593-548b-487e-bb4e-cf96a3595034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125959852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4125959852
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2032261245
Short name T443
Test name
Test status
Simulation time 15822525 ps
CPU time 0.58 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 194628 kb
Host smart-e288dfed-6c47-4e4d-9d87-d3a6cd3860ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032261245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2032261245
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.262037733
Short name T234
Test name
Test status
Simulation time 24385437 ps
CPU time 0.67 seconds
Started Aug 04 04:37:24 PM PDT 24
Finished Aug 04 04:37:25 PM PDT 24
Peak memory 195120 kb
Host smart-51dbf0c2-7ae0-43e2-a166-578750ddf9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262037733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.262037733
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1513866113
Short name T418
Test name
Test status
Simulation time 1627783239 ps
CPU time 24.61 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:38:00 PM PDT 24
Peak memory 197332 kb
Host smart-17395744-5b76-46b6-b91c-df67cf530373
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513866113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1513866113
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.594790162
Short name T601
Test name
Test status
Simulation time 92857039 ps
CPU time 0.89 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 196352 kb
Host smart-a3144666-55da-42a7-b882-229ccc813725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594790162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.594790162
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1971404310
Short name T339
Test name
Test status
Simulation time 147044923 ps
CPU time 1.43 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 197652 kb
Host smart-d45b49b1-3add-41af-9b0e-e4bf0317366d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971404310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1971404310
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1874972773
Short name T321
Test name
Test status
Simulation time 67994667 ps
CPU time 2.8 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 198796 kb
Host smart-345e0d70-09f4-4c9e-991e-0c98aa502866
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874972773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1874972773
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.254193115
Short name T468
Test name
Test status
Simulation time 218956440 ps
CPU time 3.1 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 197636 kb
Host smart-aaf6d1d1-6741-4177-912a-c6de04ff5091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254193115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
254193115
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3756929703
Short name T15
Test name
Test status
Simulation time 32114331 ps
CPU time 0.84 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 197088 kb
Host smart-46df5f62-9bc8-4bee-ab0c-408a67108f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756929703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3756929703
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.629099629
Short name T332
Test name
Test status
Simulation time 136322359 ps
CPU time 1.13 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:37:24 PM PDT 24
Peak memory 196956 kb
Host smart-4e71acd7-3e12-46c4-8cad-19c38dd450ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629099629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.629099629
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1597954806
Short name T690
Test name
Test status
Simulation time 84423091 ps
CPU time 3.78 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 198528 kb
Host smart-2cd50239-758b-4317-a23a-295717825425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597954806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1597954806
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2914438868
Short name T477
Test name
Test status
Simulation time 176781423 ps
CPU time 1.12 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 196064 kb
Host smart-0398c640-0104-4331-8a0e-67b7cfb6fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914438868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2914438868
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1543782908
Short name T602
Test name
Test status
Simulation time 57428440 ps
CPU time 1.02 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196168 kb
Host smart-08b78903-5276-429b-9918-4eb49dc859c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543782908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1543782908
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3737211269
Short name T662
Test name
Test status
Simulation time 7690009021 ps
CPU time 39.55 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:38:14 PM PDT 24
Peak memory 198764 kb
Host smart-599bec75-f44a-47ea-ac73-496e8d116fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737211269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3737211269
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1212308978
Short name T55
Test name
Test status
Simulation time 199144044664 ps
CPU time 1228.69 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:57:59 PM PDT 24
Peak memory 198924 kb
Host smart-17e25bf0-b7bd-45c1-88da-58996af767d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1212308978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1212308978
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1897340685
Short name T596
Test name
Test status
Simulation time 31287122 ps
CPU time 0.59 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 194584 kb
Host smart-439ecb63-5463-4255-9211-c1c19cceffac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897340685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1897340685
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1190222021
Short name T325
Test name
Test status
Simulation time 29068127 ps
CPU time 0.7 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 196432 kb
Host smart-e78d6505-ece4-4aad-9154-07c7e0e91d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190222021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1190222021
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2514885825
Short name T621
Test name
Test status
Simulation time 2071462712 ps
CPU time 26.1 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:38:02 PM PDT 24
Peak memory 195976 kb
Host smart-57f5791f-a423-474f-89ea-c3f6e617dccf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514885825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2514885825
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3833368842
Short name T66
Test name
Test status
Simulation time 277868218 ps
CPU time 0.92 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196472 kb
Host smart-b125d514-69ea-44f1-8f9e-ac8345f3b3ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833368842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3833368842
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1766511038
Short name T467
Test name
Test status
Simulation time 229735071 ps
CPU time 1.18 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 197304 kb
Host smart-d1618b98-3668-44fe-aa78-36ffae53ffa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766511038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1766511038
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.643660442
Short name T336
Test name
Test status
Simulation time 166518352 ps
CPU time 1.78 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 196628 kb
Host smart-8d5987c3-40b4-4080-9eee-e03ad2c4c4d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643660442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
643660442
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4102434243
Short name T173
Test name
Test status
Simulation time 221478992 ps
CPU time 1.22 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 198552 kb
Host smart-8a176789-7cdd-4db4-b908-d39ff74de7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102434243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4102434243
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.209740107
Short name T203
Test name
Test status
Simulation time 110682559 ps
CPU time 0.85 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 196416 kb
Host smart-3f3ebc51-f91a-49d7-9be5-d913125528c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209740107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.209740107
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2410692804
Short name T295
Test name
Test status
Simulation time 165868087 ps
CPU time 2.99 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 198440 kb
Host smart-9349afe5-db48-4b37-9d90-7b7d8024d695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410692804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2410692804
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1005385838
Short name T190
Test name
Test status
Simulation time 312047011 ps
CPU time 1.24 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 198408 kb
Host smart-03b3da58-0d60-4071-acf5-900a0ce984e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005385838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1005385838
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3512304347
Short name T420
Test name
Test status
Simulation time 196710903 ps
CPU time 1.06 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 196276 kb
Host smart-1fcd3b5f-6bb3-44c0-a03d-27112db4565f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512304347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3512304347
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1541683967
Short name T480
Test name
Test status
Simulation time 18187923449 ps
CPU time 60.85 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:38:37 PM PDT 24
Peak memory 198688 kb
Host smart-424f6f10-3f39-4944-897d-67f4e77a2552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541683967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1541683967
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.786550742
Short name T279
Test name
Test status
Simulation time 26721530 ps
CPU time 0.56 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 194544 kb
Host smart-92097ce4-f3c6-4a22-a102-f55323c07fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786550742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.786550742
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.353186928
Short name T54
Test name
Test status
Simulation time 75336040 ps
CPU time 0.62 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 194500 kb
Host smart-5d287186-e902-415b-8586-1d3941106cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353186928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.353186928
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1560828445
Short name T706
Test name
Test status
Simulation time 1044268846 ps
CPU time 18.1 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:37:02 PM PDT 24
Peak memory 196932 kb
Host smart-992e7fca-8ddf-422c-be5c-78dcd09e3c23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560828445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1560828445
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3694756468
Short name T597
Test name
Test status
Simulation time 521648171 ps
CPU time 0.87 seconds
Started Aug 04 04:36:32 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 196504 kb
Host smart-e2a9280c-b1d7-4f40-b7bb-0c8e1b1671e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694756468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3694756468
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3362584036
Short name T162
Test name
Test status
Simulation time 223801382 ps
CPU time 1.08 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 196464 kb
Host smart-bc736f7f-8825-45ff-aef9-ab1b707a8585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362584036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3362584036
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.825776590
Short name T119
Test name
Test status
Simulation time 165853177 ps
CPU time 3.21 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:25 PM PDT 24
Peak memory 198472 kb
Host smart-b9fa7152-d35b-426b-ae43-280eafc0d111
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825776590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.825776590
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.478892295
Short name T681
Test name
Test status
Simulation time 60874390 ps
CPU time 1.37 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 196228 kb
Host smart-81c2f7c5-1a2c-44b3-ac88-f6bab1f7c398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478892295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.478892295
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.518954925
Short name T552
Test name
Test status
Simulation time 23820950 ps
CPU time 0.87 seconds
Started Aug 04 04:36:30 PM PDT 24
Finished Aug 04 04:36:31 PM PDT 24
Peak memory 197088 kb
Host smart-c9744152-f3d3-4d6d-9bbb-53b7a7ef32f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518954925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.518954925
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2267191448
Short name T685
Test name
Test status
Simulation time 71787118 ps
CPU time 0.74 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 196556 kb
Host smart-0486553f-3381-4189-bdfa-2cfa62183d86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267191448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2267191448
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2460997181
Short name T189
Test name
Test status
Simulation time 1431213484 ps
CPU time 4.76 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 198564 kb
Host smart-b55952a7-3ea6-4c7f-a482-55dec7008dd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460997181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2460997181
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3323690481
Short name T44
Test name
Test status
Simulation time 125940856 ps
CPU time 0.86 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 214360 kb
Host smart-ed354f7f-3f22-4874-92d4-8eb75594508b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323690481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3323690481
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3707859891
Short name T130
Test name
Test status
Simulation time 99508111 ps
CPU time 1.01 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 196072 kb
Host smart-f854991b-4cf6-4dd7-bb1c-81ed2fe540ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707859891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3707859891
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.534963540
Short name T206
Test name
Test status
Simulation time 196373932 ps
CPU time 1.2 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:36 PM PDT 24
Peak memory 198520 kb
Host smart-45e530a3-b8dc-4dda-a6ee-205cadc0df6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534963540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.534963540
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3505075077
Short name T46
Test name
Test status
Simulation time 12726781085 ps
CPU time 164.32 seconds
Started Aug 04 04:36:29 PM PDT 24
Finished Aug 04 04:39:14 PM PDT 24
Peak memory 198776 kb
Host smart-e2a8ebe6-8f38-4a62-b1bf-2363a7634380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505075077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3505075077
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4009057425
Short name T157
Test name
Test status
Simulation time 23077757 ps
CPU time 0.6 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 195300 kb
Host smart-94fa7d0f-4909-4c70-a56a-af343cb3956b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009057425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4009057425
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3111131648
Short name T582
Test name
Test status
Simulation time 25291345 ps
CPU time 0.86 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 197720 kb
Host smart-c58c5e15-208d-4965-adde-32591c6f606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111131648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3111131648
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1945223246
Short name T558
Test name
Test status
Simulation time 75974095 ps
CPU time 3.54 seconds
Started Aug 04 04:37:42 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 196192 kb
Host smart-61e6895f-4841-4826-9c73-33d811434027
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945223246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1945223246
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2352221993
Short name T404
Test name
Test status
Simulation time 41552682 ps
CPU time 0.65 seconds
Started Aug 04 04:37:54 PM PDT 24
Finished Aug 04 04:37:54 PM PDT 24
Peak memory 195724 kb
Host smart-e6b65668-c58e-4de0-8620-ac8ef4e16be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352221993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2352221993
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1119160574
Short name T372
Test name
Test status
Simulation time 34624870 ps
CPU time 0.8 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 196140 kb
Host smart-1c8a2602-ddaf-4f96-a7a4-70c174eff2e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119160574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1119160574
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1661217906
Short name T352
Test name
Test status
Simulation time 23027930 ps
CPU time 0.98 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 196360 kb
Host smart-25bda95f-ddba-4ce9-bc25-dd5c2744d865
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661217906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1661217906
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4258123134
Short name T603
Test name
Test status
Simulation time 98080623 ps
CPU time 2.97 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:30 PM PDT 24
Peak memory 198520 kb
Host smart-c19b24ef-1c8b-4f74-953d-84a2a9c10c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258123134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4258123134
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3989646425
Short name T253
Test name
Test status
Simulation time 40056274 ps
CPU time 0.69 seconds
Started Aug 04 04:37:27 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 195868 kb
Host smart-a1aaf40d-4ba4-4aca-912c-565fd8d38b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989646425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3989646425
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2079317060
Short name T452
Test name
Test status
Simulation time 23221235 ps
CPU time 0.71 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 196524 kb
Host smart-2ad7b192-4ad5-4aac-bcc2-d19eeb0e059a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079317060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2079317060
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2115465825
Short name T241
Test name
Test status
Simulation time 332861567 ps
CPU time 4.02 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:44 PM PDT 24
Peak memory 198500 kb
Host smart-6ae87879-a4b4-457a-a4ab-8e8ec5f8d2bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115465825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2115465825
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1450654559
Short name T570
Test name
Test status
Simulation time 64998852 ps
CPU time 0.94 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:35 PM PDT 24
Peak memory 196976 kb
Host smart-3bd3e5ae-42b8-458e-8e29-d56108c5ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450654559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1450654559
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.133013744
Short name T65
Test name
Test status
Simulation time 152415461 ps
CPU time 1.21 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 196152 kb
Host smart-7cc93739-83f1-4071-9704-c2b6a7af382a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133013744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.133013744
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.153414786
Short name T632
Test name
Test status
Simulation time 123796925416 ps
CPU time 138.75 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:39:56 PM PDT 24
Peak memory 198792 kb
Host smart-8132e126-6595-4ccb-b5b3-010e06bba2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153414786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.153414786
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3386304672
Short name T57
Test name
Test status
Simulation time 31253536467 ps
CPU time 270.08 seconds
Started Aug 04 04:37:23 PM PDT 24
Finished Aug 04 04:41:53 PM PDT 24
Peak memory 199052 kb
Host smart-9f2c5a29-ea5d-4090-a81c-69c8e90b7935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3386304672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3386304672
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.814541148
Short name T501
Test name
Test status
Simulation time 17912813 ps
CPU time 0.59 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 195112 kb
Host smart-eb44ac74-3168-45a8-a57e-0b9802bc583b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814541148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.814541148
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2617430869
Short name T514
Test name
Test status
Simulation time 15796359 ps
CPU time 0.62 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 195104 kb
Host smart-de60753c-8db5-49d0-a2a5-5ccd9546b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617430869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2617430869
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2277951595
Short name T255
Test name
Test status
Simulation time 529483013 ps
CPU time 13.97 seconds
Started Aug 04 04:37:42 PM PDT 24
Finished Aug 04 04:37:56 PM PDT 24
Peak memory 198476 kb
Host smart-a67652a5-6f3f-414b-928c-9c86ae6f1ed4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277951595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2277951595
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1518634221
Short name T20
Test name
Test status
Simulation time 201386105 ps
CPU time 0.77 seconds
Started Aug 04 04:37:30 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 196372 kb
Host smart-c5838183-aa73-41f1-a1a6-22a12b1f631c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518634221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1518634221
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1218407847
Short name T134
Test name
Test status
Simulation time 732182171 ps
CPU time 1.09 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 197372 kb
Host smart-2675cbac-e153-40ce-b9b5-fe7dae830ee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218407847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1218407847
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.296140019
Short name T461
Test name
Test status
Simulation time 88333574 ps
CPU time 3.46 seconds
Started Aug 04 04:37:42 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 198648 kb
Host smart-5ed60b34-abb0-4a67-aec2-fb83afae46bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296140019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.296140019
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3753753772
Short name T626
Test name
Test status
Simulation time 1513769455 ps
CPU time 2.41 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 197528 kb
Host smart-80421265-d9b7-48c3-a1dc-359119b0406d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753753772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3753753772
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2424143657
Short name T371
Test name
Test status
Simulation time 86047381 ps
CPU time 0.78 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 196004 kb
Host smart-a9cd65dd-ceb1-4497-86f5-800456153a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424143657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2424143657
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2466263745
Short name T672
Test name
Test status
Simulation time 46140778 ps
CPU time 0.8 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 196684 kb
Host smart-c99a53d9-b4aa-4221-b5cb-10c48fcca4e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466263745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2466263745
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2750536938
Short name T50
Test name
Test status
Simulation time 664822899 ps
CPU time 5.37 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 198420 kb
Host smart-56602452-edb8-4930-bb41-2d88e0488766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750536938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2750536938
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2440526283
Short name T462
Test name
Test status
Simulation time 233265246 ps
CPU time 1.06 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 196208 kb
Host smart-14fe584e-0f46-49c0-9c5a-d7f781f7a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440526283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2440526283
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.720889233
Short name T641
Test name
Test status
Simulation time 81119173 ps
CPU time 1.17 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 197316 kb
Host smart-0c826c21-eaf7-47bd-b6dc-de78d2575dbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720889233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.720889233
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2127897827
Short name T7
Test name
Test status
Simulation time 13350681195 ps
CPU time 148.05 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:40:00 PM PDT 24
Peak memory 198628 kb
Host smart-44229e91-08f6-4736-9205-3effb667438f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127897827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2127897827
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1013732615
Short name T38
Test name
Test status
Simulation time 12419045 ps
CPU time 0.57 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 194408 kb
Host smart-e853e647-db26-4d16-858d-a38c27a5130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013732615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1013732615
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.699678662
Short name T122
Test name
Test status
Simulation time 59075561 ps
CPU time 0.7 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 195612 kb
Host smart-994e0561-693a-41a3-83cc-11d74d84f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699678662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.699678662
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3886059004
Short name T141
Test name
Test status
Simulation time 831222473 ps
CPU time 12.12 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:52 PM PDT 24
Peak memory 197372 kb
Host smart-0f6a437b-b8ee-4dcb-af63-64d188f2446b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886059004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3886059004
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1146121168
Short name T291
Test name
Test status
Simulation time 92099164 ps
CPU time 0.69 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 195168 kb
Host smart-ccc9c237-007c-48ac-9afc-dfed9c3b5ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146121168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1146121168
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1367819966
Short name T167
Test name
Test status
Simulation time 47254646 ps
CPU time 0.88 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:31 PM PDT 24
Peak memory 197152 kb
Host smart-6bfa18af-5eff-44f2-9a54-c9b8cef207a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367819966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1367819966
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3841204529
Short name T660
Test name
Test status
Simulation time 642472708 ps
CPU time 2.7 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:49 PM PDT 24
Peak memory 198424 kb
Host smart-7c50d03a-647e-4a71-8293-a9609e6d9024
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841204529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3841204529
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4051258044
Short name T436
Test name
Test status
Simulation time 565337105 ps
CPU time 2.96 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 198532 kb
Host smart-24614f51-4ee4-4370-9171-a116ba7d9bff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051258044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4051258044
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1693367177
Short name T237
Test name
Test status
Simulation time 36902156 ps
CPU time 0.88 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 196296 kb
Host smart-53baf06a-58f7-4ed6-90ba-5abe92684a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693367177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1693367177
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2926816211
Short name T348
Test name
Test status
Simulation time 37208029 ps
CPU time 0.9 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196352 kb
Host smart-ac3bc1d8-7183-40a3-b031-8bcc04c56f61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926816211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2926816211
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2949361581
Short name T500
Test name
Test status
Simulation time 96859050 ps
CPU time 3.7 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 198400 kb
Host smart-9c979bb2-11c4-4e6b-8ed1-81134ed6c900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949361581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2949361581
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.315810389
Short name T430
Test name
Test status
Simulation time 89966126 ps
CPU time 0.85 seconds
Started Aug 04 04:37:52 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 196280 kb
Host smart-a6e9d9e8-33d6-4be2-80af-e60f398b3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315810389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.315810389
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2566514821
Short name T11
Test name
Test status
Simulation time 673866308 ps
CPU time 1.18 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 198460 kb
Host smart-38712f93-7d34-41b6-900a-1e5997a6457a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566514821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2566514821
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1215754379
Short name T658
Test name
Test status
Simulation time 21813567540 ps
CPU time 73.96 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:38:48 PM PDT 24
Peak memory 198688 kb
Host smart-a186e488-31df-446c-9b75-c8810184ca81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215754379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1215754379
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3644889481
Short name T265
Test name
Test status
Simulation time 36234585 ps
CPU time 0.54 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 194364 kb
Host smart-328f823d-586a-44e0-9888-9f7c84fd8f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644889481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3644889481
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.19575545
Short name T634
Test name
Test status
Simulation time 37867172 ps
CPU time 0.91 seconds
Started Aug 04 04:37:42 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 195892 kb
Host smart-456a04c9-6dc1-42da-bc10-fb5642c6948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19575545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.19575545
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1823833122
Short name T534
Test name
Test status
Simulation time 415160615 ps
CPU time 11.08 seconds
Started Aug 04 04:37:29 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 196124 kb
Host smart-7ffc945e-7691-41d3-bcda-0fd629e67dfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823833122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1823833122
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2713581528
Short name T643
Test name
Test status
Simulation time 840185881 ps
CPU time 0.99 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 197008 kb
Host smart-55f94b50-50de-420b-802d-376946b83aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713581528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2713581528
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.223213858
Short name T667
Test name
Test status
Simulation time 190105853 ps
CPU time 0.8 seconds
Started Aug 04 04:37:33 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 196652 kb
Host smart-b089439a-d5c6-4fef-9932-a59e99fb0e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223213858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.223213858
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3644130310
Short name T285
Test name
Test status
Simulation time 102230566 ps
CPU time 3.05 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:48 PM PDT 24
Peak memory 198668 kb
Host smart-a832492b-b83a-41ee-9af0-5013f97f618b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644130310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3644130310
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3710170521
Short name T300
Test name
Test status
Simulation time 1163312753 ps
CPU time 2.64 seconds
Started Aug 04 04:38:03 PM PDT 24
Finished Aug 04 04:38:06 PM PDT 24
Peak memory 196952 kb
Host smart-d9491502-c205-432c-a1e2-69fc9a6fd7ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710170521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3710170521
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3302633129
Short name T407
Test name
Test status
Simulation time 80182623 ps
CPU time 0.95 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196516 kb
Host smart-580eb093-420d-46bd-8370-691f9980e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302633129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3302633129
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2478681982
Short name T556
Test name
Test status
Simulation time 27496456 ps
CPU time 0.98 seconds
Started Aug 04 04:37:49 PM PDT 24
Finished Aug 04 04:37:50 PM PDT 24
Peak memory 196320 kb
Host smart-876987c4-c6b0-456e-8b07-cfb7d12e4072
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478681982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2478681982
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_smoke.3314201549
Short name T411
Test name
Test status
Simulation time 76546682 ps
CPU time 0.99 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 197056 kb
Host smart-c615ff95-4181-45db-a88c-80d3af3b5312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314201549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3314201549
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2009365397
Short name T425
Test name
Test status
Simulation time 41553708 ps
CPU time 1.05 seconds
Started Aug 04 04:37:52 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 196208 kb
Host smart-4e2357fa-7823-4a82-95b6-6fa805408ce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009365397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2009365397
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3092511087
Short name T669
Test name
Test status
Simulation time 14254812633 ps
CPU time 158.28 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:40:16 PM PDT 24
Peak memory 198600 kb
Host smart-5874286e-2855-436f-b141-8e7f0e8b2720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092511087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3092511087
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3225159544
Short name T28
Test name
Test status
Simulation time 165180025586 ps
CPU time 583.2 seconds
Started Aug 04 04:37:44 PM PDT 24
Finished Aug 04 04:47:28 PM PDT 24
Peak memory 198776 kb
Host smart-298ce055-e37a-4645-b275-3acd311849e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3225159544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3225159544
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1288171621
Short name T268
Test name
Test status
Simulation time 56729798 ps
CPU time 0.56 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 194516 kb
Host smart-5901f997-e3fa-45c4-b18a-5773b382cbb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288171621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1288171621
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2435160013
Short name T136
Test name
Test status
Simulation time 193019862 ps
CPU time 0.78 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 196448 kb
Host smart-f9f80394-beb1-47d6-9d0c-bf7c850981d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435160013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2435160013
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1312411804
Short name T679
Test name
Test status
Simulation time 286380399 ps
CPU time 14.23 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 198432 kb
Host smart-a4847411-0e70-4f06-b8f7-84e4f0216886
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312411804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1312411804
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.552255985
Short name T565
Test name
Test status
Simulation time 76618619 ps
CPU time 0.91 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 196800 kb
Host smart-3154acc3-f671-4c7a-b127-c768155337d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552255985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.552255985
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4073945574
Short name T200
Test name
Test status
Simulation time 94269650 ps
CPU time 1.4 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 197692 kb
Host smart-6b0df98d-c96a-4a11-b832-e92ebfdb31b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073945574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4073945574
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3081454399
Short name T433
Test name
Test status
Simulation time 105269806 ps
CPU time 1.93 seconds
Started Aug 04 04:37:52 PM PDT 24
Finished Aug 04 04:37:54 PM PDT 24
Peak memory 196876 kb
Host smart-21a609ae-3ae7-4545-8574-4e8c5bff3d7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081454399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3081454399
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.863471816
Short name T510
Test name
Test status
Simulation time 132604009 ps
CPU time 2.87 seconds
Started Aug 04 04:37:43 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 198536 kb
Host smart-e28e1b4b-c44a-4dcb-b106-95ccf88b3a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863471816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
863471816
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.688599683
Short name T375
Test name
Test status
Simulation time 105078198 ps
CPU time 1.02 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196400 kb
Host smart-28e6f0e3-705f-46bd-a6cd-0d9c75519597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688599683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.688599683
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1551938631
Short name T617
Test name
Test status
Simulation time 83869549 ps
CPU time 0.81 seconds
Started Aug 04 04:38:04 PM PDT 24
Finished Aug 04 04:38:05 PM PDT 24
Peak memory 196964 kb
Host smart-9f7578a9-dec5-4b61-9c1f-27b2c9adc5d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551938631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1551938631
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4049866131
Short name T464
Test name
Test status
Simulation time 108025408 ps
CPU time 1.05 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 196984 kb
Host smart-5d6fabef-780a-4671-a491-5e2d90ab948a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049866131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4049866131
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.884926335
Short name T393
Test name
Test status
Simulation time 75242136 ps
CPU time 1.18 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 198432 kb
Host smart-4c679901-54ac-4aa6-a094-912f2ba151e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884926335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.884926335
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3607444416
Short name T590
Test name
Test status
Simulation time 264904014 ps
CPU time 1.05 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:37 PM PDT 24
Peak memory 196660 kb
Host smart-0cd0c8c1-d324-4aae-a830-a6c4f3a359ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607444416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3607444416
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1292107188
Short name T438
Test name
Test status
Simulation time 123791576947 ps
CPU time 117.37 seconds
Started Aug 04 04:37:52 PM PDT 24
Finished Aug 04 04:39:50 PM PDT 24
Peak memory 198620 kb
Host smart-ece018e2-3b4d-4ed0-9da6-74c1fdc6f206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292107188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1292107188
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2088849478
Short name T518
Test name
Test status
Simulation time 62753961 ps
CPU time 0.56 seconds
Started Aug 04 04:37:49 PM PDT 24
Finished Aug 04 04:37:50 PM PDT 24
Peak memory 195052 kb
Host smart-39161654-fa7f-451d-a24f-11fcf4e30b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088849478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2088849478
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1295057382
Short name T666
Test name
Test status
Simulation time 33400788 ps
CPU time 0.84 seconds
Started Aug 04 04:37:48 PM PDT 24
Finished Aug 04 04:37:49 PM PDT 24
Peak memory 195648 kb
Host smart-bf45c80b-1c1c-422f-bcb6-b9d55defa128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295057382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1295057382
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2420751300
Short name T245
Test name
Test status
Simulation time 933160141 ps
CPU time 28.34 seconds
Started Aug 04 04:37:51 PM PDT 24
Finished Aug 04 04:38:20 PM PDT 24
Peak memory 198472 kb
Host smart-2692dde0-4978-46c5-9df3-e9c37ce1c9d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420751300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2420751300
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1321213417
Short name T262
Test name
Test status
Simulation time 66925550 ps
CPU time 0.69 seconds
Started Aug 04 04:37:53 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 195836 kb
Host smart-66531893-cede-4c15-af1c-3f8107aa9fd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321213417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1321213417
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2254924669
Short name T260
Test name
Test status
Simulation time 45771826 ps
CPU time 0.72 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 195888 kb
Host smart-8b6bc886-1783-4375-ae13-f5b717748343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254924669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2254924669
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1870202729
Short name T494
Test name
Test status
Simulation time 80379793 ps
CPU time 1.65 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 198620 kb
Host smart-08e3f4f3-19bb-40d0-a22f-9bf5099b5269
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870202729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1870202729
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3786151568
Short name T389
Test name
Test status
Simulation time 87474087 ps
CPU time 2.47 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 196316 kb
Host smart-2d59483a-5886-45ca-8545-c2ce01fd9364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786151568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3786151568
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3185872692
Short name T413
Test name
Test status
Simulation time 144787678 ps
CPU time 0.92 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 197064 kb
Host smart-75d243d0-3f41-40e8-9860-34a4255078b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185872692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3185872692
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2529239366
Short name T386
Test name
Test status
Simulation time 31181012 ps
CPU time 0.99 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 196368 kb
Host smart-8b71da94-ddb3-4dfb-8829-21c272dacdf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529239366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2529239366
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2149200687
Short name T388
Test name
Test status
Simulation time 332420276 ps
CPU time 3.65 seconds
Started Aug 04 04:38:12 PM PDT 24
Finished Aug 04 04:38:16 PM PDT 24
Peak memory 198504 kb
Host smart-8dd22bf7-f0c6-46fd-9055-67dd00d18c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149200687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2149200687
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3748737810
Short name T636
Test name
Test status
Simulation time 30824388 ps
CPU time 0.7 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 194596 kb
Host smart-acb698a9-cc24-4ff4-9499-f7820dc8ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748737810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3748737810
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.939075881
Short name T439
Test name
Test status
Simulation time 158956031 ps
CPU time 0.83 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 195644 kb
Host smart-f2a23bb3-da8b-4b2f-9a84-a124979924c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939075881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.939075881
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.309202006
Short name T235
Test name
Test status
Simulation time 8416054161 ps
CPU time 108.8 seconds
Started Aug 04 04:37:36 PM PDT 24
Finished Aug 04 04:39:25 PM PDT 24
Peak memory 198704 kb
Host smart-2afccd2f-8ae8-457d-956a-abb0ff435ce8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309202006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.309202006
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3131499849
Short name T428
Test name
Test status
Simulation time 11854226 ps
CPU time 0.54 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 194388 kb
Host smart-a8a35065-10e6-4853-9873-0ca2690b93f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131499849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3131499849
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1674609028
Short name T460
Test name
Test status
Simulation time 20918089 ps
CPU time 0.72 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 196424 kb
Host smart-7fe75ec4-b735-4bd4-9676-4ac441549811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674609028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1674609028
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1245611786
Short name T316
Test name
Test status
Simulation time 2359802623 ps
CPU time 15.85 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:38:01 PM PDT 24
Peak memory 196024 kb
Host smart-100379b9-79f9-4624-bf18-1d40c96a583a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245611786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1245611786
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2689991483
Short name T654
Test name
Test status
Simulation time 82108350 ps
CPU time 1.04 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 196824 kb
Host smart-5a7d94a5-9ced-4124-8b9a-67b80f5bfcbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689991483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2689991483
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4160367751
Short name T661
Test name
Test status
Simulation time 290215904 ps
CPU time 1.22 seconds
Started Aug 04 04:37:34 PM PDT 24
Finished Aug 04 04:37:36 PM PDT 24
Peak memory 197120 kb
Host smart-4d181bad-8c2c-4137-a9f3-cc4d14a59d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160367751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4160367751
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2460881301
Short name T335
Test name
Test status
Simulation time 70446105 ps
CPU time 0.9 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:37:38 PM PDT 24
Peak memory 197400 kb
Host smart-578057f5-87de-4fd4-b847-83fd9405a327
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460881301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2460881301
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.658764124
Short name T607
Test name
Test status
Simulation time 90528841 ps
CPU time 1.26 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 197928 kb
Host smart-946885f1-83aa-4636-ba39-6ede541f125e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658764124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
658764124
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3537095050
Short name T657
Test name
Test status
Simulation time 58320070 ps
CPU time 1.3 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 197416 kb
Host smart-94056b7f-a9a5-44be-9310-fb0b1f2598ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537095050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3537095050
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3308854610
Short name T179
Test name
Test status
Simulation time 112410950 ps
CPU time 0.74 seconds
Started Aug 04 04:37:44 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 195796 kb
Host smart-9d660601-0449-4ff7-8aae-352381c69267
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308854610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3308854610
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3840412654
Short name T505
Test name
Test status
Simulation time 195448289 ps
CPU time 2.41 seconds
Started Aug 04 04:37:31 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 198432 kb
Host smart-f0383fea-f62b-4fb6-97da-ac79600fdf60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840412654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3840412654
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3350508839
Short name T227
Test name
Test status
Simulation time 157245326 ps
CPU time 0.97 seconds
Started Aug 04 04:37:47 PM PDT 24
Finished Aug 04 04:37:48 PM PDT 24
Peak memory 196296 kb
Host smart-7daa115d-6090-491e-b7fc-8a9bd6c91eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350508839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3350508839
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3331636782
Short name T639
Test name
Test status
Simulation time 82919360 ps
CPU time 1.32 seconds
Started Aug 04 04:37:52 PM PDT 24
Finished Aug 04 04:37:53 PM PDT 24
Peak memory 198440 kb
Host smart-505d7e35-47b0-4bb6-99ff-497e4947a720
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331636782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3331636782
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3219415413
Short name T473
Test name
Test status
Simulation time 2982697503 ps
CPU time 41.19 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:38:22 PM PDT 24
Peak memory 198628 kb
Host smart-9b96f3c1-5169-4175-96fb-f5caf7de6491
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219415413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3219415413
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4066864192
Short name T563
Test name
Test status
Simulation time 29884540 ps
CPU time 0.57 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 194600 kb
Host smart-2ddec3b4-f58b-4324-97fe-433af77dbc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066864192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4066864192
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.170242765
Short name T127
Test name
Test status
Simulation time 80308365 ps
CPU time 0.66 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 194440 kb
Host smart-e6a10178-e137-42ee-a82b-d3b915b69c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170242765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.170242765
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.30919561
Short name T247
Test name
Test status
Simulation time 961618048 ps
CPU time 12.39 seconds
Started Aug 04 04:37:56 PM PDT 24
Finished Aug 04 04:38:08 PM PDT 24
Peak memory 197168 kb
Host smart-693c7c1a-68c8-49c9-aa6b-a7fefce013fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress
.30919561
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2859039165
Short name T176
Test name
Test status
Simulation time 80306015 ps
CPU time 0.71 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 195816 kb
Host smart-b1910c89-ab64-449b-9bde-93099875b7db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859039165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2859039165
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3695195737
Short name T427
Test name
Test status
Simulation time 294239031 ps
CPU time 1.43 seconds
Started Aug 04 04:37:43 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 198404 kb
Host smart-80de13a8-932d-4315-90d5-f1e884dc29d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695195737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3695195737
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3727208051
Short name T52
Test name
Test status
Simulation time 84805419 ps
CPU time 1.96 seconds
Started Aug 04 04:37:53 PM PDT 24
Finished Aug 04 04:37:55 PM PDT 24
Peak memory 197512 kb
Host smart-8e81285d-c62f-486a-9b34-917d3e09d354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727208051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3727208051
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2574820218
Short name T64
Test name
Test status
Simulation time 67338691 ps
CPU time 0.72 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 195904 kb
Host smart-aa7c58b5-570b-4f25-9763-838019e1e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574820218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2574820218
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4170051255
Short name T228
Test name
Test status
Simulation time 54722261 ps
CPU time 1.16 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 196336 kb
Host smart-38459dd2-93bb-4edd-a6aa-ac54d66ebe67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170051255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4170051255
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1244880502
Short name T622
Test name
Test status
Simulation time 396031698 ps
CPU time 3.45 seconds
Started Aug 04 04:37:44 PM PDT 24
Finished Aug 04 04:37:48 PM PDT 24
Peak memory 198448 kb
Host smart-17888f76-fcf1-4ad3-8ee1-e8dd50bc638c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244880502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1244880502
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4274889034
Short name T496
Test name
Test status
Simulation time 51381680 ps
CPU time 1.07 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 195988 kb
Host smart-03dfc966-f0cf-4411-9f46-5cddfc32b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274889034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4274889034
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3233889022
Short name T329
Test name
Test status
Simulation time 223024885 ps
CPU time 1.23 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:48 PM PDT 24
Peak memory 196304 kb
Host smart-4de5e3dc-9ca4-4195-9c91-bce9ce77f870
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233889022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3233889022
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1669267104
Short name T592
Test name
Test status
Simulation time 52875817279 ps
CPU time 32.72 seconds
Started Aug 04 04:37:37 PM PDT 24
Finished Aug 04 04:38:10 PM PDT 24
Peak memory 198624 kb
Host smart-74c33634-4e55-4d1f-8e6b-91b254e808c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669267104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1669267104
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.530216849
Short name T589
Test name
Test status
Simulation time 35482164 ps
CPU time 0.59 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 194388 kb
Host smart-31e3a420-8bf9-47ed-8231-ce89ee77f323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530216849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.530216849
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3308892606
Short name T208
Test name
Test status
Simulation time 32469731 ps
CPU time 0.61 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:33 PM PDT 24
Peak memory 194528 kb
Host smart-2cf233a1-b06b-4851-9dd7-b5d1674c4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308892606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3308892606
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.779527108
Short name T14
Test name
Test status
Simulation time 1842353014 ps
CPU time 18.37 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:38:03 PM PDT 24
Peak memory 197224 kb
Host smart-cf0dc952-efda-4316-a1bf-113e4a6e9c7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779527108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.779527108
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4155957286
Short name T331
Test name
Test status
Simulation time 185388901 ps
CPU time 1.08 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 198280 kb
Host smart-3c6c3c88-35c0-4cb3-a1da-6b3ab7408ad6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155957286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4155957286
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3004967827
Short name T541
Test name
Test status
Simulation time 31183273 ps
CPU time 0.74 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 195892 kb
Host smart-8c800f84-45f1-48d0-a1fe-9c1f48dca73e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004967827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3004967827
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2372398938
Short name T380
Test name
Test status
Simulation time 77318904 ps
CPU time 2.77 seconds
Started Aug 04 04:37:42 PM PDT 24
Finished Aug 04 04:37:45 PM PDT 24
Peak memory 198432 kb
Host smart-fd41e689-f6db-4acf-b769-c1cb6b608076
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372398938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2372398938
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1059622411
Short name T166
Test name
Test status
Simulation time 183966695 ps
CPU time 2.81 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:43 PM PDT 24
Peak memory 196372 kb
Host smart-0893ce94-4407-4337-84e2-0ab703b0e1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059622411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1059622411
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.953949534
Short name T250
Test name
Test status
Simulation time 115990401 ps
CPU time 1.08 seconds
Started Aug 04 04:37:40 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 196464 kb
Host smart-a66cd73f-3f8f-4a74-bf37-84f1eb9c711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953949534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.953949534
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3267065832
Short name T653
Test name
Test status
Simulation time 80560232 ps
CPU time 1.14 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 196952 kb
Host smart-bfde0241-0d25-4668-85f5-0a8b8c8282a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267065832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3267065832
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3003449976
Short name T49
Test name
Test status
Simulation time 374609597 ps
CPU time 5.72 seconds
Started Aug 04 04:38:03 PM PDT 24
Finished Aug 04 04:38:09 PM PDT 24
Peak memory 198396 kb
Host smart-34dce30e-4316-46fd-9ae0-f27de8212014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003449976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3003449976
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.632727927
Short name T305
Test name
Test status
Simulation time 257039985 ps
CPU time 1.2 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:41 PM PDT 24
Peak memory 195960 kb
Host smart-a7112111-5260-4930-a7c0-e393a96b28cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632727927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.632727927
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2162272137
Short name T614
Test name
Test status
Simulation time 247704058 ps
CPU time 1.16 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 196232 kb
Host smart-017a4f4e-3840-4281-9547-6b2b75b7920a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162272137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2162272137
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1639632388
Short name T686
Test name
Test status
Simulation time 16224499649 ps
CPU time 87.89 seconds
Started Aug 04 04:37:44 PM PDT 24
Finished Aug 04 04:39:12 PM PDT 24
Peak memory 198724 kb
Host smart-c395c3b8-707a-401f-80e1-5fdfafdde3b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639632388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1639632388
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2704766907
Short name T266
Test name
Test status
Simulation time 25358972 ps
CPU time 0.57 seconds
Started Aug 04 04:37:39 PM PDT 24
Finished Aug 04 04:37:40 PM PDT 24
Peak memory 194568 kb
Host smart-d891f940-3368-4774-a50e-83c3b4150817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704766907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2704766907
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1853646868
Short name T633
Test name
Test status
Simulation time 48291731 ps
CPU time 0.61 seconds
Started Aug 04 04:37:59 PM PDT 24
Finished Aug 04 04:38:00 PM PDT 24
Peak memory 195116 kb
Host smart-cc4fdef2-1125-48ca-b2b1-517139e47e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853646868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1853646868
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1004917066
Short name T442
Test name
Test status
Simulation time 6773257316 ps
CPU time 18.84 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:57 PM PDT 24
Peak memory 197176 kb
Host smart-3a7059f1-d23e-4666-a8c4-272b27f280b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004917066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1004917066
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.626218726
Short name T224
Test name
Test status
Simulation time 40492706 ps
CPU time 0.72 seconds
Started Aug 04 04:37:41 PM PDT 24
Finished Aug 04 04:37:42 PM PDT 24
Peak memory 197056 kb
Host smart-af91eeb3-b1ab-44dc-96de-02d4330c94ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626218726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.626218726
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3288668738
Short name T319
Test name
Test status
Simulation time 54473417 ps
CPU time 0.82 seconds
Started Aug 04 04:37:38 PM PDT 24
Finished Aug 04 04:37:39 PM PDT 24
Peak memory 197148 kb
Host smart-7c109218-2118-4cf0-9e10-572a7290dfc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288668738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3288668738
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1913003953
Short name T674
Test name
Test status
Simulation time 76237848 ps
CPU time 2.94 seconds
Started Aug 04 04:37:46 PM PDT 24
Finished Aug 04 04:37:49 PM PDT 24
Peak memory 198612 kb
Host smart-a73ee1fb-4a21-4259-bcbb-50ad73009d04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913003953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1913003953
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2507808921
Short name T497
Test name
Test status
Simulation time 67247575 ps
CPU time 2.11 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:47 PM PDT 24
Peak memory 197640 kb
Host smart-57b9f3ee-0f00-4c97-8e84-58ceee2866d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507808921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2507808921
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3653513639
Short name T248
Test name
Test status
Simulation time 61987595 ps
CPU time 1.3 seconds
Started Aug 04 04:38:05 PM PDT 24
Finished Aug 04 04:38:06 PM PDT 24
Peak memory 197528 kb
Host smart-e7cdb1fd-147d-472f-8c36-5321c767f22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653513639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3653513639
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.492031784
Short name T422
Test name
Test status
Simulation time 139828273 ps
CPU time 1.09 seconds
Started Aug 04 04:37:45 PM PDT 24
Finished Aug 04 04:37:46 PM PDT 24
Peak memory 196276 kb
Host smart-23e84d28-06ff-437e-9c3c-3713b29b608d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492031784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.492031784
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.697579454
Short name T358
Test name
Test status
Simulation time 164456601 ps
CPU time 1.01 seconds
Started Aug 04 04:37:43 PM PDT 24
Finished Aug 04 04:37:44 PM PDT 24
Peak memory 197008 kb
Host smart-5dc56235-2020-4210-a450-b5fd23d58f57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697579454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.697579454
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.736335526
Short name T71
Test name
Test status
Simulation time 265273159 ps
CPU time 1.17 seconds
Started Aug 04 04:37:32 PM PDT 24
Finished Aug 04 04:37:34 PM PDT 24
Peak memory 196336 kb
Host smart-582136c2-d8bb-4ef7-aa55-b490c0864c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736335526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.736335526
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.526897976
Short name T512
Test name
Test status
Simulation time 42246746 ps
CPU time 0.87 seconds
Started Aug 04 04:37:49 PM PDT 24
Finished Aug 04 04:37:50 PM PDT 24
Peak memory 197644 kb
Host smart-36a0b96c-241f-4596-b40c-c9f520ca727f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526897976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.526897976
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.517223747
Short name T8
Test name
Test status
Simulation time 59224705090 ps
CPU time 154.34 seconds
Started Aug 04 04:37:55 PM PDT 24
Finished Aug 04 04:40:30 PM PDT 24
Peak memory 198692 kb
Host smart-e6d719be-87db-4517-865d-c21a59830769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517223747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.517223747
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3745382222
Short name T595
Test name
Test status
Simulation time 185943512596 ps
CPU time 962.16 seconds
Started Aug 04 04:37:35 PM PDT 24
Finished Aug 04 04:53:37 PM PDT 24
Peak memory 198808 kb
Host smart-33d1f62e-1747-460d-b3d5-d3238bef5ac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3745382222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3745382222
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3172094387
Short name T492
Test name
Test status
Simulation time 66855673 ps
CPU time 0.55 seconds
Started Aug 04 04:36:49 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 195244 kb
Host smart-76e01f4d-b657-4127-9992-3e98c7a4b70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172094387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3172094387
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.619863418
Short name T151
Test name
Test status
Simulation time 91954713 ps
CPU time 0.82 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 197040 kb
Host smart-29c36320-1396-435a-884a-a1d28c4c8fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619863418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.619863418
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2340881078
Short name T576
Test name
Test status
Simulation time 960036788 ps
CPU time 6.4 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 197316 kb
Host smart-e8a02fe5-65a4-462a-9e5c-8344e4c7ea05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340881078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2340881078
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.708054797
Short name T395
Test name
Test status
Simulation time 53369924 ps
CPU time 0.83 seconds
Started Aug 04 04:36:32 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 196476 kb
Host smart-3252baed-7c27-43bc-85c0-dae6992be807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708054797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.708054797
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.10279406
Short name T594
Test name
Test status
Simulation time 82173205 ps
CPU time 1.08 seconds
Started Aug 04 04:36:57 PM PDT 24
Finished Aug 04 04:36:58 PM PDT 24
Peak memory 196508 kb
Host smart-63cc4560-eb8f-4f3a-a063-3db2d61af4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.10279406
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3916304954
Short name T502
Test name
Test status
Simulation time 79703663 ps
CPU time 1.01 seconds
Started Aug 04 04:36:41 PM PDT 24
Finished Aug 04 04:36:42 PM PDT 24
Peak memory 197592 kb
Host smart-d309a04f-a4eb-4a38-8cac-73206e738b3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916304954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3916304954
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2857648530
Short name T226
Test name
Test status
Simulation time 122947355 ps
CPU time 2.3 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 197692 kb
Host smart-7d76db99-1328-4c5f-b372-0f5df1100c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857648530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2857648530
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.4114684123
Short name T74
Test name
Test status
Simulation time 28607691 ps
CPU time 0.82 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 195988 kb
Host smart-17b23533-2b2a-497d-bdf0-261e22a7c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114684123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.4114684123
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1640372653
Short name T313
Test name
Test status
Simulation time 24428662 ps
CPU time 0.61 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 194744 kb
Host smart-78cd5074-0aba-4922-819c-fb862cb01260
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640372653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1640372653
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1937247218
Short name T440
Test name
Test status
Simulation time 503348719 ps
CPU time 4.13 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 198532 kb
Host smart-3944e0ac-1534-4d95-8a9f-004524e93511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937247218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1937247218
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4288627946
Short name T242
Test name
Test status
Simulation time 73322600 ps
CPU time 0.72 seconds
Started Aug 04 04:37:03 PM PDT 24
Finished Aug 04 04:37:04 PM PDT 24
Peak memory 195756 kb
Host smart-fe058584-60a8-44c4-8d22-7ded4f66e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288627946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4288627946
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3324576338
Short name T197
Test name
Test status
Simulation time 122918719 ps
CPU time 1.09 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 196180 kb
Host smart-ff3f80d0-275f-4674-bcf0-710b5ef458c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324576338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3324576338
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2522027945
Short name T232
Test name
Test status
Simulation time 7439586079 ps
CPU time 181.23 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:39:46 PM PDT 24
Peak memory 198696 kb
Host smart-9440dd76-8321-43d5-886e-0f46e254f55b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522027945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2522027945
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1057657455
Short name T175
Test name
Test status
Simulation time 12260174 ps
CPU time 0.59 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 195064 kb
Host smart-cbcb5d3b-ad44-4f9c-9f2f-a5e96c20cbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057657455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1057657455
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3081797622
Short name T546
Test name
Test status
Simulation time 73117460 ps
CPU time 0.84 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 196988 kb
Host smart-e799ad0c-9a9d-4cf4-98f2-a55ff3dd62fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081797622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3081797622
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.377184970
Short name T450
Test name
Test status
Simulation time 420563009 ps
CPU time 18.45 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:37:05 PM PDT 24
Peak memory 197612 kb
Host smart-69227912-d791-4026-9406-58b63c0fa74f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377184970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.377184970
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2991060509
Short name T195
Test name
Test status
Simulation time 74573022 ps
CPU time 0.6 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 194812 kb
Host smart-459f98b1-cffd-44d8-952b-ed17db67901e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991060509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2991060509
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3719757708
Short name T535
Test name
Test status
Simulation time 45552574 ps
CPU time 0.79 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 197076 kb
Host smart-a447a3d2-91b7-448e-a4ef-d679d9d2651d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719757708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3719757708
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.953785454
Short name T315
Test name
Test status
Simulation time 940452486 ps
CPU time 2.57 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 196912 kb
Host smart-81aeda2f-bed8-41d1-abb2-2df75b3a8aad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953785454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.953785454
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1276897692
Short name T17
Test name
Test status
Simulation time 249241651 ps
CPU time 2.65 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 198576 kb
Host smart-c6701fd7-844e-438c-bd07-ccf8b943d1e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276897692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1276897692
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1392803749
Short name T287
Test name
Test status
Simulation time 47459845 ps
CPU time 0.66 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 195620 kb
Host smart-ea57533d-607e-4278-9dc1-d8e1721a91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392803749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1392803749
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3171531429
Short name T545
Test name
Test status
Simulation time 77066280 ps
CPU time 0.91 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 197188 kb
Host smart-dbcf786c-55fb-4a10-9bcb-72eaab2b446b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171531429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3171531429
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.179510699
Short name T694
Test name
Test status
Simulation time 388847812 ps
CPU time 5.08 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 198432 kb
Host smart-b5e842e6-57fb-4144-bee7-3df2bf273afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179510699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.179510699
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.4050639087
Short name T217
Test name
Test status
Simulation time 337281222 ps
CPU time 1.42 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 198460 kb
Host smart-4c33c170-65e2-4903-a53e-05d7344ffe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050639087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.4050639087
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.752573650
Short name T618
Test name
Test status
Simulation time 67716743 ps
CPU time 0.79 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 195736 kb
Host smart-4a26ad92-7ee0-400a-b30e-3d29a28e853f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752573650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.752573650
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2042231107
Short name T495
Test name
Test status
Simulation time 8822108913 ps
CPU time 101.14 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:38:19 PM PDT 24
Peak memory 198676 kb
Host smart-fafbb396-583e-479c-bf89-efc1703eb47d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042231107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2042231107
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2033912879
Short name T409
Test name
Test status
Simulation time 47792437 ps
CPU time 0.57 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 194708 kb
Host smart-fa64bb0b-0094-4bf5-aaa0-ecab7baf3dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033912879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2033912879
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.520096845
Short name T453
Test name
Test status
Simulation time 25283523 ps
CPU time 0.66 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 194580 kb
Host smart-16151544-c847-40a6-99e1-3c02adfc5a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520096845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.520096845
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2270135246
Short name T298
Test name
Test status
Simulation time 1280839825 ps
CPU time 15.86 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:52 PM PDT 24
Peak memory 197332 kb
Host smart-3b10ebf4-9f04-4b78-9853-1c66654284db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270135246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2270135246
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.609804409
Short name T367
Test name
Test status
Simulation time 38168904 ps
CPU time 0.74 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 196236 kb
Host smart-92dced96-f950-46c3-a364-82f39714fe2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609804409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.609804409
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4035367842
Short name T148
Test name
Test status
Simulation time 251472434 ps
CPU time 1.07 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196504 kb
Host smart-093f4f83-1caa-40c8-8ceb-60a7cdc877af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035367842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4035367842
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2533956396
Short name T524
Test name
Test status
Simulation time 100496103 ps
CPU time 2.05 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 198584 kb
Host smart-b74b6e2f-cf58-44ac-8ff4-6f9c2500a472
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533956396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2533956396
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1530107512
Short name T223
Test name
Test status
Simulation time 432721739 ps
CPU time 3.07 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 197608 kb
Host smart-b3be0bc8-93e3-46e9-a233-b19d5f6808e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530107512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1530107512
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1386195947
Short name T378
Test name
Test status
Simulation time 37505625 ps
CPU time 1.2 seconds
Started Aug 04 04:36:48 PM PDT 24
Finished Aug 04 04:36:50 PM PDT 24
Peak memory 197616 kb
Host smart-027f894b-ba7c-41c5-b735-5fb24a27906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386195947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1386195947
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3055472268
Short name T138
Test name
Test status
Simulation time 128217860 ps
CPU time 0.65 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:45 PM PDT 24
Peak memory 194656 kb
Host smart-e8f1734c-6ec1-4662-8fbe-fbae1b4b27c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055472268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3055472268
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2836714483
Short name T536
Test name
Test status
Simulation time 1357786207 ps
CPU time 4.07 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 198400 kb
Host smart-2eb6a5f0-8f23-4cba-87d6-018324a90ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836714483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2836714483
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1193618877
Short name T424
Test name
Test status
Simulation time 373114867 ps
CPU time 0.85 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:49 PM PDT 24
Peak memory 196784 kb
Host smart-f6f1abf2-e65b-4598-bd30-0fac4285956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193618877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1193618877
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.292744764
Short name T572
Test name
Test status
Simulation time 35458373 ps
CPU time 1.07 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 196288 kb
Host smart-075f8ed0-2026-456c-80bf-ba1f17198c4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292744764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.292744764
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1742976611
Short name T4
Test name
Test status
Simulation time 5802505461 ps
CPU time 63.13 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:37:51 PM PDT 24
Peak memory 198564 kb
Host smart-d3c652b5-04b7-40b7-9b8c-1f00ccfcb9e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742976611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1742976611
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.196165592
Short name T557
Test name
Test status
Simulation time 55258009813 ps
CPU time 1572.61 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 05:02:54 PM PDT 24
Peak memory 198740 kb
Host smart-c22e314b-e45f-4d42-91bb-70383fa31b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=196165592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.196165592
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4020890619
Short name T682
Test name
Test status
Simulation time 23676158 ps
CPU time 0.54 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:43 PM PDT 24
Peak memory 195100 kb
Host smart-d8e72e15-06f9-47c9-aba1-361c5e70eff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020890619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4020890619
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.485883021
Short name T585
Test name
Test status
Simulation time 162616215 ps
CPU time 0.93 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196212 kb
Host smart-12080136-2b8f-4eb6-9638-644bfb8d148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485883021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.485883021
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.357162933
Short name T186
Test name
Test status
Simulation time 1611026553 ps
CPU time 27.34 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:37:21 PM PDT 24
Peak memory 197412 kb
Host smart-a30b0172-f0e4-490b-b2dc-6d1f6424cdf7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357162933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.357162933
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3462377572
Short name T568
Test name
Test status
Simulation time 214014711 ps
CPU time 0.85 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 197580 kb
Host smart-ed730e95-824b-4048-ac6c-e0d53644ba2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462377572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3462377572
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1284305568
Short name T406
Test name
Test status
Simulation time 71497169 ps
CPU time 0.72 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 195980 kb
Host smart-2f68ecc4-574d-4a75-a4ce-87ce97de06e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284305568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1284305568
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.29933811
Short name T216
Test name
Test status
Simulation time 1088353535 ps
CPU time 2.7 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 197004 kb
Host smart-17a0bfbe-3477-47fb-9ea1-2591ddf024aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.gpio_intr_with_filter_rand_intr_event.29933811
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3021416567
Short name T185
Test name
Test status
Simulation time 124360767 ps
CPU time 3.38 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 198472 kb
Host smart-4e4043a0-873d-4992-b5b2-fce44197d5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021416567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3021416567
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4249128297
Short name T509
Test name
Test status
Simulation time 81145062 ps
CPU time 0.66 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 195444 kb
Host smart-895be2bb-4ccf-4fd1-98dc-bd21cc26af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249128297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4249128297
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2765220743
Short name T170
Test name
Test status
Simulation time 37834750 ps
CPU time 0.99 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 196536 kb
Host smart-f3f65992-b9ae-4718-93db-d461a15b152e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765220743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2765220743
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3544129860
Short name T481
Test name
Test status
Simulation time 116153674 ps
CPU time 4.89 seconds
Started Aug 04 04:36:42 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 198492 kb
Host smart-b3422f42-2655-46e8-8a94-2c644d55aca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544129860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3544129860
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1864385075
Short name T484
Test name
Test status
Simulation time 69774579 ps
CPU time 0.88 seconds
Started Aug 04 04:36:55 PM PDT 24
Finished Aug 04 04:36:56 PM PDT 24
Peak memory 197560 kb
Host smart-bf02ef3f-e2a1-438e-a218-dd0fed34e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864385075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1864385075
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3520964815
Short name T272
Test name
Test status
Simulation time 127565910 ps
CPU time 1.12 seconds
Started Aug 04 04:36:57 PM PDT 24
Finished Aug 04 04:36:58 PM PDT 24
Peak memory 196280 kb
Host smart-4adabca6-bae9-4e07-8ad7-6ca32882f217
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520964815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3520964815
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4094762778
Short name T360
Test name
Test status
Simulation time 79195391016 ps
CPU time 187.1 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:39:47 PM PDT 24
Peak memory 198620 kb
Host smart-d05bfafe-9e0b-4ee3-bb44-5d73db2bf8e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094762778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4094762778
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2430610853
Short name T434
Test name
Test status
Simulation time 30498424 ps
CPU time 0.58 seconds
Started Aug 04 04:36:45 PM PDT 24
Finished Aug 04 04:36:46 PM PDT 24
Peak memory 194324 kb
Host smart-3aff1e38-2f57-449e-afbe-cf3fd3d333b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430610853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2430610853
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.697165142
Short name T292
Test name
Test status
Simulation time 17444383 ps
CPU time 0.62 seconds
Started Aug 04 04:36:36 PM PDT 24
Finished Aug 04 04:36:37 PM PDT 24
Peak memory 194348 kb
Host smart-efa8ff2a-4257-4dae-93de-0cef5cca3220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697165142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.697165142
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3157731998
Short name T651
Test name
Test status
Simulation time 2432567687 ps
CPU time 16.47 seconds
Started Aug 04 04:36:49 PM PDT 24
Finished Aug 04 04:37:06 PM PDT 24
Peak memory 197648 kb
Host smart-b8fcad87-10e5-4ac4-8bfa-4c246a60c438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157731998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3157731998
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2698972301
Short name T598
Test name
Test status
Simulation time 150967002 ps
CPU time 0.94 seconds
Started Aug 04 04:36:57 PM PDT 24
Finished Aug 04 04:36:58 PM PDT 24
Peak memory 197056 kb
Host smart-9cc5d195-cf43-455c-8e88-c8e3b97fd0eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698972301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2698972301
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1778314646
Short name T516
Test name
Test status
Simulation time 104887624 ps
CPU time 1.4 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:47 PM PDT 24
Peak memory 198480 kb
Host smart-b994173b-f941-48ef-9415-96f7b8fbd266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778314646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1778314646
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1451229773
Short name T705
Test name
Test status
Simulation time 24802290 ps
CPU time 0.97 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 197388 kb
Host smart-1639b0ec-8fc4-428f-8822-42ef2de16aca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451229773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1451229773
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1064192090
Short name T267
Test name
Test status
Simulation time 675558917 ps
CPU time 3.01 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 197780 kb
Host smart-b948a4ce-07b0-47dd-8f97-dc17cab32282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064192090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1064192090
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.476026325
Short name T205
Test name
Test status
Simulation time 29375363 ps
CPU time 0.96 seconds
Started Aug 04 04:36:39 PM PDT 24
Finished Aug 04 04:36:41 PM PDT 24
Peak memory 197236 kb
Host smart-d4c108a2-faa4-4708-b8eb-dbd67850bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476026325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.476026325
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.935395662
Short name T366
Test name
Test status
Simulation time 57741126 ps
CPU time 1.07 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 196472 kb
Host smart-5d974757-82d8-4352-95fe-8f4d08e34a6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935395662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.935395662
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3199222039
Short name T670
Test name
Test status
Simulation time 158025441 ps
CPU time 1.57 seconds
Started Aug 04 04:36:38 PM PDT 24
Finished Aug 04 04:36:40 PM PDT 24
Peak memory 198232 kb
Host smart-fe5a00ec-c974-4e61-84d2-6f6d877b40ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199222039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3199222039
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1972122587
Short name T490
Test name
Test status
Simulation time 73888106 ps
CPU time 1.2 seconds
Started Aug 04 04:36:46 PM PDT 24
Finished Aug 04 04:36:48 PM PDT 24
Peak memory 196192 kb
Host smart-7ca22bd5-04f8-4d53-8d33-f2b5656480ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972122587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1972122587
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1337126505
Short name T172
Test name
Test status
Simulation time 29682514 ps
CPU time 0.89 seconds
Started Aug 04 04:36:43 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 197388 kb
Host smart-ea93e08a-484f-4b88-9a7e-5a41590e032a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337126505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1337126505
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2444761668
Short name T648
Test name
Test status
Simulation time 33365450014 ps
CPU time 100.57 seconds
Started Aug 04 04:36:54 PM PDT 24
Finished Aug 04 04:38:34 PM PDT 24
Peak memory 198780 kb
Host smart-af198144-5c06-4e9c-a350-f32eb73f2bd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444761668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2444761668
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.561654438
Short name T914
Test name
Test status
Simulation time 332700201 ps
CPU time 1.28 seconds
Started Aug 04 04:24:08 PM PDT 24
Finished Aug 04 04:24:09 PM PDT 24
Peak memory 196560 kb
Host smart-2bbd2804-6475-4835-a74c-bc0e755b2ca6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=561654438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.561654438
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3499718893
Short name T865
Test name
Test status
Simulation time 236927911 ps
CPU time 1.09 seconds
Started Aug 04 04:20:43 PM PDT 24
Finished Aug 04 04:20:44 PM PDT 24
Peak memory 196424 kb
Host smart-b5c03feb-8f35-4b18-a33b-c2a3c3518dbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499718893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3499718893
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2813394946
Short name T930
Test name
Test status
Simulation time 174947369 ps
CPU time 0.89 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 195828 kb
Host smart-4a4b5019-5e7c-48cf-a6d0-8e857758e186
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2813394946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2813394946
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3892546332
Short name T838
Test name
Test status
Simulation time 59639300 ps
CPU time 1.09 seconds
Started Aug 04 04:24:14 PM PDT 24
Finished Aug 04 04:24:15 PM PDT 24
Peak memory 197860 kb
Host smart-4996448e-b410-4eef-9ae2-5eeffa3abdcb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892546332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3892546332
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1459624191
Short name T911
Test name
Test status
Simulation time 164884453 ps
CPU time 1.49 seconds
Started Aug 04 04:24:10 PM PDT 24
Finished Aug 04 04:24:12 PM PDT 24
Peak memory 197768 kb
Host smart-f1c7a0b1-147c-475e-8733-de2706d02011
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1459624191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1459624191
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751662286
Short name T917
Test name
Test status
Simulation time 32421549 ps
CPU time 0.89 seconds
Started Aug 04 04:23:55 PM PDT 24
Finished Aug 04 04:23:56 PM PDT 24
Peak memory 195376 kb
Host smart-537e3d97-fc4c-4372-9cab-9c07e44eb846
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751662286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3751662286
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1659752185
Short name T913
Test name
Test status
Simulation time 72605433 ps
CPU time 1.03 seconds
Started Aug 04 04:21:26 PM PDT 24
Finished Aug 04 04:21:27 PM PDT 24
Peak memory 195772 kb
Host smart-ef70926f-31b8-4792-956e-c72d3ab80018
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1659752185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1659752185
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3645201804
Short name T878
Test name
Test status
Simulation time 199565928 ps
CPU time 1.03 seconds
Started Aug 04 04:22:43 PM PDT 24
Finished Aug 04 04:22:44 PM PDT 24
Peak memory 196848 kb
Host smart-0d3f44ef-9579-4ae4-9678-4987b89f88e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645201804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3645201804
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2327346350
Short name T849
Test name
Test status
Simulation time 147694044 ps
CPU time 0.98 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 195436 kb
Host smart-37a01042-81e3-4f1f-8eb6-93a640f1c708
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2327346350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2327346350
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1429308603
Short name T893
Test name
Test status
Simulation time 129805822 ps
CPU time 0.92 seconds
Started Aug 04 04:23:57 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 195124 kb
Host smart-e4161b12-a94a-416b-9186-58c2902c773a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429308603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1429308603
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.245856157
Short name T866
Test name
Test status
Simulation time 134907605 ps
CPU time 1.11 seconds
Started Aug 04 04:23:56 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 195448 kb
Host smart-c56aadb1-5994-40f9-be8f-0f7a2ecd1796
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=245856157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.245856157
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3005526055
Short name T837
Test name
Test status
Simulation time 579344238 ps
CPU time 1.14 seconds
Started Aug 04 04:23:57 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 194928 kb
Host smart-967c1d43-1a20-4596-939d-0fbe8a3593a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005526055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3005526055
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3575582164
Short name T845
Test name
Test status
Simulation time 40480095 ps
CPU time 1.18 seconds
Started Aug 04 04:24:14 PM PDT 24
Finished Aug 04 04:24:16 PM PDT 24
Peak memory 196200 kb
Host smart-301b17e7-bdf3-411a-afd9-d06addaeedd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3575582164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3575582164
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735300632
Short name T863
Test name
Test status
Simulation time 895105021 ps
CPU time 1.35 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:01 PM PDT 24
Peak memory 196796 kb
Host smart-7ed3bccb-4c63-4551-9c9f-2eb461115d12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735300632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.735300632
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2004186200
Short name T931
Test name
Test status
Simulation time 117602335 ps
CPU time 0.94 seconds
Started Aug 04 04:23:57 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 195968 kb
Host smart-57d3ce04-98ea-4088-9b96-e5d685b32a19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2004186200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2004186200
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.300806215
Short name T928
Test name
Test status
Simulation time 50547396 ps
CPU time 1 seconds
Started Aug 04 04:24:12 PM PDT 24
Finished Aug 04 04:24:13 PM PDT 24
Peak memory 197020 kb
Host smart-a23f0d57-c749-4e0e-9dcd-a1734fbdbf23
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300806215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.300806215
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3528464001
Short name T874
Test name
Test status
Simulation time 97976506 ps
CPU time 0.98 seconds
Started Aug 04 04:22:10 PM PDT 24
Finished Aug 04 04:22:11 PM PDT 24
Peak memory 196916 kb
Host smart-5e135881-4af4-42fc-912f-156ad3704c32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3528464001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3528464001
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3983176933
Short name T844
Test name
Test status
Simulation time 208805690 ps
CPU time 0.96 seconds
Started Aug 04 04:24:13 PM PDT 24
Finished Aug 04 04:24:14 PM PDT 24
Peak memory 196172 kb
Host smart-b761e9b9-fe83-494f-ac3d-9f0506abc055
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983176933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3983176933
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2557581276
Short name T935
Test name
Test status
Simulation time 325915277 ps
CPU time 1.24 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 197580 kb
Host smart-c7d1405f-c166-45f4-a25f-f0bebc859520
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2557581276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2557581276
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2939038979
Short name T924
Test name
Test status
Simulation time 568102738 ps
CPU time 0.95 seconds
Started Aug 04 04:23:57 PM PDT 24
Finished Aug 04 04:23:58 PM PDT 24
Peak memory 194716 kb
Host smart-3edd0d6b-dace-4554-8f5e-dfc15bfa00fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939038979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2939038979
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2088811989
Short name T887
Test name
Test status
Simulation time 562888966 ps
CPU time 1.34 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 197744 kb
Host smart-5065403f-1d10-4244-986c-d5a2f719eca4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088811989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2088811989
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2932676782
Short name T873
Test name
Test status
Simulation time 198193111 ps
CPU time 0.76 seconds
Started Aug 04 04:25:59 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 194984 kb
Host smart-a0c9d470-6a00-4b1a-b09b-33c81a87d91c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932676782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2932676782
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1842618739
Short name T855
Test name
Test status
Simulation time 27177318 ps
CPU time 0.7 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 194148 kb
Host smart-cd4efc0f-f0dd-464a-85b0-a0e0065baf23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1842618739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1842618739
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2276743182
Short name T900
Test name
Test status
Simulation time 32486231 ps
CPU time 0.9 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 196280 kb
Host smart-1dba64e4-c0e8-4fef-9363-86cf4f201623
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276743182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2276743182
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2887260135
Short name T851
Test name
Test status
Simulation time 56289630 ps
CPU time 0.99 seconds
Started Aug 04 04:26:05 PM PDT 24
Finished Aug 04 04:26:06 PM PDT 24
Peak memory 191372 kb
Host smart-da6ac2bb-b882-4a67-bc95-b838348efcd9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2887260135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2887260135
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193827263
Short name T881
Test name
Test status
Simulation time 88786050 ps
CPU time 0.85 seconds
Started Aug 04 04:23:58 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 195376 kb
Host smart-c946e93d-cc37-4b8d-a23e-16f6705758c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193827263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3193827263
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2674619260
Short name T927
Test name
Test status
Simulation time 47779540 ps
CPU time 0.98 seconds
Started Aug 04 04:23:05 PM PDT 24
Finished Aug 04 04:23:06 PM PDT 24
Peak memory 197200 kb
Host smart-ecd7f7ff-4a89-4162-8c75-9101dab33e16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2674619260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2674619260
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1097201602
Short name T885
Test name
Test status
Simulation time 230615341 ps
CPU time 1.08 seconds
Started Aug 04 04:25:43 PM PDT 24
Finished Aug 04 04:25:44 PM PDT 24
Peak memory 197844 kb
Host smart-24cd2306-9ab7-4507-a5e2-1073f2182577
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097201602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1097201602
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2912882739
Short name T868
Test name
Test status
Simulation time 557155373 ps
CPU time 1.08 seconds
Started Aug 04 04:23:18 PM PDT 24
Finished Aug 04 04:23:20 PM PDT 24
Peak memory 197876 kb
Host smart-f1b23453-bf2a-4192-a61f-934a3ce00a0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2912882739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2912882739
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855713571
Short name T933
Test name
Test status
Simulation time 45996281 ps
CPU time 0.93 seconds
Started Aug 04 04:23:19 PM PDT 24
Finished Aug 04 04:23:20 PM PDT 24
Peak memory 196260 kb
Host smart-62986448-1aee-4322-8b16-59a2d8d40ce3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855713571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2855713571
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.398223407
Short name T847
Test name
Test status
Simulation time 173636028 ps
CPU time 1.58 seconds
Started Aug 04 04:22:03 PM PDT 24
Finished Aug 04 04:22:04 PM PDT 24
Peak memory 196596 kb
Host smart-d452da82-2b1c-49ba-8706-99e3a1168368
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=398223407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.398223407
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2202305015
Short name T859
Test name
Test status
Simulation time 413107773 ps
CPU time 0.87 seconds
Started Aug 04 04:23:27 PM PDT 24
Finished Aug 04 04:23:28 PM PDT 24
Peak memory 197648 kb
Host smart-922771e3-1742-48b7-a4d7-8e5cc4f905e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202305015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2202305015
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1387150661
Short name T895
Test name
Test status
Simulation time 248357893 ps
CPU time 1.18 seconds
Started Aug 04 04:20:56 PM PDT 24
Finished Aug 04 04:20:58 PM PDT 24
Peak memory 197716 kb
Host smart-6251785f-2147-43ba-a478-9d13fdb333d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1387150661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1387150661
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3120255539
Short name T836
Test name
Test status
Simulation time 177562746 ps
CPU time 0.95 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 196344 kb
Host smart-de0e98dc-124b-4636-bd67-7e6ccccb5ca5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120255539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3120255539
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1623213568
Short name T916
Test name
Test status
Simulation time 71519863 ps
CPU time 1.13 seconds
Started Aug 04 04:25:55 PM PDT 24
Finished Aug 04 04:25:56 PM PDT 24
Peak memory 197740 kb
Host smart-3ace6ed1-5bb3-4624-b850-55d39659bb4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1623213568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1623213568
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541467265
Short name T840
Test name
Test status
Simulation time 33246533 ps
CPU time 0.94 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 197312 kb
Host smart-e679474d-ff06-4ed4-8982-500f3bd3396f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541467265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3541467265
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2685938780
Short name T891
Test name
Test status
Simulation time 108882093 ps
CPU time 1.03 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 195740 kb
Host smart-e390b1f9-4b48-4f85-a26c-03a56f657b88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2685938780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2685938780
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716844102
Short name T909
Test name
Test status
Simulation time 230506820 ps
CPU time 1.21 seconds
Started Aug 04 04:22:11 PM PDT 24
Finished Aug 04 04:22:13 PM PDT 24
Peak memory 195684 kb
Host smart-99ddf4fb-2b84-43df-98eb-22f39a1561c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716844102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.716844102
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3043892731
Short name T908
Test name
Test status
Simulation time 42495053 ps
CPU time 1.12 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:36 PM PDT 24
Peak memory 196420 kb
Host smart-c64855b3-8253-4231-9c2e-86d16bdbde6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3043892731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3043892731
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1098081
Short name T853
Test name
Test status
Simulation time 291160411 ps
CPU time 0.9 seconds
Started Aug 04 04:26:04 PM PDT 24
Finished Aug 04 04:26:05 PM PDT 24
Peak memory 196012 kb
Host smart-5204ce0f-b396-4c15-9405-ab4d36a1ccf7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.1098081
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1172399890
Short name T869
Test name
Test status
Simulation time 158293104 ps
CPU time 1.19 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 197876 kb
Host smart-ad514e24-1538-4cb9-b380-93645a084632
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1172399890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1172399890
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111500754
Short name T848
Test name
Test status
Simulation time 77025156 ps
CPU time 1 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 196412 kb
Host smart-131f8e8c-6f59-4533-ac20-a7bade83364a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111500754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1111500754
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2506278725
Short name T856
Test name
Test status
Simulation time 25749891 ps
CPU time 0.91 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 195268 kb
Host smart-27a9e6dc-b6e0-45d0-aaa4-1f2c487ed156
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2506278725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2506278725
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667769389
Short name T905
Test name
Test status
Simulation time 52685125 ps
CPU time 1.12 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 196408 kb
Host smart-a0e0a7be-5a05-4726-927f-a2c9ef3c64c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667769389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2667769389
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4275340352
Short name T864
Test name
Test status
Simulation time 196868145 ps
CPU time 1.09 seconds
Started Aug 04 04:25:19 PM PDT 24
Finished Aug 04 04:25:21 PM PDT 24
Peak memory 195384 kb
Host smart-44e92fc4-b377-49a4-978e-fde022561dba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4275340352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4275340352
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292253080
Short name T889
Test name
Test status
Simulation time 147467690 ps
CPU time 1.28 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 196784 kb
Host smart-fb5fc217-be5e-4aec-b625-b7c6ecd25aa0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292253080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2292253080
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3414202373
Short name T906
Test name
Test status
Simulation time 432477472 ps
CPU time 1.02 seconds
Started Aug 04 04:23:52 PM PDT 24
Finished Aug 04 04:23:53 PM PDT 24
Peak memory 195236 kb
Host smart-05c244b9-49e9-4eec-8c2e-7b386df55253
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3414202373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3414202373
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.307327709
Short name T872
Test name
Test status
Simulation time 148121258 ps
CPU time 1.04 seconds
Started Aug 04 04:24:07 PM PDT 24
Finished Aug 04 04:24:08 PM PDT 24
Peak memory 196388 kb
Host smart-3dc5ef5b-9f6d-4005-abbc-0a4685a4da9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307327709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.307327709
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3567670683
Short name T894
Test name
Test status
Simulation time 185996801 ps
CPU time 0.91 seconds
Started Aug 04 04:23:52 PM PDT 24
Finished Aug 04 04:23:53 PM PDT 24
Peak memory 196248 kb
Host smart-9b9ed770-9ed9-42b5-930c-39302272c142
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3567670683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3567670683
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3405572105
Short name T860
Test name
Test status
Simulation time 82876833 ps
CPU time 1.35 seconds
Started Aug 04 04:23:10 PM PDT 24
Finished Aug 04 04:23:11 PM PDT 24
Peak memory 197852 kb
Host smart-d82811fe-c8c1-45bb-9846-5d93b8d466a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405572105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3405572105
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3581737752
Short name T882
Test name
Test status
Simulation time 58215395 ps
CPU time 0.77 seconds
Started Aug 04 04:22:08 PM PDT 24
Finished Aug 04 04:22:09 PM PDT 24
Peak memory 195252 kb
Host smart-d9bb1524-b4a6-4e67-9e00-9b77aad4d9c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3581737752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3581737752
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399180785
Short name T925
Test name
Test status
Simulation time 81786572 ps
CPU time 0.86 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:48 PM PDT 24
Peak memory 195292 kb
Host smart-c62cb17f-0e0b-472d-b122-5b59a7be04eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399180785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1399180785
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.663186866
Short name T852
Test name
Test status
Simulation time 67219767 ps
CPU time 1.21 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 195048 kb
Host smart-e4373e18-6011-4dd0-8f3f-a6453befbf4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=663186866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.663186866
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.687771938
Short name T858
Test name
Test status
Simulation time 158406484 ps
CPU time 0.89 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:48 PM PDT 24
Peak memory 195280 kb
Host smart-7378c050-e1b4-43c4-96f1-e1c682f53d93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687771938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.687771938
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.955797167
Short name T854
Test name
Test status
Simulation time 89798577 ps
CPU time 1.3 seconds
Started Aug 04 04:25:21 PM PDT 24
Finished Aug 04 04:25:23 PM PDT 24
Peak memory 195616 kb
Host smart-fc338b78-dd37-436e-a08e-c9724e57b569
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=955797167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.955797167
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3819890636
Short name T870
Test name
Test status
Simulation time 26194198 ps
CPU time 0.74 seconds
Started Aug 04 04:25:48 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 194096 kb
Host smart-53161cba-ae12-4da5-a9f6-369184828ae3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819890636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3819890636
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.777785530
Short name T921
Test name
Test status
Simulation time 25708414 ps
CPU time 0.8 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 195212 kb
Host smart-b68c7a59-d228-467e-b1f9-f7b930505d71
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=777785530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.777785530
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3927373497
Short name T929
Test name
Test status
Simulation time 361696075 ps
CPU time 1.01 seconds
Started Aug 04 04:23:31 PM PDT 24
Finished Aug 04 04:23:32 PM PDT 24
Peak memory 196584 kb
Host smart-95babc32-59a8-414e-95c7-099b2b847ac6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927373497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3927373497
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3679618867
Short name T876
Test name
Test status
Simulation time 94842872 ps
CPU time 0.9 seconds
Started Aug 04 04:26:00 PM PDT 24
Finished Aug 04 04:26:01 PM PDT 24
Peak memory 196192 kb
Host smart-8fcf5165-9695-492e-8b42-5032ab88d0da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3679618867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3679618867
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2601556283
Short name T846
Test name
Test status
Simulation time 39048363 ps
CPU time 0.86 seconds
Started Aug 04 04:21:16 PM PDT 24
Finished Aug 04 04:21:17 PM PDT 24
Peak memory 195160 kb
Host smart-0107ced9-361e-410a-a4d9-22ac221b1f61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601556283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2601556283
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1138793216
Short name T901
Test name
Test status
Simulation time 55568602 ps
CPU time 0.92 seconds
Started Aug 04 04:23:03 PM PDT 24
Finished Aug 04 04:23:04 PM PDT 24
Peak memory 196928 kb
Host smart-08b08f6c-5382-493d-8bbd-300f59c8c450
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1138793216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1138793216
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2844659160
Short name T879
Test name
Test status
Simulation time 32180438 ps
CPU time 0.9 seconds
Started Aug 04 04:25:57 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 196404 kb
Host smart-adc2d9db-a098-4db0-8544-f63a6060c135
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844659160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2844659160
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2231010559
Short name T907
Test name
Test status
Simulation time 339008055 ps
CPU time 1.08 seconds
Started Aug 04 04:25:21 PM PDT 24
Finished Aug 04 04:25:23 PM PDT 24
Peak memory 195464 kb
Host smart-1de7dc9a-c148-485e-919a-5d490de5948b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2231010559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2231010559
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2794784153
Short name T910
Test name
Test status
Simulation time 30241274 ps
CPU time 0.95 seconds
Started Aug 04 04:21:31 PM PDT 24
Finished Aug 04 04:21:32 PM PDT 24
Peak memory 196752 kb
Host smart-e2ab3377-8548-477e-b87d-cbbb42256d18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794784153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2794784153
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.754909933
Short name T842
Test name
Test status
Simulation time 56749766 ps
CPU time 1.35 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 197828 kb
Host smart-849c61e8-fac9-4cfe-95a7-f85eac86a9fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=754909933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.754909933
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471875589
Short name T904
Test name
Test status
Simulation time 340657072 ps
CPU time 1.34 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:01 PM PDT 24
Peak memory 196484 kb
Host smart-7611e38e-177b-4b67-b70a-de03f859473f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471875589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3471875589
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2978237837
Short name T877
Test name
Test status
Simulation time 82010295 ps
CPU time 1.29 seconds
Started Aug 04 04:24:05 PM PDT 24
Finished Aug 04 04:24:06 PM PDT 24
Peak memory 195888 kb
Host smart-dbfd647b-38f4-480f-b35c-585ff59c3a33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978237837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2978237837
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2255197879
Short name T883
Test name
Test status
Simulation time 184985553 ps
CPU time 1.28 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194836 kb
Host smart-99e98b95-c9db-4a32-b36f-3be5d4bd632c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255197879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2255197879
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1748113574
Short name T861
Test name
Test status
Simulation time 26768189 ps
CPU time 0.95 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 197784 kb
Host smart-e70455f9-e30c-4c64-84c3-e3bc4d77e05b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1748113574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1748113574
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.63800624
Short name T867
Test name
Test status
Simulation time 148819712 ps
CPU time 1.33 seconds
Started Aug 04 04:24:10 PM PDT 24
Finished Aug 04 04:24:11 PM PDT 24
Peak memory 196812 kb
Host smart-50241c80-abce-4d04-a46d-9fe03fa8f1e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63800624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.63800624
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1923046606
Short name T875
Test name
Test status
Simulation time 87014851 ps
CPU time 1.39 seconds
Started Aug 04 04:21:18 PM PDT 24
Finished Aug 04 04:21:20 PM PDT 24
Peak memory 197856 kb
Host smart-2a851628-5f8a-471a-8417-c666f2e00774
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1923046606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1923046606
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376701833
Short name T857
Test name
Test status
Simulation time 43513208 ps
CPU time 1.19 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:43 PM PDT 24
Peak memory 195688 kb
Host smart-6ef25b08-54b7-4107-b4b0-c4e7ec5ab2af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376701833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2376701833
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1109934309
Short name T892
Test name
Test status
Simulation time 51613221 ps
CPU time 0.96 seconds
Started Aug 04 04:21:36 PM PDT 24
Finished Aug 04 04:21:37 PM PDT 24
Peak memory 195664 kb
Host smart-f16a371f-5722-49e7-9670-67a5032bb30d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1109934309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1109934309
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3815905948
Short name T850
Test name
Test status
Simulation time 42453821 ps
CPU time 1.07 seconds
Started Aug 04 04:22:02 PM PDT 24
Finished Aug 04 04:22:03 PM PDT 24
Peak memory 198256 kb
Host smart-719edcae-34ca-4e3a-87cb-5ef275ae6960
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815905948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3815905948
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.716818809
Short name T915
Test name
Test status
Simulation time 32936446 ps
CPU time 0.91 seconds
Started Aug 04 04:21:30 PM PDT 24
Finished Aug 04 04:21:31 PM PDT 24
Peak memory 197532 kb
Host smart-597a87b7-b7f8-46a5-8340-6af8a49c8776
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=716818809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.716818809
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2686802813
Short name T843
Test name
Test status
Simulation time 37753054 ps
CPU time 1.17 seconds
Started Aug 04 04:22:11 PM PDT 24
Finished Aug 04 04:22:12 PM PDT 24
Peak memory 197852 kb
Host smart-8254e8eb-3361-458d-b32e-830cba7a43ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686802813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2686802813
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2484013800
Short name T919
Test name
Test status
Simulation time 155054157 ps
CPU time 1.06 seconds
Started Aug 04 04:23:53 PM PDT 24
Finished Aug 04 04:23:54 PM PDT 24
Peak memory 195260 kb
Host smart-f6b7a348-3303-4104-bc7d-7679c1dc378f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2484013800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2484013800
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852578563
Short name T898
Test name
Test status
Simulation time 36261595 ps
CPU time 1.1 seconds
Started Aug 04 04:21:51 PM PDT 24
Finished Aug 04 04:21:52 PM PDT 24
Peak memory 196548 kb
Host smart-c766fac5-0c92-454d-ae7b-60c6d0f624b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852578563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.852578563
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1108933321
Short name T871
Test name
Test status
Simulation time 63680305 ps
CPU time 0.87 seconds
Started Aug 04 04:23:53 PM PDT 24
Finished Aug 04 04:23:54 PM PDT 24
Peak memory 193824 kb
Host smart-a991ce83-645a-4109-ae57-a80f56c3bcf1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1108933321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1108933321
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2996334868
Short name T918
Test name
Test status
Simulation time 88541448 ps
CPU time 1.36 seconds
Started Aug 04 04:20:53 PM PDT 24
Finished Aug 04 04:20:54 PM PDT 24
Peak memory 195500 kb
Host smart-ce801009-353d-4396-91ce-b58490ae16d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996334868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2996334868
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.380321987
Short name T886
Test name
Test status
Simulation time 224947818 ps
CPU time 1.22 seconds
Started Aug 04 04:22:52 PM PDT 24
Finished Aug 04 04:22:54 PM PDT 24
Peak memory 197888 kb
Host smart-7de6878a-c4d7-4f66-abee-ec266cf4eb08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=380321987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.380321987
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1251601309
Short name T884
Test name
Test status
Simulation time 77325739 ps
CPU time 1.21 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 195604 kb
Host smart-6d7ddac8-ba1d-4ea3-8342-58853126290d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251601309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1251601309
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.745409274
Short name T923
Test name
Test status
Simulation time 250328780 ps
CPU time 1.17 seconds
Started Aug 04 04:22:12 PM PDT 24
Finished Aug 04 04:22:14 PM PDT 24
Peak memory 196524 kb
Host smart-8091fcac-4780-41fb-bb35-5b1331196797
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=745409274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.745409274
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3804039389
Short name T899
Test name
Test status
Simulation time 279653925 ps
CPU time 1.15 seconds
Started Aug 04 04:25:54 PM PDT 24
Finished Aug 04 04:25:55 PM PDT 24
Peak memory 196440 kb
Host smart-55049ea2-5ec2-41b8-8411-ef9fc8c20fed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804039389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3804039389
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3266860406
Short name T920
Test name
Test status
Simulation time 264092258 ps
CPU time 1.12 seconds
Started Aug 04 04:24:06 PM PDT 24
Finished Aug 04 04:24:07 PM PDT 24
Peak memory 195880 kb
Host smart-40f6273a-695e-413a-84fa-84c391cb0f4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3266860406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3266860406
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497322024
Short name T903
Test name
Test status
Simulation time 69217043 ps
CPU time 1.07 seconds
Started Aug 04 04:23:23 PM PDT 24
Finished Aug 04 04:23:25 PM PDT 24
Peak memory 196480 kb
Host smart-619ef4fe-0774-4f38-b4a8-cb901d5bad09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497322024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2497322024
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1528067339
Short name T912
Test name
Test status
Simulation time 299751446 ps
CPU time 1.35 seconds
Started Aug 04 04:23:13 PM PDT 24
Finished Aug 04 04:23:15 PM PDT 24
Peak memory 197760 kb
Host smart-dd3f2f94-446f-49e9-a1ac-d6b3d1f2b09e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1528067339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1528067339
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.641788383
Short name T922
Test name
Test status
Simulation time 104669056 ps
CPU time 1.28 seconds
Started Aug 04 04:22:45 PM PDT 24
Finished Aug 04 04:22:46 PM PDT 24
Peak memory 197504 kb
Host smart-d1e9eeb4-6356-4f0f-af21-d62f5f8aeb75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641788383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.641788383
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.926630830
Short name T897
Test name
Test status
Simulation time 297057056 ps
CPU time 1.45 seconds
Started Aug 04 04:21:03 PM PDT 24
Finished Aug 04 04:21:05 PM PDT 24
Peak memory 196452 kb
Host smart-ede899f8-ac69-4b15-a49d-a159caecb485
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=926630830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.926630830
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509084733
Short name T896
Test name
Test status
Simulation time 81626041 ps
CPU time 0.87 seconds
Started Aug 04 04:23:27 PM PDT 24
Finished Aug 04 04:23:28 PM PDT 24
Peak memory 196216 kb
Host smart-825bd692-4393-4209-ac00-1681a3445c49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509084733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3509084733
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3909032353
Short name T862
Test name
Test status
Simulation time 65158436 ps
CPU time 1.13 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 195424 kb
Host smart-074a9fe3-96c8-4f5d-953c-21ff2fb77990
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3909032353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3909032353
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1165348865
Short name T839
Test name
Test status
Simulation time 320437811 ps
CPU time 0.85 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:47 PM PDT 24
Peak memory 194964 kb
Host smart-33ad2414-ff27-4de3-852e-e162e56d6189
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165348865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1165348865
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1883357209
Short name T880
Test name
Test status
Simulation time 482695438 ps
CPU time 1.01 seconds
Started Aug 04 04:22:29 PM PDT 24
Finished Aug 04 04:22:30 PM PDT 24
Peak memory 197864 kb
Host smart-9bf72792-94bf-4240-b918-6bc71cb7ef2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1883357209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1883357209
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4281113076
Short name T902
Test name
Test status
Simulation time 54716497 ps
CPU time 0.96 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:48 PM PDT 24
Peak memory 196308 kb
Host smart-466005bf-f2f7-451b-94de-3062c18fd5dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281113076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4281113076
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1213761548
Short name T841
Test name
Test status
Simulation time 424933180 ps
CPU time 1.16 seconds
Started Aug 04 04:24:09 PM PDT 24
Finished Aug 04 04:24:10 PM PDT 24
Peak memory 195572 kb
Host smart-8e08878c-ca51-4ae2-9362-f26bf3399e61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1213761548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1213761548
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1486063447
Short name T932
Test name
Test status
Simulation time 54757151 ps
CPU time 0.92 seconds
Started Aug 04 04:24:14 PM PDT 24
Finished Aug 04 04:24:16 PM PDT 24
Peak memory 196092 kb
Host smart-07e455ca-4826-4ceb-8034-4e77d5bb02d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486063447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1486063447
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3984195489
Short name T890
Test name
Test status
Simulation time 104310683 ps
CPU time 1.33 seconds
Started Aug 04 04:24:09 PM PDT 24
Finished Aug 04 04:24:10 PM PDT 24
Peak memory 196560 kb
Host smart-87c1d154-36f1-4d83-bf5b-92a9e63b5b93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3984195489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3984195489
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3900355219
Short name T934
Test name
Test status
Simulation time 78186766 ps
CPU time 0.89 seconds
Started Aug 04 04:22:13 PM PDT 24
Finished Aug 04 04:22:15 PM PDT 24
Peak memory 195364 kb
Host smart-71b1b3b3-dd1d-40bb-8b41-a52ad7424b5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900355219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3900355219
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3567671983
Short name T926
Test name
Test status
Simulation time 704234732 ps
CPU time 1.28 seconds
Started Aug 04 04:21:51 PM PDT 24
Finished Aug 04 04:21:52 PM PDT 24
Peak memory 197832 kb
Host smart-3d2e5641-859d-493a-8de3-35026b20686c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3567671983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3567671983
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.510777635
Short name T888
Test name
Test status
Simulation time 196555071 ps
CPU time 1.24 seconds
Started Aug 04 04:23:59 PM PDT 24
Finished Aug 04 04:24:00 PM PDT 24
Peak memory 196080 kb
Host smart-9979657e-75bd-4c0e-afd6-996f506f3054
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510777635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.510777635
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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