Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[1]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[2]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[3]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[4]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[5]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[6]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[7]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[8]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[9]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[10]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[11]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[12]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[13]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[14]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[15]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[16]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[17]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[18]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[19]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[20]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[21]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[22]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[23]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[24]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[25]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[26]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[27]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[28]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[29]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[30]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[31]	17735176	1			T32	321992		T33	14861		T34	1187

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320976965

1

T32

519856

T33

475552

T34

19326

auto[1]

246548667

1

T32

510517

T34

18658

T50

19066

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121927703

1

T32

101441

T33

475552

T34

4506

auto[1]

445597929

1

T32

928933

T34

33478

T50

32547

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3047241	1			T32	15833		T33	14861		T34	121
all_values[0]	auto[0]	auto[1]	6979347	1			T32	144173		T34	635		T50	427
all_values[0]	auto[1]	auto[0]	740631	1			T32	14671		T34	54		T50	32
all_values[0]	auto[1]	auto[1]	6967957	1			T32	147315		T34	377		T50	607
all_values[1]	auto[0]	auto[0]	3064762	1			T32	18243		T33	14861		T34	35
all_values[1]	auto[0]	auto[1]	6937915	1			T32	149371		T34	494		T50	469
all_values[1]	auto[1]	auto[0]	752780	1			T32	16333		T34	88		T50	30
all_values[1]	auto[1]	auto[1]	6979719	1			T32	138045		T34	570		T50	598
all_values[2]	auto[0]	auto[0]	3059126	1			T32	17044		T33	14861		T34	61
all_values[2]	auto[0]	auto[1]	6974282	1			T32	142107		T34	638		T50	513
all_values[2]	auto[1]	auto[0]	749292	1			T32	16261		T34	83		T50	76
all_values[2]	auto[1]	auto[1]	6952476	1			T32	146580		T34	405		T50	470
all_values[3]	auto[0]	auto[0]	3070521	1			T32	16156		T33	14861		T34	48
all_values[3]	auto[0]	auto[1]	6959153	1			T32	149601		T34	475		T50	591
all_values[3]	auto[1]	auto[0]	754541	1			T32	15060		T34	74		T50	49
all_values[3]	auto[1]	auto[1]	6950961	1			T32	141175		T34	590		T50	402
all_values[4]	auto[0]	auto[0]	3064282	1			T32	16924		T33	14861		T34	64
all_values[4]	auto[0]	auto[1]	6986269	1			T32	144801		T34	583		T50	525
all_values[4]	auto[1]	auto[0]	746794	1			T32	14667		T34	47		T50	51
all_values[4]	auto[1]	auto[1]	6937831	1			T32	145600		T34	493		T50	513
all_values[5]	auto[0]	auto[0]	3058162	1			T32	16319		T33	14861		T34	68
all_values[5]	auto[0]	auto[1]	7000662	1			T32	145863		T34	605		T50	548
all_values[5]	auto[1]	auto[0]	746701	1			T32	15749		T34	43		T50	74
all_values[5]	auto[1]	auto[1]	6929651	1			T32	144061		T34	471		T50	459
all_values[6]	auto[0]	auto[0]	3060662	1			T32	16976		T33	14861		T34	82
all_values[6]	auto[0]	auto[1]	6974870	1			T32	147638		T34	427		T50	394
all_values[6]	auto[1]	auto[0]	741848	1			T32	15501		T34	61		T50	54
all_values[6]	auto[1]	auto[1]	6957796	1			T32	141877		T34	617		T50	633
all_values[7]	auto[0]	auto[0]	3068283	1			T32	15259		T33	14861		T34	54
all_values[7]	auto[0]	auto[1]	6951096	1			T32	141873		T34	549		T50	482
all_values[7]	auto[1]	auto[0]	744056	1			T32	15758		T34	35		T50	49
all_values[7]	auto[1]	auto[1]	6971741	1			T32	149102		T34	549		T50	504
all_values[8]	auto[0]	auto[0]	3061729	1			T32	16428		T33	14861		T34	55
all_values[8]	auto[0]	auto[1]	7001286	1			T32	142894		T34	624		T50	505
all_values[8]	auto[1]	auto[0]	747793	1			T32	14234		T34	34		T50	37
all_values[8]	auto[1]	auto[1]	6924368	1			T32	148436		T34	474		T50	502
all_values[9]	auto[0]	auto[0]	3068394	1			T32	14933		T33	14861		T34	37
all_values[9]	auto[0]	auto[1]	6947853	1			T32	148687		T34	504		T50	340
all_values[9]	auto[1]	auto[0]	745171	1			T32	14191		T34	60		T50	34
all_values[9]	auto[1]	auto[1]	6973758	1			T32	144181		T34	586		T50	683
all_values[10]	auto[0]	auto[0]	3063199	1			T32	16258		T33	14861		T34	33
all_values[10]	auto[0]	auto[1]	6942870	1			T32	142460		T34	541		T50	556
all_values[10]	auto[1]	auto[0]	747527	1			T32	13919		T34	56		T50	59
all_values[10]	auto[1]	auto[1]	6981580	1			T32	149355		T34	557		T50	477
all_values[11]	auto[0]	auto[0]	3056456	1			T32	18010		T33	14861		T34	72
all_values[11]	auto[0]	auto[1]	6943097	1			T32	148169		T34	613		T50	448
all_values[11]	auto[1]	auto[0]	750445	1			T32	16729		T34	36		T50	64
all_values[11]	auto[1]	auto[1]	6985178	1			T32	139084		T34	466		T50	563
all_values[12]	auto[0]	auto[0]	3056022	1			T32	15948		T33	14861		T34	62
all_values[12]	auto[0]	auto[1]	6994761	1			T32	148763		T34	511		T50	415
all_values[12]	auto[1]	auto[0]	745620	1			T32	15609		T34	54		T50	45
all_values[12]	auto[1]	auto[1]	6938773	1			T32	141672		T34	560		T50	631
all_values[13]	auto[0]	auto[0]	3053208	1			T32	16005		T33	14861		T34	71
all_values[13]	auto[0]	auto[1]	6964409	1			T32	150411		T34	405		T50	436
all_values[13]	auto[1]	auto[0]	745012	1			T32	14011		T34	91		T50	14
all_values[13]	auto[1]	auto[1]	6972547	1			T32	141565		T34	620		T50	633
all_values[14]	auto[0]	auto[0]	3067190	1			T32	15327		T33	14861		T34	64
all_values[14]	auto[0]	auto[1]	6959472	1			T32	139665		T34	552		T50	483
all_values[14]	auto[1]	auto[0]	754073	1			T32	15463		T34	83		T50	64
all_values[14]	auto[1]	auto[1]	6954441	1			T32	151537		T34	488		T50	468
all_values[15]	auto[0]	auto[0]	3058456	1			T32	15974		T33	14861		T34	42
all_values[15]	auto[0]	auto[1]	6958085	1			T32	149156		T34	386		T50	456
all_values[15]	auto[1]	auto[0]	748104	1			T32	17607		T34	85		T50	38
all_values[15]	auto[1]	auto[1]	6970531	1			T32	139255		T34	674		T50	540
all_values[16]	auto[0]	auto[0]	3063532	1			T32	18802		T33	14861		T34	152
all_values[16]	auto[0]	auto[1]	6939155	1			T32	139962		T34	515		T50	278
all_values[16]	auto[1]	auto[0]	742410	1			T32	14138		T34	102		T50	139
all_values[16]	auto[1]	auto[1]	6990079	1			T32	149090		T34	418		T50	670
all_values[17]	auto[0]	auto[0]	3066587	1			T32	17258		T33	14861		T34	85
all_values[17]	auto[0]	auto[1]	6999926	1			T32	145561		T34	649		T50	336
all_values[17]	auto[1]	auto[0]	738250	1			T32	15370		T34	60		T50	54
all_values[17]	auto[1]	auto[1]	6930413	1			T32	143803		T34	393		T50	684
all_values[18]	auto[0]	auto[0]	3066954	1			T32	15763		T33	14861		T34	33
all_values[18]	auto[0]	auto[1]	6968930	1			T32	145786		T34	526		T50	706
all_values[18]	auto[1]	auto[0]	743733	1			T32	14552		T34	93		T50	9
all_values[18]	auto[1]	auto[1]	6955559	1			T32	145891		T34	535		T50	359
all_values[19]	auto[0]	auto[0]	3053870	1			T32	16281		T33	14861		T34	75
all_values[19]	auto[0]	auto[1]	6972856	1			T32	146179		T34	573		T50	524
all_values[19]	auto[1]	auto[0]	747837	1			T32	16129		T34	77		T50	31
all_values[19]	auto[1]	auto[1]	6960613	1			T32	143403		T34	462		T50	482
all_values[20]	auto[0]	auto[0]	3055971	1			T32	15919		T33	14861		T34	81
all_values[20]	auto[0]	auto[1]	6973329	1			T32	152952		T34	488		T50	263
all_values[20]	auto[1]	auto[0]	757257	1			T32	14613		T34	101		T50	48
all_values[20]	auto[1]	auto[1]	6948619	1			T32	138508		T34	517		T50	786
all_values[21]	auto[0]	auto[0]	3056646	1			T32	15182		T33	14861		T34	66
all_values[21]	auto[0]	auto[1]	6964077	1			T32	148540		T34	474		T50	547
all_values[21]	auto[1]	auto[0]	747964	1			T32	15528		T34	64		T50	25
all_values[21]	auto[1]	auto[1]	6966489	1			T32	142742		T34	583		T50	489
all_values[22]	auto[0]	auto[0]	3064756	1			T32	15998		T33	14861		T34	103
all_values[22]	auto[0]	auto[1]	6997831	1			T32	145333		T34	623		T50	320
all_values[22]	auto[1]	auto[0]	761570	1			T32	16576		T34	44		T50	35
all_values[22]	auto[1]	auto[1]	6911019	1			T32	144085		T34	417		T50	710
all_values[23]	auto[0]	auto[0]	3059604	1			T32	16785		T33	14861		T34	50
all_values[23]	auto[0]	auto[1]	6969469	1			T32	142990		T34	580		T50	567
all_values[23]	auto[1]	auto[0]	752473	1			T32	14879		T34	70		T50	46
all_values[23]	auto[1]	auto[1]	6953630	1			T32	147338		T34	487		T50	444
all_values[24]	auto[0]	auto[0]	3060843	1			T32	15190		T33	14861		T34	74
all_values[24]	auto[0]	auto[1]	6977973	1			T32	138098		T34	603		T50	468
all_values[24]	auto[1]	auto[0]	751659	1			T32	15045		T34	112		T50	67
all_values[24]	auto[1]	auto[1]	6944701	1			T32	153659		T34	398		T50	530
all_values[25]	auto[0]	auto[0]	3066232	1			T32	16745		T33	14861		T34	101
all_values[25]	auto[0]	auto[1]	7005049	1			T32	146674		T34	582		T50	485
all_values[25]	auto[1]	auto[0]	745674	1			T32	14148		T34	103		T50	28
all_values[25]	auto[1]	auto[1]	6918221	1			T32	144425		T34	401		T50	508
all_values[26]	auto[0]	auto[0]	3063459	1			T32	16573		T33	14861		T34	49
all_values[26]	auto[0]	auto[1]	6965885	1			T32	152161		T34	509		T50	486
all_values[26]	auto[1]	auto[0]	753098	1			T32	14883		T34	91		T50	46
all_values[26]	auto[1]	auto[1]	6952734	1			T32	138375		T34	538		T50	468
all_values[27]	auto[0]	auto[0]	3051311	1			T32	16462		T33	14861		T34	97
all_values[27]	auto[0]	auto[1]	6954950	1			T32	147387		T34	507		T50	677
all_values[27]	auto[1]	auto[0]	746315	1			T32	14205		T34	154		T50	24
all_values[27]	auto[1]	auto[1]	6982600	1			T32	143938		T34	429		T50	346
all_values[28]	auto[0]	auto[0]	3071983	1			T32	16775		T33	14861		T34	128
all_values[28]	auto[0]	auto[1]	6978496	1			T32	151235		T34	431		T50	554
all_values[28]	auto[1]	auto[0]	752882	1			T32	14420		T34	54		T50	41
all_values[28]	auto[1]	auto[1]	6931815	1			T32	139562		T34	574		T50	458
all_values[29]	auto[0]	auto[0]	3070284	1			T32	17934		T33	14861		T34	64
all_values[29]	auto[0]	auto[1]	6956305	1			T32	145775		T34	537		T50	385
all_values[29]	auto[1]	auto[0]	755336	1			T32	15076		T34	51		T50	68
all_values[29]	auto[1]	auto[1]	6953251	1			T32	143207		T34	535		T50	638
all_values[30]	auto[0]	auto[0]	3064422	1			T32	16646		T33	14861		T34	102
all_values[30]	auto[0]	auto[1]	6946847	1			T32	141211		T34	446		T50	424
all_values[30]	auto[1]	auto[0]	754505	1			T32	15902		T34	59		T50	35
all_values[30]	auto[1]	auto[1]	6969402	1			T32	148233		T34	580		T50	640
all_values[31]	auto[0]	auto[0]	3053588	1			T32	16575		T33	14861		T34	17
all_values[31]	auto[0]	auto[1]	6962725	1			T32	146565		T34	495		T50	368
all_values[31]	auto[1]	auto[0]	748617	1			T32	16658		T34	41		T50	29
all_values[31]	auto[1]	auto[1]	6970246	1			T32	142194		T34	634		T50	676