Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5474272	1			T32	111621		T33	29		T34	449
all_pins[1]	5474272	1			T32	111621		T33	29		T34	449
all_pins[2]	5474272	1			T32	111621		T33	29		T34	449
all_pins[3]	5474272	1			T32	111621		T33	29		T34	449
all_pins[4]	5474272	1			T32	111621		T33	29		T34	449
all_pins[5]	5474272	1			T32	111621		T33	29		T34	449
all_pins[6]	5474272	1			T32	111621		T33	29		T34	449
all_pins[7]	5474272	1			T32	111621		T33	29		T34	449
all_pins[8]	5474272	1			T32	111621		T33	29		T34	449
all_pins[9]	5474272	1			T32	111621		T33	29		T34	449
all_pins[10]	5474272	1			T32	111621		T33	29		T34	449
all_pins[11]	5474272	1			T32	111621		T33	29		T34	449
all_pins[12]	5474272	1			T32	111621		T33	29		T34	449
all_pins[13]	5474272	1			T32	111621		T33	29		T34	449
all_pins[14]	5474272	1			T32	111621		T33	29		T34	449
all_pins[15]	5474272	1			T32	111621		T33	29		T34	449
all_pins[16]	5474272	1			T32	111621		T33	29		T34	449
all_pins[17]	5474272	1			T32	111621		T33	29		T34	449
all_pins[18]	5474272	1			T32	111621		T33	29		T34	449
all_pins[19]	5474272	1			T32	111621		T33	29		T34	449
all_pins[20]	5474272	1			T32	111621		T33	29		T34	449
all_pins[21]	5474272	1			T32	111621		T33	29		T34	449
all_pins[22]	5474272	1			T32	111621		T33	29		T34	449
all_pins[23]	5474272	1			T32	111621		T33	29		T34	449
all_pins[24]	5474272	1			T32	111621		T33	29		T34	449
all_pins[25]	5474272	1			T32	111621		T33	29		T34	449
all_pins[26]	5474272	1			T32	111621		T33	29		T34	449
all_pins[27]	5474272	1			T32	111621		T33	29		T34	449
all_pins[28]	5474272	1			T32	111621		T33	29		T34	449
all_pins[29]	5474272	1			T32	111621		T33	29		T34	449
all_pins[30]	5474272	1			T32	111621		T33	29		T34	449
all_pins[31]	5474272	1			T32	111621		T33	29		T34	449

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	108858533	1			T32	221937		T33	507		T34	8933
values[0x1]	66318171	1			T32	135249		T33	421		T34	5435
transitions[0x0=>0x1]	39757656	1			T32	812303		T33	233		T34	3267
transitions[0x1=>0x0]	39757499	1			T32	812302		T33	233		T34	3266

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3396164	1			T32	69821		T33	16		T34	313
all_pins[0]	values[0x1]	2078108	1			T32	41800		T33	13		T34	136
all_pins[0]	transitions[0x0=>0x1]	1288527	1			T32	25814		T33	9		T34	64
all_pins[0]	transitions[0x1=>0x0]	1280651	1			T32	26921		T33	6		T34	161
all_pins[1]	values[0x0]	3394464	1			T32	70047		T33	19		T34	267
all_pins[1]	values[0x1]	2079808	1			T32	41574		T33	10		T34	182
all_pins[1]	transitions[0x0=>0x1]	1244035	1			T32	25010		T33	4		T34	126
all_pins[1]	transitions[0x1=>0x0]	1242335	1			T32	25236		T33	7		T34	80
all_pins[2]	values[0x0]	3403088	1			T32	68794		T33	16		T34	295
all_pins[2]	values[0x1]	2071184	1			T32	42827		T33	13		T34	154
all_pins[2]	transitions[0x0=>0x1]	1233646	1			T32	26090		T33	8		T34	98
all_pins[2]	transitions[0x1=>0x0]	1242270	1			T32	24837		T33	5		T34	126
all_pins[3]	values[0x0]	3408573	1			T32	69837		T33	16		T34	271
all_pins[3]	values[0x1]	2065699	1			T32	41784		T33	13		T34	178
all_pins[3]	transitions[0x0=>0x1]	1235895	1			T32	24501		T33	7		T34	116
all_pins[3]	transitions[0x1=>0x0]	1241380	1			T32	25544		T33	7		T34	92
all_pins[4]	values[0x0]	3406120	1			T32	69210		T33	13		T34	272
all_pins[4]	values[0x1]	2068152	1			T32	42411		T33	16		T34	177
all_pins[4]	transitions[0x0=>0x1]	1242504	1			T32	25708		T33	8		T34	79
all_pins[4]	transitions[0x1=>0x0]	1240051	1			T32	25081		T33	5		T34	80
all_pins[5]	values[0x0]	3399466	1			T32	68716		T33	13		T34	293
all_pins[5]	values[0x1]	2074806	1			T32	42905		T33	16		T34	156
all_pins[5]	transitions[0x0=>0x1]	1241685	1			T32	25680		T33	8		T34	78
all_pins[5]	transitions[0x1=>0x0]	1235031	1			T32	25186		T33	8		T34	99
all_pins[6]	values[0x0]	3399065	1			T32	68780		T33	18		T34	242
all_pins[6]	values[0x1]	2075207	1			T32	42841		T33	11		T34	207
all_pins[6]	transitions[0x0=>0x1]	1241889	1			T32	25726		T33	3		T34	157
all_pins[6]	transitions[0x1=>0x0]	1241488	1			T32	25790		T33	8		T34	106
all_pins[7]	values[0x0]	3401705	1			T32	68800		T33	18		T34	285
all_pins[7]	values[0x1]	2072567	1			T32	42821		T33	11		T34	164
all_pins[7]	transitions[0x0=>0x1]	1239547	1			T32	25622		T33	6		T34	78
all_pins[7]	transitions[0x1=>0x0]	1242187	1			T32	25642		T33	6		T34	121
all_pins[8]	values[0x0]	3408405	1			T32	68500		T33	18		T34	294
all_pins[8]	values[0x1]	2065867	1			T32	43121		T33	11		T34	155
all_pins[8]	transitions[0x0=>0x1]	1235268	1			T32	25325		T33	8		T34	107
all_pins[8]	transitions[0x1=>0x0]	1241968	1			T32	25025		T33	8		T34	116
all_pins[9]	values[0x0]	3400407	1			T32	69900		T33	21		T34	259
all_pins[9]	values[0x1]	2073865	1			T32	41721		T33	8		T34	190
all_pins[9]	transitions[0x0=>0x1]	1241951	1			T32	24770		T33	7		T34	121
all_pins[9]	transitions[0x1=>0x0]	1233953	1			T32	26170		T33	10		T34	86
all_pins[10]	values[0x0]	3406479	1			T32	69834		T33	18		T34	247
all_pins[10]	values[0x1]	2067793	1			T32	41787		T33	11		T34	202
all_pins[10]	transitions[0x0=>0x1]	1238927	1			T32	25499		T33	7		T34	125
all_pins[10]	transitions[0x1=>0x0]	1244999	1			T32	25433		T33	4		T34	113
all_pins[11]	values[0x0]	3403488	1			T32	70398		T33	22		T34	303
all_pins[11]	values[0x1]	2070784	1			T32	41223		T33	7		T34	146
all_pins[11]	transitions[0x0=>0x1]	1242075	1			T32	24967		T33	4		T34	93
all_pins[11]	transitions[0x1=>0x0]	1239084	1			T32	25531		T33	8		T34	149
all_pins[12]	values[0x0]	3400284	1			T32	68902		T33	10		T34	256
all_pins[12]	values[0x1]	2073988	1			T32	42719		T33	19		T34	193
all_pins[12]	transitions[0x0=>0x1]	1245411	1			T32	26406		T33	14		T34	137
all_pins[12]	transitions[0x1=>0x0]	1242207	1			T32	24910		T33	2		T34	90
all_pins[13]	values[0x0]	3400781	1			T32	69574		T33	18		T34	242
all_pins[13]	values[0x1]	2073491	1			T32	42047		T33	11		T34	207
all_pins[13]	transitions[0x0=>0x1]	1241096	1			T32	24993		T33	6		T34	109
all_pins[13]	transitions[0x1=>0x0]	1241593	1			T32	25665		T33	14		T34	95
all_pins[14]	values[0x0]	3404674	1			T32	67813		T33	14		T34	281
all_pins[14]	values[0x1]	2069598	1			T32	43808		T33	15		T34	168
all_pins[14]	transitions[0x0=>0x1]	1240381	1			T32	26523		T33	8		T34	93
all_pins[14]	transitions[0x1=>0x0]	1244274	1			T32	24762		T33	4		T34	132
all_pins[15]	values[0x0]	3401517	1			T32	69380		T33	12		T34	256
all_pins[15]	values[0x1]	2072755	1			T32	42241		T33	17		T34	193
all_pins[15]	transitions[0x0=>0x1]	1243250	1			T32	24390		T33	9		T34	116
all_pins[15]	transitions[0x1=>0x0]	1240093	1			T32	25957		T33	7		T34	91
all_pins[16]	values[0x0]	3399813	1			T32	69685		T33	18		T34	325
all_pins[16]	values[0x1]	2074459	1			T32	41936		T33	11		T34	124
all_pins[16]	transitions[0x0=>0x1]	1240456	1			T32	25323		T33	7		T34	65
all_pins[16]	transitions[0x1=>0x0]	1238752	1			T32	25628		T33	13		T34	134
all_pins[17]	values[0x0]	3403825	1			T32	69634		T33	15		T34	316
all_pins[17]	values[0x1]	2070447	1			T32	41987		T33	14		T34	133
all_pins[17]	transitions[0x0=>0x1]	1238244	1			T32	25040		T33	6		T34	117
all_pins[17]	transitions[0x1=>0x0]	1242256	1			T32	24989		T33	3		T34	108
all_pins[18]	values[0x0]	3403547	1			T32	69450		T33	13		T34	263
all_pins[18]	values[0x1]	2070725	1			T32	42171		T33	16		T34	186
all_pins[18]	transitions[0x0=>0x1]	1243201	1			T32	25290		T33	9		T34	118
all_pins[18]	transitions[0x1=>0x0]	1242923	1			T32	25106		T33	7		T34	65
all_pins[19]	values[0x0]	3402320	1			T32	69213		T33	16		T34	295
all_pins[19]	values[0x1]	2071952	1			T32	42408		T33	13		T34	154
all_pins[19]	transitions[0x0=>0x1]	1241890	1			T32	25537		T33	6		T34	75
all_pins[19]	transitions[0x1=>0x0]	1240663	1			T32	25300		T33	9		T34	107
all_pins[20]	values[0x0]	3401555	1			T32	70089		T33	14		T34	298
all_pins[20]	values[0x1]	2072717	1			T32	41532		T33	15		T34	151
all_pins[20]	transitions[0x0=>0x1]	1244201	1			T32	25009		T33	10		T34	94
all_pins[20]	transitions[0x1=>0x0]	1243436	1			T32	25885		T33	8		T34	97
all_pins[21]	values[0x0]	3399285	1			T32	69473		T33	18		T34	255
all_pins[21]	values[0x1]	2074987	1			T32	42148		T33	11		T34	194
all_pins[21]	transitions[0x0=>0x1]	1243587	1			T32	25862		T33	3		T34	123
all_pins[21]	transitions[0x1=>0x0]	1241317	1			T32	25246		T33	7		T34	80
all_pins[22]	values[0x0]	3409356	1			T32	69136		T33	20		T34	295
all_pins[22]	values[0x1]	2064916	1			T32	42485		T33	9		T34	154
all_pins[22]	transitions[0x0=>0x1]	1236536	1			T32	25656		T33	5		T34	89
all_pins[22]	transitions[0x1=>0x0]	1246607	1			T32	25319		T33	7		T34	129
all_pins[23]	values[0x0]	3400988	1			T32	69341		T33	19		T34	266
all_pins[23]	values[0x1]	2073284	1			T32	42280		T33	10		T34	183
all_pins[23]	transitions[0x0=>0x1]	1245807	1			T32	25349		T33	8		T34	115
all_pins[23]	transitions[0x1=>0x0]	1237439	1			T32	25554		T33	7		T34	86
all_pins[24]	values[0x0]	3398935	1			T32	68702		T33	21		T34	319
all_pins[24]	values[0x1]	2075337	1			T32	42919		T33	8		T34	130
all_pins[24]	transitions[0x0=>0x1]	1244087	1			T32	25709		T33	7		T34	71
all_pins[24]	transitions[0x1=>0x0]	1242034	1			T32	25070		T33	9		T34	124
all_pins[25]	values[0x0]	3398289	1			T32	70251		T33	8		T34	323
all_pins[25]	values[0x1]	2075983	1			T32	41370		T33	21		T34	126
all_pins[25]	transitions[0x0=>0x1]	1244425	1			T32	24309		T33	15		T34	99
all_pins[25]	transitions[0x1=>0x0]	1243779	1			T32	25858		T33	2		T34	103
all_pins[26]	values[0x0]	3398050	1			T32	69825		T33	11		T34	284
all_pins[26]	values[0x1]	2076222	1			T32	41796		T33	18		T34	165
all_pins[26]	transitions[0x0=>0x1]	1238300	1			T32	25149		T33	5		T34	112
all_pins[26]	transitions[0x1=>0x0]	1238061	1			T32	24723		T33	8		T34	73
all_pins[27]	values[0x0]	3394587	1			T32	68979		T33	14		T34	306
all_pins[27]	values[0x1]	2079685	1			T32	42642		T33	15		T34	143
all_pins[27]	transitions[0x0=>0x1]	1243229	1			T32	25754		T33	7		T34	80
all_pins[27]	transitions[0x1=>0x0]	1239766	1			T32	24908		T33	10		T34	102
all_pins[28]	values[0x0]	3407259	1			T32	70077		T33	17		T34	264
all_pins[28]	values[0x1]	2067013	1			T32	41544		T33	12		T34	185
all_pins[28]	transitions[0x0=>0x1]	1235678	1			T32	24919		T33	8		T34	113
all_pins[28]	transitions[0x1=>0x0]	1248350	1			T32	26017		T33	11		T34	71
all_pins[29]	values[0x0]	3402621	1			T32	70059		T33	10		T34	268
all_pins[29]	values[0x1]	2071651	1			T32	41562		T33	19		T34	181
all_pins[29]	transitions[0x0=>0x1]	1240699	1			T32	25322		T33	13		T34	83
all_pins[29]	transitions[0x1=>0x0]	1236061	1			T32	25304		T33	6		T34	87
all_pins[30]	values[0x0]	3399540	1			T32	68444		T33	12		T34	265
all_pins[30]	values[0x1]	2074732	1			T32	43177		T33	17		T34	184
all_pins[30]	transitions[0x0=>0x1]	1241680	1			T32	25971		T33	3		T34	84
all_pins[30]	transitions[0x1=>0x0]	1238599	1			T32	24356		T33	5		T34	81
all_pins[31]	values[0x0]	3403883	1			T32	68713		T33	19		T34	215
all_pins[31]	values[0x1]	2070389	1			T32	42908		T33	10		T34	234
all_pins[31]	transitions[0x0=>0x1]	1239549	1			T32	25080		T33	5		T34	132
all_pins[31]	transitions[0x1=>0x0]	1243892	1			T32	25349		T33	12		T34	82