Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[1]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[2]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[3]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[4]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[5]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[6]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[7]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[8]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[9]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[10]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[11]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[12]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[13]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[14]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[15]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[16]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[17]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[18]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[19]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[20]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[21]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[22]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[23]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[24]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[25]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[26]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[27]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[28]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[29]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[30]	17735176	1			T32	321992		T33	14861		T34	1187
all_values[31]	17735176	1			T32	321992		T33	14861		T34	1187

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320976965

1

T32

519856

T33

475552

T34

19326

auto[1]

246548667

1

T32

510517

T34

18658

T50

19066

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121927703

1

T32

101441

T33

475552

T34

4506

auto[1]

445597929

1

T32

928933

T34

33478

T50

32547

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

561074442

1

T32

101815

T33

475552

T34

36657

auto[1]

6451190

1

T32

122206

T34

1327

T1

159

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3047241	1			T32	15833		T33	14861		T34	121
all_values[0]	auto[0]	auto[0]	auto[1]	6878056	1			T32	142285		T34	605		T50	427
all_values[0]	auto[0]	auto[1]	auto[0]	740631	1			T32	14671		T34	54		T50	32
all_values[0]	auto[0]	auto[1]	auto[1]	6867608	1			T32	145405		T34	363		T50	607
all_values[0]	auto[1]	auto[0]	auto[1]	101291	1			T32	1888		T34	30		T1	3
all_values[0]	auto[1]	auto[1]	auto[1]	100349	1			T32	1910		T34	14		T1	2
all_values[1]	auto[0]	auto[0]	auto[0]	3064762	1			T32	18243		T33	14861		T34	35
all_values[1]	auto[0]	auto[0]	auto[1]	6836913	1			T32	147451		T34	474		T50	469
all_values[1]	auto[0]	auto[1]	auto[0]	752780	1			T32	16333		T34	88		T50	30
all_values[1]	auto[0]	auto[1]	auto[1]	6878817	1			T32	136172		T34	546		T50	598
all_values[1]	auto[1]	auto[0]	auto[1]	101002	1			T32	1920		T34	20		T1	3
all_values[1]	auto[1]	auto[1]	auto[1]	100902	1			T32	1873		T34	24		T1	1
all_values[2]	auto[0]	auto[0]	auto[0]	3059126	1			T32	17044		T33	14861		T34	61
all_values[2]	auto[0]	auto[0]	auto[1]	6873156	1			T32	140282		T34	611		T50	513
all_values[2]	auto[0]	auto[1]	auto[0]	749292	1			T32	16261		T34	83		T50	76
all_values[2]	auto[0]	auto[1]	auto[1]	6852135	1			T32	144559		T34	386		T50	470
all_values[2]	auto[1]	auto[0]	auto[1]	101126	1			T32	1825		T34	27		T1	2
all_values[2]	auto[1]	auto[1]	auto[1]	100341	1			T32	2021		T34	19		T1	2
all_values[3]	auto[0]	auto[0]	auto[0]	3070521	1			T32	16156		T33	14861		T34	48
all_values[3]	auto[0]	auto[0]	auto[1]	6858219	1			T32	147651		T34	454		T50	591
all_values[3]	auto[0]	auto[1]	auto[0]	754541	1			T32	15060		T34	74		T50	49
all_values[3]	auto[0]	auto[1]	auto[1]	6850757	1			T32	139327		T34	567		T50	402
all_values[3]	auto[1]	auto[0]	auto[1]	100934	1			T32	1950		T34	21		T1	2
all_values[3]	auto[1]	auto[1]	auto[1]	100204	1			T32	1848		T34	23		T1	1
all_values[4]	auto[0]	auto[0]	auto[0]	3064282	1			T32	16924		T33	14861		T34	64
all_values[4]	auto[0]	auto[0]	auto[1]	6885843	1			T32	142926		T34	570		T50	525
all_values[4]	auto[0]	auto[1]	auto[0]	746794	1			T32	14667		T34	47		T50	51
all_values[4]	auto[0]	auto[1]	auto[1]	6836893	1			T32	143610		T34	466		T50	513
all_values[4]	auto[1]	auto[0]	auto[1]	100426	1			T32	1875		T34	13		T1	4
all_values[4]	auto[1]	auto[1]	auto[1]	100938	1			T32	1990		T34	27		T1	2
all_values[5]	auto[0]	auto[0]	auto[0]	3058162	1			T32	16319		T33	14861		T34	68
all_values[5]	auto[0]	auto[0]	auto[1]	6899954	1			T32	143994		T34	580		T50	548
all_values[5]	auto[0]	auto[1]	auto[0]	746701	1			T32	15749		T34	43		T50	74
all_values[5]	auto[0]	auto[1]	auto[1]	6828752	1			T32	142072		T34	455		T50	459
all_values[5]	auto[1]	auto[0]	auto[1]	100708	1			T32	1869		T34	25		T1	2
all_values[5]	auto[1]	auto[1]	auto[1]	100899	1			T32	1989		T34	16		T1	2
all_values[6]	auto[0]	auto[0]	auto[0]	3060662	1			T32	16976		T33	14861		T34	82
all_values[6]	auto[0]	auto[0]	auto[1]	6873419	1			T32	145714		T34	411		T50	394
all_values[6]	auto[0]	auto[1]	auto[0]	741848	1			T32	15501		T34	61		T50	54
all_values[6]	auto[0]	auto[1]	auto[1]	6857333	1			T32	140010		T34	588		T50	633
all_values[6]	auto[1]	auto[0]	auto[1]	101451	1			T32	1924		T34	16		T1	1
all_values[6]	auto[1]	auto[1]	auto[1]	100463	1			T32	1867		T34	29		T1	3
all_values[7]	auto[0]	auto[0]	auto[0]	3068283	1			T32	15259		T33	14861		T34	54
all_values[7]	auto[0]	auto[0]	auto[1]	6850071	1			T32	139958		T34	521		T50	482
all_values[7]	auto[0]	auto[1]	auto[0]	744056	1			T32	15758		T34	35		T50	49
all_values[7]	auto[0]	auto[1]	auto[1]	6870843	1			T32	147151		T34	531		T50	504
all_values[7]	auto[1]	auto[0]	auto[1]	101025	1			T32	1915		T34	28		T1	3
all_values[7]	auto[1]	auto[1]	auto[1]	100898	1			T32	1951		T34	18		T1	1
all_values[8]	auto[0]	auto[0]	auto[0]	3061729	1			T32	16428		T33	14861		T34	55
all_values[8]	auto[0]	auto[0]	auto[1]	6900406	1			T32	141006		T34	596		T50	505
all_values[8]	auto[0]	auto[1]	auto[0]	747793	1			T32	14234		T34	34		T50	37
all_values[8]	auto[0]	auto[1]	auto[1]	6823487	1			T32	146432		T34	463		T50	502
all_values[8]	auto[1]	auto[0]	auto[1]	100880	1			T32	1888		T34	28		T1	2
all_values[8]	auto[1]	auto[1]	auto[1]	100881	1			T32	2004		T34	11		T1	2
all_values[9]	auto[0]	auto[0]	auto[0]	3068394	1			T32	14933		T33	14861		T34	37
all_values[9]	auto[0]	auto[0]	auto[1]	6847347	1			T32	146803		T34	486		T50	340
all_values[9]	auto[0]	auto[1]	auto[0]	745171	1			T32	14191		T34	60		T50	34
all_values[9]	auto[0]	auto[1]	auto[1]	6873235	1			T32	142301		T34	565		T50	683
all_values[9]	auto[1]	auto[0]	auto[1]	100506	1			T32	1884		T34	18		T1	3
all_values[9]	auto[1]	auto[1]	auto[1]	100523	1			T32	1880		T34	21		T17	16
all_values[10]	auto[0]	auto[0]	auto[0]	3063199	1			T32	16258		T33	14861		T34	33
all_values[10]	auto[0]	auto[0]	auto[1]	6841887	1			T32	140553		T34	523		T50	556
all_values[10]	auto[0]	auto[1]	auto[0]	747527	1			T32	13919		T34	56		T50	59
all_values[10]	auto[0]	auto[1]	auto[1]	6881248	1			T32	147453		T34	530		T50	477
all_values[10]	auto[1]	auto[0]	auto[1]	100983	1			T32	1907		T34	18		T1	5
all_values[10]	auto[1]	auto[1]	auto[1]	100332	1			T32	1902		T34	27		T1	2
all_values[11]	auto[0]	auto[0]	auto[0]	3056456	1			T32	18010		T33	14861		T34	72
all_values[11]	auto[0]	auto[0]	auto[1]	6841622	1			T32	146165		T34	587		T50	448
all_values[11]	auto[0]	auto[1]	auto[0]	750445	1			T32	16729		T34	36		T50	64
all_values[11]	auto[0]	auto[1]	auto[1]	6884624	1			T32	137224		T34	444		T50	563
all_values[11]	auto[1]	auto[0]	auto[1]	101475	1			T32	2004		T34	26		T1	2
all_values[11]	auto[1]	auto[1]	auto[1]	100554	1			T32	1860		T34	22		T1	1
all_values[12]	auto[0]	auto[0]	auto[0]	3056022	1			T32	15948		T33	14861		T34	62
all_values[12]	auto[0]	auto[0]	auto[1]	6893976	1			T32	146935		T34	488		T50	415
all_values[12]	auto[0]	auto[1]	auto[0]	745620	1			T32	15609		T34	54		T50	45
all_values[12]	auto[0]	auto[1]	auto[1]	6837727	1			T32	139767		T34	543		T50	631
all_values[12]	auto[1]	auto[0]	auto[1]	100785	1			T32	1828		T34	23		T1	4
all_values[12]	auto[1]	auto[1]	auto[1]	101046	1			T32	1905		T34	17		T1	1
all_values[13]	auto[0]	auto[0]	auto[0]	3053208	1			T32	16005		T33	14861		T34	71
all_values[13]	auto[0]	auto[0]	auto[1]	6862674	1			T32	148481		T34	388		T50	436
all_values[13]	auto[0]	auto[1]	auto[0]	745012	1			T32	14011		T34	91		T50	14
all_values[13]	auto[0]	auto[1]	auto[1]	6872142	1			T32	139633		T34	599		T50	633
all_values[13]	auto[1]	auto[0]	auto[1]	101735	1			T32	1930		T34	17		T1	5
all_values[13]	auto[1]	auto[1]	auto[1]	100405	1			T32	1932		T34	21		T17	13
all_values[14]	auto[0]	auto[0]	auto[0]	3067190	1			T32	15327		T33	14861		T34	64
all_values[14]	auto[0]	auto[0]	auto[1]	6859255	1			T32	137729		T34	532		T50	483
all_values[14]	auto[0]	auto[1]	auto[0]	754073	1			T32	15463		T34	83		T50	64
all_values[14]	auto[0]	auto[1]	auto[1]	6853188	1			T32	149613		T34	470		T50	468
all_values[14]	auto[1]	auto[0]	auto[1]	100217	1			T32	1936		T34	20		T1	6
all_values[14]	auto[1]	auto[1]	auto[1]	101253	1			T32	1924		T34	18		T17	9
all_values[15]	auto[0]	auto[0]	auto[0]	3058456	1			T32	15974		T33	14861		T34	42
all_values[15]	auto[0]	auto[0]	auto[1]	6857435	1			T32	147199		T34	368		T50	456
all_values[15]	auto[0]	auto[1]	auto[0]	748104	1			T32	17607		T34	85		T50	38
all_values[15]	auto[0]	auto[1]	auto[1]	6870341	1			T32	137380		T34	646		T50	540
all_values[15]	auto[1]	auto[0]	auto[1]	100650	1			T32	1957		T34	18		T1	6
all_values[15]	auto[1]	auto[1]	auto[1]	100190	1			T32	1875		T34	28		T1	1
all_values[16]	auto[0]	auto[0]	auto[0]	3063532	1			T32	18802		T33	14861		T34	152
all_values[16]	auto[0]	auto[0]	auto[1]	6838418	1			T32	138124		T34	490		T50	278
all_values[16]	auto[0]	auto[1]	auto[0]	742410	1			T32	14138		T34	102		T50	139
all_values[16]	auto[0]	auto[1]	auto[1]	6888911	1			T32	147150		T34	401		T50	670
all_values[16]	auto[1]	auto[0]	auto[1]	100737	1			T32	1838		T34	25		T1	5
all_values[16]	auto[1]	auto[1]	auto[1]	101168	1			T32	1940		T34	17		T17	20
all_values[17]	auto[0]	auto[0]	auto[0]	3066587	1			T32	17258		T33	14861		T34	85
all_values[17]	auto[0]	auto[0]	auto[1]	6899140	1			T32	143689		T34	632		T50	336
all_values[17]	auto[0]	auto[1]	auto[0]	738250	1			T32	15370		T34	60		T50	54
all_values[17]	auto[0]	auto[1]	auto[1]	6829761	1			T32	141905		T34	380		T50	684
all_values[17]	auto[1]	auto[0]	auto[1]	100786	1			T32	1872		T34	17		T1	3
all_values[17]	auto[1]	auto[1]	auto[1]	100652	1			T32	1898		T34	13		T1	4
all_values[18]	auto[0]	auto[0]	auto[0]	3066954	1			T32	15763		T33	14861		T34	33
all_values[18]	auto[0]	auto[0]	auto[1]	6867537	1			T32	143813		T34	514		T50	706
all_values[18]	auto[0]	auto[1]	auto[0]	743733	1			T32	14552		T34	93		T50	9
all_values[18]	auto[0]	auto[1]	auto[1]	6855119	1			T32	143987		T34	509		T50	359
all_values[18]	auto[1]	auto[0]	auto[1]	101393	1			T32	1973		T34	12		T1	3
all_values[18]	auto[1]	auto[1]	auto[1]	100440	1			T32	1904		T34	26		T1	1
all_values[19]	auto[0]	auto[0]	auto[0]	3053870	1			T32	16281		T33	14861		T34	75
all_values[19]	auto[0]	auto[0]	auto[1]	6872297	1			T32	144293		T34	553		T50	524
all_values[19]	auto[0]	auto[1]	auto[0]	747837	1			T32	16129		T34	77		T50	31
all_values[19]	auto[0]	auto[1]	auto[1]	6859788	1			T32	141494		T34	441		T50	482
all_values[19]	auto[1]	auto[0]	auto[1]	100559	1			T32	1886		T34	20		T1	3
all_values[19]	auto[1]	auto[1]	auto[1]	100825	1			T32	1909		T34	21		T1	4
all_values[20]	auto[0]	auto[0]	auto[0]	3055971	1			T32	15919		T33	14861		T34	81
all_values[20]	auto[0]	auto[0]	auto[1]	6872306	1			T32	151021		T34	471		T50	263
all_values[20]	auto[0]	auto[1]	auto[0]	757257	1			T32	14613		T34	101		T50	48
all_values[20]	auto[0]	auto[1]	auto[1]	6847823	1			T32	136653		T34	498		T50	786
all_values[20]	auto[1]	auto[0]	auto[1]	101023	1			T32	1931		T34	17		T1	2
all_values[20]	auto[1]	auto[1]	auto[1]	100796	1			T32	1855		T34	19		T1	3
all_values[21]	auto[0]	auto[0]	auto[0]	3056646	1			T32	15182		T33	14861		T34	66
all_values[21]	auto[0]	auto[0]	auto[1]	6863729	1			T32	146626		T34	456		T50	547
all_values[21]	auto[0]	auto[1]	auto[0]	747964	1			T32	15528		T34	64		T50	25
all_values[21]	auto[0]	auto[1]	auto[1]	6865741	1			T32	140876		T34	560		T50	489
all_values[21]	auto[1]	auto[0]	auto[1]	100348	1			T32	1914		T34	18		T1	6
all_values[21]	auto[1]	auto[1]	auto[1]	100748	1			T32	1866		T34	23		T1	1
all_values[22]	auto[0]	auto[0]	auto[0]	3064756	1			T32	15998		T33	14861		T34	103
all_values[22]	auto[0]	auto[0]	auto[1]	6896866	1			T32	143495		T34	598		T50	320
all_values[22]	auto[0]	auto[1]	auto[0]	761570	1			T32	16576		T34	44		T50	35
all_values[22]	auto[0]	auto[1]	auto[1]	6810815	1			T32	142138		T34	397		T50	710
all_values[22]	auto[1]	auto[0]	auto[1]	100965	1			T32	1838		T34	25		T1	2
all_values[22]	auto[1]	auto[1]	auto[1]	100204	1			T32	1947		T34	20		T1	2
all_values[23]	auto[0]	auto[0]	auto[0]	3059604	1			T32	16785		T33	14861		T34	50
all_values[23]	auto[0]	auto[0]	auto[1]	6867845	1			T32	141048		T34	559		T50	567
all_values[23]	auto[0]	auto[1]	auto[0]	752473	1			T32	14879		T34	70		T50	46
all_values[23]	auto[0]	auto[1]	auto[1]	6852936	1			T32	145487		T34	465		T50	444
all_values[23]	auto[1]	auto[0]	auto[1]	101624	1			T32	1942		T34	21		T1	5
all_values[23]	auto[1]	auto[1]	auto[1]	100694	1			T32	1851		T34	22		T17	16
all_values[24]	auto[0]	auto[0]	auto[0]	3060843	1			T32	15190		T33	14861		T34	74
all_values[24]	auto[0]	auto[0]	auto[1]	6876818	1			T32	136190		T34	583		T50	468
all_values[24]	auto[0]	auto[1]	auto[0]	751659	1			T32	15045		T34	112		T50	67
all_values[24]	auto[0]	auto[1]	auto[1]	6844451	1			T32	151698		T34	377		T50	530
all_values[24]	auto[1]	auto[0]	auto[1]	101155	1			T32	1908		T34	20		T1	3
all_values[24]	auto[1]	auto[1]	auto[1]	100250	1			T32	1961		T34	21		T17	31
all_values[25]	auto[0]	auto[0]	auto[0]	3066232	1			T32	16745		T33	14861		T34	101
all_values[25]	auto[0]	auto[0]	auto[1]	6904119	1			T32	144827		T34	549		T50	485
all_values[25]	auto[0]	auto[1]	auto[0]	745674	1			T32	14148		T34	103		T50	28
all_values[25]	auto[0]	auto[1]	auto[1]	6817576	1			T32	142468		T34	388		T50	508
all_values[25]	auto[1]	auto[0]	auto[1]	100930	1			T32	1847		T34	33		T1	2
all_values[25]	auto[1]	auto[1]	auto[1]	100645	1			T32	1957		T34	13		T17	17
all_values[26]	auto[0]	auto[0]	auto[0]	3063459	1			T32	16573		T33	14861		T34	49
all_values[26]	auto[0]	auto[0]	auto[1]	6864744	1			T32	150244		T34	484		T50	486
all_values[26]	auto[0]	auto[1]	auto[0]	753098	1			T32	14883		T34	91		T50	46
all_values[26]	auto[0]	auto[1]	auto[1]	6852354	1			T32	136498		T34	518		T50	468
all_values[26]	auto[1]	auto[0]	auto[1]	101141	1			T32	1917		T34	25		T1	3
all_values[26]	auto[1]	auto[1]	auto[1]	100380	1			T32	1877		T34	20		T1	2
all_values[27]	auto[0]	auto[0]	auto[0]	3051311	1			T32	16462		T33	14861		T34	97
all_values[27]	auto[0]	auto[0]	auto[1]	6853555	1			T32	145447		T34	485		T50	677
all_values[27]	auto[0]	auto[1]	auto[0]	746315	1			T32	14205		T34	154		T50	24
all_values[27]	auto[0]	auto[1]	auto[1]	6881984	1			T32	142070		T34	404		T50	346
all_values[27]	auto[1]	auto[0]	auto[1]	101395	1			T32	1940		T34	22		T1	4
all_values[27]	auto[1]	auto[1]	auto[1]	100616	1			T32	1868		T34	25		T1	2
all_values[28]	auto[0]	auto[0]	auto[0]	3071983	1			T32	16775		T33	14861		T34	128
all_values[28]	auto[0]	auto[0]	auto[1]	6877375	1			T32	149243		T34	413		T50	554
all_values[28]	auto[0]	auto[1]	auto[0]	752882	1			T32	14420		T34	54		T50	41
all_values[28]	auto[0]	auto[1]	auto[1]	6831446	1			T32	137708		T34	555		T50	458
all_values[28]	auto[1]	auto[0]	auto[1]	101121	1			T32	1992		T34	18		T1	8
all_values[28]	auto[1]	auto[1]	auto[1]	100369	1			T32	1854		T34	19		T17	12
all_values[29]	auto[0]	auto[0]	auto[0]	3070284	1			T32	17934		T33	14861		T34	64
all_values[29]	auto[0]	auto[0]	auto[1]	6855139	1			T32	143793		T34	517		T50	385
all_values[29]	auto[0]	auto[1]	auto[0]	755336	1			T32	15076		T34	51		T50	68
all_values[29]	auto[0]	auto[1]	auto[1]	6853103	1			T32	141362		T34	518		T50	638
all_values[29]	auto[1]	auto[0]	auto[1]	101166	1			T32	1982		T34	20		T1	4
all_values[29]	auto[1]	auto[1]	auto[1]	100148	1			T32	1845		T34	17		T1	1
all_values[30]	auto[0]	auto[0]	auto[0]	3064422	1			T32	16646		T33	14861		T34	102
all_values[30]	auto[0]	auto[0]	auto[1]	6845492	1			T32	139314		T34	432		T50	424
all_values[30]	auto[0]	auto[1]	auto[0]	754505	1			T32	15902		T34	59		T50	35
all_values[30]	auto[0]	auto[1]	auto[1]	6868958	1			T32	146315		T34	559		T50	640
all_values[30]	auto[1]	auto[0]	auto[1]	101355	1			T32	1897		T34	14		T1	3
all_values[30]	auto[1]	auto[1]	auto[1]	100444	1			T32	1918		T34	21		T1	2
all_values[31]	auto[0]	auto[0]	auto[0]	3053588	1			T32	16575		T33	14861		T34	17
all_values[31]	auto[0]	auto[0]	auto[1]	6861637	1			T32	144566		T34	480		T50	368
all_values[31]	auto[0]	auto[1]	auto[0]	748617	1			T32	16658		T34	41		T50	29
all_values[31]	auto[0]	auto[1]	auto[1]	6869593	1			T32	140345		T34	609		T50	676
all_values[31]	auto[1]	auto[0]	auto[1]	101088	1			T32	1999		T34	15		T1	4
all_values[31]	auto[1]	auto[1]	auto[1]	100653	1			T32	1849		T34	25		T1	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal