Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[1]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[2]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[3]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[4]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[5]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[6]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[7]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[8]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[9]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[10]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[11]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[12]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[13]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[14]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[15]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[16]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[17]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[18]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[19]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[20]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[21]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[22]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[23]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[24]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[25]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[26]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[27]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[28]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[29]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[30]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[31]	17448851	1			T32	315155		T33	14861		T34	1097

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338934377

1

T32

660361

T33

234645

T34

8255

auto[1]

219428855

1

T32

348134

T33

240907

T34

26849

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445258464

1

T32

787801

T33

475552

T34

20252

auto[1]

113104768

1

T32

220694

T34

14852

T35

6583

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

411904629

1

T32

723058

T33

475552

T34

17967

auto[1]

146458603

1

T32

285437

T34

17137

T35

6732

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6485413	1			T32	120048		T33	7896		T34	3
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4601009	1			T32	71114		T33	6965		T34	246
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1782283	1			T32	34483		T34	348		T35	104
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2321999	1			T32	51127		T34	13		T36	92
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	493664	1			T32	3525		T34	320		T35	104
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1764483	1			T32	34858		T34	167		T35	144
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6479454	1			T32	120666		T33	6972		T34	7
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4608627	1			T32	70701		T33	7889		T34	328
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1782919	1			T32	35015		T34	172		T35	80
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2321394	1			T32	51302		T34	7		T36	80
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	493391	1			T32	3477		T34	350		T35	114
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1763066	1			T32	33994		T34	233		T35	89
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6497074	1			T32	120777		T33	7615		T34	5
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4603200	1			T32	71034		T33	7246		T34	292
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1778625	1			T32	34920		T34	291		T35	112
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2317965	1			T32	50622		T34	12		T36	46
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	490946	1			T32	3417		T34	272		T35	111
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1761041	1			T32	34385		T34	225		T35	100
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6498875	1			T32	120271		T33	7038		T34	10
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4602963	1			T32	71270		T33	7823		T34	302
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1777400	1			T32	34574		T34	233		T35	118
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2317031	1			T32	50807		T34	1		T36	99
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	493011	1			T32	3618		T34	280		T35	109
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1759571	1			T32	34615		T34	271		T35	86
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6485832	1			T32	120700		T33	7019		T34	3
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4611732	1			T32	71139		T33	7842		T34	229
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1769826	1			T32	34886		T34	226		T35	94
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2326219	1			T32	50373		T34	12		T36	45
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	495678	1			T32	3545		T34	334		T35	114
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1759564	1			T32	34512		T34	293		T35	94
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6488716	1			T32	120076		T33	6711		T34	15
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4600700	1			T32	71134		T33	8150		T34	370
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1773625	1			T32	34593		T34	210		T35	118
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2322066	1			T32	51661		T34	4		T36	58
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	494516	1			T32	3733		T34	232		T35	88
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1769228	1			T32	33958		T34	266		T35	99
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6496166	1			T32	119229		T33	7842		T34	12
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4598448	1			T32	70654		T33	7019		T34	364
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1776351	1			T32	34010		T34	206		T35	100
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2320913	1			T32	52304		T34	5		T36	63
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	491487	1			T32	3813		T34	259		T35	116
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1765486	1			T32	35145		T34	251		T35	60
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6489566	1			T32	120873		T33	7425		T34	10
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4602244	1			T32	70710		T33	7436		T34	285
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1775678	1			T32	35184		T34	198		T35	98
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2322649	1			T32	50524		T34	10		T36	77
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	495577	1			T32	3521		T34	344		T35	120
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1763137	1			T32	34343		T34	250		T35	111
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6495848	1			T32	121270		T33	7436		T34	5
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4596448	1			T32	70824		T33	7425		T34	296
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1778490	1			T32	34056		T34	248		T35	92
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2320361	1			T32	51821		T34	16		T36	90
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	492033	1			T32	3593		T34	293		T35	94
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1765671	1			T32	33591		T34	239		T35	93
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6486638	1			T32	119788		T33	6649		T34	10
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4603383	1			T32	71150		T33	8212		T34	289
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1780819	1			T32	35607		T34	202		T35	86
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2316740	1			T32	50783		T34	10		T36	65
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	495006	1			T32	3644		T34	332		T35	105
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1766265	1			T32	34183		T34	254		T35	122
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6500211	1			T32	120649		T33	7612		T34	16
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4595395	1			T32	70889		T33	7249		T34	404
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1777829	1			T32	34511		T34	311		T35	118
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2316968	1			T32	50768		T34	2		T36	119
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	495422	1			T32	3514		T34	189		T35	94
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1763026	1			T32	34824		T34	175		T35	118
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6483761	1			T32	119060		T33	6679		T34	11
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4606688	1			T32	70936		T33	8182		T34	363
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1776967	1			T32	35132		T34	220		T35	94
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2322061	1			T32	50906		T34	9		T36	85
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	495728	1			T32	3608		T34	254		T35	90
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1763646	1			T32	35513		T34	240		T35	90
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6507851	1			T32	120317		T33	7514		T34	12
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4580502	1			T32	70635		T33	7347		T34	279
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1779173	1			T32	34636		T34	286		T35	102
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2321232	1			T32	51347		T34	10		T36	74
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	496851	1			T32	3650		T34	318		T35	137
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1763242	1			T32	34570		T34	192		T35	94
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6479984	1			T32	121160		T33	7942		T34	19
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4613713	1			T32	70876		T33	6919		T34	294
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1783685	1			T32	34616		T34	248		T35	84
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2311643	1			T32	51123		T34	6		T36	37
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	493500	1			T32	3537		T34	336		T35	96
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1766326	1			T32	33843		T34	194		T35	128
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6493667	1			T32	120422		T33	7135		T34	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4605445	1			T32	70963		T33	7726		T34	338
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1776185	1			T32	35127		T34	211		T35	132
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2320921	1			T32	50718		T34	7		T36	143
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	493467	1			T32	3457		T34	298		T35	94
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1759166	1			T32	34468		T34	233		T35	117
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6481571	1			T32	119590		T33	7208		T34	8
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4605203	1			T32	70682		T33	7653		T34	306
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1777803	1			T32	35502		T34	206		T35	76
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2324698	1			T32	50849		T34	4		T36	84
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	494255	1			T32	3823		T34	298		T35	118
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1765321	1			T32	34709		T34	275		T35	125
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6489614	1			T32	121136		T33	6529		T34	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4617709	1			T32	70689		T33	8332		T34	305
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1766134	1			T32	34860		T34	166		T35	116
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2328524	1			T32	50598		T34	14		T36	103
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	493044	1			T32	3569		T34	393		T35	92
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1753826	1			T32	34303		T34	211		T35	88
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6496750	1			T32	120328		T33	7252		T34	16
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4603811	1			T32	70867		T33	7609		T34	306
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1773486	1			T32	34236		T34	253		T35	132
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2326840	1			T32	52133		T34	4		T36	91
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	492369	1			T32	3679		T34	270		T35	100
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1755595	1			T32	33912		T34	248		T35	92
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6491517	1			T32	120231		T33	7620		T34	14
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4608216	1			T32	70718		T33	7241		T34	350
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1772213	1			T32	35172		T34	249		T35	99
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2323475	1			T32	51110		T34	1		T36	76
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	495977	1			T32	3602		T34	241		T35	98
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1757453	1			T32	34322		T34	242		T35	90
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6487163	1			T32	119748		T33	6955		T34	8
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4603338	1			T32	71161		T33	7906		T34	259
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1774329	1			T32	33823		T34	244		T35	112
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2327570	1			T32	52161		T34	12		T36	123
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	494897	1			T32	3692		T34	339		T35	104
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1761554	1			T32	34570		T34	235		T35	124
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6492115	1			T32	120607		T33	8295		T34	3
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4606070	1			T32	70728		T33	6566		T34	323
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1775863	1			T32	34077		T34	194		T35	90
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2329034	1			T32	51666		T34	15		T36	75
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	493693	1			T32	3708		T34	346		T35	100
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1752076	1			T32	34369		T34	216		T35	107
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6501461	1			T32	120701		T33	6960		T34	7
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4605094	1			T32	71040		T33	7901		T34	255
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1767589	1			T32	35203		T34	326		T35	90
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2329757	1			T32	50601		T34	11		T36	108
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	491015	1			T32	3434		T34	303		T35	105
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1753935	1			T32	34176		T34	195		T35	86
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6506583	1			T32	120339		T33	7709		T34	15
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4600894	1			T32	71036		T33	7152		T34	374
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1775094	1			T32	34851		T34	357		T35	91
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2325211	1			T32	51720		T34	6		T36	84
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	489875	1			T32	3643		T34	219		T35	106
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1751194	1			T32	33566		T34	126		T35	106
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6484254	1			T32	121845		T33	7727		T34	6
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4616692	1			T32	71124		T33	7134		T34	315
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1769935	1			T32	34794		T34	265		T35	114
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2332248	1			T32	50480		T34	4		T36	120
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	492097	1			T32	3476		T34	326		T35	113
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1753625	1			T32	33436		T34	181		T35	78
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6492259	1			T32	121192		T33	7243		T34	5
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4606959	1			T32	71106		T33	7618		T34	330
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1773477	1			T32	34814		T34	185		T35	91
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2326456	1			T32	50525		T34	11		T36	102
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	493167	1			T32	3543		T34	329		T35	114
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1756533	1			T32	33975		T34	237		T35	102
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6500609	1			T32	119624		T33	6864		T34	9
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4606652	1			T32	70748		T33	7997		T34	347
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1776098	1			T32	34709		T34	239		T35	140
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2322781	1			T32	51989		T34	5		T36	88
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	492871	1			T32	3733		T34	314		T35	104
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1749840	1			T32	34352		T34	183		T35	92
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6496301	1			T32	120703		T33	7721		T34	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4604370	1			T32	70748		T33	7140		T34	341
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1766471	1			T32	34140		T34	218		T35	113
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2328399	1			T32	52105		T34	12		T36	30
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	496222	1			T32	3538		T34	307		T35	116
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1757088	1			T32	33921		T34	209		T35	112
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6502194	1			T32	121075		T33	7347		T34	13
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4598857	1			T32	70671		T33	7514		T34	274
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1775302	1			T32	33843		T34	239		T35	120
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2321950	1			T32	51878		T34	13		T36	87
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	492948	1			T32	3584		T34	325		T35	110
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1757600	1			T32	34104		T34	233		T35	93
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6487776	1			T32	119761		T33	7289		T34	3
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4604123	1			T32	70796		T33	7572		T34	271
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1768529	1			T32	34105		T34	215		T35	59
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2335491	1			T32	52217		T34	19		T36	101
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	496573	1			T32	3683		T34	386		T35	114
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1756359	1			T32	34593		T34	203		T35	130
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6500170	1			T32	120463		T33	7399		T34	3
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4607184	1			T32	70877		T33	7462		T34	258
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1772698	1			T32	34305		T34	208		T35	96
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2323272	1			T32	51677		T34	16		T36	51
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	491011	1			T32	3610		T34	374		T35	116
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1754516	1			T32	34223		T34	238		T35	116
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6494575	1			T32	120382		T33	7162		T34	6
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4602747	1			T32	70934		T33	7699		T34	264
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1771016	1			T32	34164		T34	282		T35	90
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2333491	1			T32	52055		T34	9		T36	130
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	494229	1			T32	3416		T34	300		T35	100
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1752793	1			T32	34204		T34	236		T35	127
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6499065	1			T32	119942		T33	7880		T34	16
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4601053	1			T32	70557		T33	6981		T34	443
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1776235	1			T32	35151		T34	213		T35	86
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2319858	1			T32	51589		T34	8		T36	52
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	492225	1			T32	3607		T34	185		T35	100
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1760415	1			T32	34309		T34	232		T35	123

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal