Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[1]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[2]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[3]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[4]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[5]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[6]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[7]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[8]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[9]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[10]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[11]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[12]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[13]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[14]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[15]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[16]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[17]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[18]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[19]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[20]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[21]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[22]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[23]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[24]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[25]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[26]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[27]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[28]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[29]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[30]	17448851	1			T32	315155		T33	14861		T34	1097
bins_for_gpio_bits[31]	17448851	1			T32	315155		T33	14861		T34	1097

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338934377

1

T32

660361

T33

234645

T34

8255

auto[1]

219428855

1

T32

348134

T33

240907

T34

26849

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338926826

1

T32

660358

T33

234645

T34

8263

auto[1]

219436406

1

T32

348137

T33

240907

T34

26841

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10274788	1			T32	199484		T33	7896		T34	321
bins_for_gpio_bits[0]	auto[0]	auto[1]	314684	1			T32	6174		T34	43		T35	24
bins_for_gpio_bits[0]	auto[1]	auto[0]	314907	1			T32	6174		T34	43		T35	24
bins_for_gpio_bits[0]	auto[1]	auto[1]	6544472	1			T32	103323		T33	6965		T34	690
bins_for_gpio_bits[1]	auto[0]	auto[0]	10268600	1			T32	200880		T33	6972		T34	156
bins_for_gpio_bits[1]	auto[0]	auto[1]	314931	1			T32	6101		T34	30		T35	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	315167	1			T32	6103		T34	30		T35	22
bins_for_gpio_bits[1]	auto[1]	auto[1]	6550153	1			T32	102071		T33	7889		T34	881
bins_for_gpio_bits[2]	auto[0]	auto[0]	10279732	1			T32	200201		T33	7615		T34	272
bins_for_gpio_bits[2]	auto[0]	auto[1]	313715	1			T32	6116		T34	36		T35	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	313932	1			T32	6118		T34	36		T35	26
bins_for_gpio_bits[2]	auto[1]	auto[1]	6541472	1			T32	102720		T33	7246		T34	753
bins_for_gpio_bits[3]	auto[0]	auto[0]	10279359	1			T32	199470		T33	7038		T34	207
bins_for_gpio_bits[3]	auto[0]	auto[1]	313746	1			T32	6182		T34	37		T35	22
bins_for_gpio_bits[3]	auto[1]	auto[0]	313947	1			T32	6182		T34	37		T35	22
bins_for_gpio_bits[3]	auto[1]	auto[1]	6541799	1			T32	103321		T33	7823		T34	816
bins_for_gpio_bits[4]	auto[0]	auto[0]	10267621	1			T32	199774		T33	7019		T34	207
bins_for_gpio_bits[4]	auto[0]	auto[1]	314030	1			T32	6185		T34	34		T35	30
bins_for_gpio_bits[4]	auto[1]	auto[0]	314256	1			T32	6185		T34	34		T35	30
bins_for_gpio_bits[4]	auto[1]	auto[1]	6552944	1			T32	103011		T33	7842		T34	822
bins_for_gpio_bits[5]	auto[0]	auto[0]	10268991	1			T32	200103		T33	6711		T34	194
bins_for_gpio_bits[5]	auto[0]	auto[1]	315162	1			T32	6225		T34	35		T35	27
bins_for_gpio_bits[5]	auto[1]	auto[0]	315416	1			T32	6227		T34	35		T35	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	6549282	1			T32	102600		T33	8150		T34	833
bins_for_gpio_bits[6]	auto[0]	auto[0]	10278665	1			T32	199311		T33	7842		T34	189
bins_for_gpio_bits[6]	auto[0]	auto[1]	314522	1			T32	6230		T34	34		T35	25
bins_for_gpio_bits[6]	auto[1]	auto[0]	314765	1			T32	6232		T34	34		T35	25
bins_for_gpio_bits[6]	auto[1]	auto[1]	6540899	1			T32	103382		T33	7019		T34	840
bins_for_gpio_bits[7]	auto[0]	auto[0]	10273412	1			T32	200449		T33	7425		T34	183
bins_for_gpio_bits[7]	auto[0]	auto[1]	314254	1			T32	6132		T34	36		T35	27
bins_for_gpio_bits[7]	auto[1]	auto[0]	314481	1			T32	6132		T34	35		T35	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	6546704	1			T32	102442		T33	7436		T34	843
bins_for_gpio_bits[8]	auto[0]	auto[0]	10279743	1			T32	201054		T33	7436		T34	230
bins_for_gpio_bits[8]	auto[0]	auto[1]	314696	1			T32	6091		T34	39		T35	28
bins_for_gpio_bits[8]	auto[1]	auto[0]	314956	1			T32	6093		T34	39		T35	28
bins_for_gpio_bits[8]	auto[1]	auto[1]	6539456	1			T32	101917		T33	7425		T34	789
bins_for_gpio_bits[9]	auto[0]	auto[0]	10269305	1			T32	199968		T33	6649		T34	188
bins_for_gpio_bits[9]	auto[0]	auto[1]	314644	1			T32	6209		T34	34		T35	22
bins_for_gpio_bits[9]	auto[1]	auto[0]	314892	1			T32	6210		T34	34		T35	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	6550010	1			T32	102768		T33	8212		T34	841
bins_for_gpio_bits[10]	auto[0]	auto[0]	10280779	1			T32	199741		T33	7612		T34	290
bins_for_gpio_bits[10]	auto[0]	auto[1]	314009	1			T32	6187		T34	39		T35	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	314229	1			T32	6187		T34	39		T35	27
bins_for_gpio_bits[10]	auto[1]	auto[1]	6539834	1			T32	103040		T33	7249		T34	729
bins_for_gpio_bits[11]	auto[0]	auto[0]	10268474	1			T32	198855		T33	6679		T34	193
bins_for_gpio_bits[11]	auto[0]	auto[1]	314054	1			T32	6242		T34	48		T35	25
bins_for_gpio_bits[11]	auto[1]	auto[0]	314315	1			T32	6243		T34	47		T35	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	6552008	1			T32	103815		T33	8182		T34	809
bins_for_gpio_bits[12]	auto[0]	auto[0]	10293949	1			T32	200101		T33	7514		T34	273
bins_for_gpio_bits[12]	auto[0]	auto[1]	314105	1			T32	6199		T34	36		T35	20
bins_for_gpio_bits[12]	auto[1]	auto[0]	314307	1			T32	6199		T34	35		T35	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	6526490	1			T32	102656		T33	7347		T34	753
bins_for_gpio_bits[13]	auto[0]	auto[0]	10260422	1			T32	200918		T33	7942		T34	239
bins_for_gpio_bits[13]	auto[0]	auto[1]	314637	1			T32	5981		T34	35		T35	23
bins_for_gpio_bits[13]	auto[1]	auto[0]	314890	1			T32	5981		T34	34		T35	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	6558902	1			T32	102275		T33	6919		T34	789
bins_for_gpio_bits[14]	auto[0]	auto[0]	10276289	1			T32	200126		T33	7135		T34	191
bins_for_gpio_bits[14]	auto[0]	auto[1]	314236	1			T32	6141		T34	37		T35	27
bins_for_gpio_bits[14]	auto[1]	auto[0]	314484	1			T32	6141		T34	37		T35	27
bins_for_gpio_bits[14]	auto[1]	auto[1]	6543842	1			T32	102747		T33	7726		T34	832
bins_for_gpio_bits[15]	auto[0]	auto[0]	10268788	1			T32	199748		T33	7208		T34	184
bins_for_gpio_bits[15]	auto[0]	auto[1]	315063	1			T32	6192		T34	34		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[0]	315284	1			T32	6193		T34	34		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	6549716	1			T32	103022		T33	7653		T34	845
bins_for_gpio_bits[16]	auto[0]	auto[0]	10269407	1			T32	200423		T33	6529		T34	159
bins_for_gpio_bits[16]	auto[0]	auto[1]	314648	1			T32	6170		T34	29		T35	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	314865	1			T32	6171		T34	29		T35	27
bins_for_gpio_bits[16]	auto[1]	auto[1]	6549931	1			T32	102391		T33	8332		T34	880
bins_for_gpio_bits[17]	auto[0]	auto[0]	10281718	1			T32	200565		T33	7252		T34	234
bins_for_gpio_bits[17]	auto[0]	auto[1]	315123	1			T32	6131		T34	39		T35	29
bins_for_gpio_bits[17]	auto[1]	auto[0]	315358	1			T32	6132		T34	39		T35	29
bins_for_gpio_bits[17]	auto[1]	auto[1]	6536652	1			T32	102327		T33	7609		T34	785
bins_for_gpio_bits[18]	auto[0]	auto[0]	10272144	1			T32	200272		T33	7620		T34	229
bins_for_gpio_bits[18]	auto[0]	auto[1]	314811	1			T32	6240		T34	35		T35	29
bins_for_gpio_bits[18]	auto[1]	auto[0]	315061	1			T32	6241		T34	35		T35	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	6546835	1			T32	102402		T33	7241		T34	798
bins_for_gpio_bits[19]	auto[0]	auto[0]	10274031	1			T32	199611		T33	6955		T34	234
bins_for_gpio_bits[19]	auto[0]	auto[1]	314794	1			T32	6120		T34	30		T35	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	315031	1			T32	6121		T34	30		T35	24
bins_for_gpio_bits[19]	auto[1]	auto[1]	6544995	1			T32	103303		T33	7906		T34	803
bins_for_gpio_bits[20]	auto[0]	auto[0]	10282644	1			T32	200302		T33	8295		T34	176
bins_for_gpio_bits[20]	auto[0]	auto[1]	314144	1			T32	6048		T34	36		T35	23
bins_for_gpio_bits[20]	auto[1]	auto[0]	314368	1			T32	6048		T34	36		T35	23
bins_for_gpio_bits[20]	auto[1]	auto[1]	6537695	1			T32	102757		T33	6566		T34	849
bins_for_gpio_bits[21]	auto[0]	auto[0]	10284529	1			T32	200301		T33	6960		T34	311
bins_for_gpio_bits[21]	auto[0]	auto[1]	314015	1			T32	6204		T34	33		T35	26
bins_for_gpio_bits[21]	auto[1]	auto[0]	314278	1			T32	6204		T34	33		T35	26
bins_for_gpio_bits[21]	auto[1]	auto[1]	6536029	1			T32	102446		T33	7901		T34	720
bins_for_gpio_bits[22]	auto[0]	auto[0]	10292506	1			T32	200715		T33	7709		T34	334
bins_for_gpio_bits[22]	auto[0]	auto[1]	314142	1			T32	6195		T34	45		T35	28
bins_for_gpio_bits[22]	auto[1]	auto[0]	314382	1			T32	6195		T34	44		T35	27
bins_for_gpio_bits[22]	auto[1]	auto[1]	6527821	1			T32	102050		T33	7152		T34	674
bins_for_gpio_bits[23]	auto[0]	auto[0]	10271393	1			T32	201092		T33	7727		T34	245
bins_for_gpio_bits[23]	auto[0]	auto[1]	314800	1			T32	6027		T34	30		T35	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	315044	1			T32	6027		T34	30		T35	28
bins_for_gpio_bits[23]	auto[1]	auto[1]	6547614	1			T32	102009		T33	7134		T34	792
bins_for_gpio_bits[24]	auto[0]	auto[0]	10276966	1			T32	200469		T33	7243		T34	173
bins_for_gpio_bits[24]	auto[0]	auto[1]	315000	1			T32	6061		T34	28		T35	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	315226	1			T32	6062		T34	28		T35	25
bins_for_gpio_bits[24]	auto[1]	auto[1]	6541659	1			T32	102563		T33	7618		T34	868
bins_for_gpio_bits[25]	auto[0]	auto[0]	10285443	1			T32	200222		T33	6864		T34	222
bins_for_gpio_bits[25]	auto[0]	auto[1]	313804	1			T32	6100		T34	31		T35	29
bins_for_gpio_bits[25]	auto[1]	auto[0]	314045	1			T32	6100		T34	31		T35	29
bins_for_gpio_bits[25]	auto[1]	auto[1]	6535559	1			T32	102733		T33	7997		T34	813
bins_for_gpio_bits[26]	auto[0]	auto[0]	10276498	1			T32	200845		T33	7721		T34	211
bins_for_gpio_bits[26]	auto[0]	auto[1]	314461	1			T32	6101		T34	29		T35	21
bins_for_gpio_bits[26]	auto[1]	auto[0]	314673	1			T32	6103		T34	29		T35	20
bins_for_gpio_bits[26]	auto[1]	auto[1]	6543219	1			T32	102106		T33	7140		T34	828
bins_for_gpio_bits[27]	auto[0]	auto[0]	10283792	1			T32	200585		T33	7347		T34	233
bins_for_gpio_bits[27]	auto[0]	auto[1]	315394	1			T32	6211		T34	33		T35	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	315654	1			T32	6211		T34	32		T35	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	6534011	1			T32	102148		T33	7514		T34	799
bins_for_gpio_bits[28]	auto[0]	auto[0]	10276840	1			T32	199816		T33	7289		T34	210
bins_for_gpio_bits[28]	auto[0]	auto[1]	314710	1			T32	6267		T34	28		T35	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	314956	1			T32	6267		T34	27		T35	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	6542345	1			T32	102805		T33	7572		T34	832
bins_for_gpio_bits[29]	auto[0]	auto[0]	10281032	1			T32	200174		T33	7399		T34	197
bins_for_gpio_bits[29]	auto[0]	auto[1]	314881	1			T32	6270		T34	30		T35	26
bins_for_gpio_bits[29]	auto[1]	auto[0]	315108	1			T32	6271		T34	30		T35	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	6537830	1			T32	102440		T33	7462		T34	840
bins_for_gpio_bits[30]	auto[0]	auto[0]	10285044	1			T32	200398		T33	7162		T34	263
bins_for_gpio_bits[30]	auto[0]	auto[1]	313789	1			T32	6201		T34	35		T35	28
bins_for_gpio_bits[30]	auto[1]	auto[0]	314038	1			T32	6203		T34	34		T35	28
bins_for_gpio_bits[30]	auto[1]	auto[1]	6535980	1			T32	102353		T33	7699		T34	765
bins_for_gpio_bits[31]	auto[0]	auto[0]	10280697	1			T32	200553		T33	7880		T34	199
bins_for_gpio_bits[31]	auto[0]	auto[1]	314221	1			T32	6127		T34	38		T35	24
bins_for_gpio_bits[31]	auto[1]	auto[0]	314461	1			T32	6129		T34	38		T35	24
bins_for_gpio_bits[31]	auto[1]	auto[1]	6539472	1			T32	102346		T33	6981		T34	822