Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026588 |
1 |
|
|
T32 |
160006 |
|
T33 |
14861 |
|
T34 |
756 |
| auto[1] |
7708588 |
1 |
|
|
T32 |
161986 |
|
T34 |
431 |
|
T50 |
639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16758013 |
1 |
|
|
T32 |
301237 |
|
T33 |
14861 |
|
T34 |
1166 |
| auto[1] |
977163 |
1 |
|
|
T32 |
20755 |
|
T34 |
21 |
|
T50 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10034851 |
1 |
|
|
T32 |
163186 |
|
T33 |
14861 |
|
T34 |
664 |
| auto[1] |
7700325 |
1 |
|
|
T32 |
158806 |
|
T34 |
523 |
|
T50 |
564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3372948 |
1 |
|
|
T32 |
67199 |
|
T34 |
365 |
|
T50 |
163 |
| auto[1] |
auto[0] |
auto[1] |
490022 |
1 |
|
|
T32 |
10056 |
|
T34 |
16 |
|
T50 |
36 |
| auto[1] |
auto[1] |
auto[0] |
3350214 |
1 |
|
|
T32 |
70852 |
|
T34 |
137 |
|
T50 |
293 |
| auto[1] |
auto[1] |
auto[1] |
487141 |
1 |
|
|
T32 |
10699 |
|
T34 |
5 |
|
T50 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10002677 |
1 |
|
|
T32 |
167614 |
|
T33 |
14861 |
|
T34 |
529 |
| auto[1] |
7732499 |
1 |
|
|
T32 |
154378 |
|
T34 |
658 |
|
T50 |
628 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16754640 |
1 |
|
|
T32 |
301909 |
|
T33 |
14861 |
|
T34 |
1172 |
| auto[1] |
980536 |
1 |
|
|
T32 |
20083 |
|
T34 |
15 |
|
T50 |
120 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10037990 |
1 |
|
|
T32 |
167063 |
|
T33 |
14861 |
|
T34 |
826 |
| auto[1] |
7697186 |
1 |
|
|
T32 |
154929 |
|
T34 |
361 |
|
T50 |
652 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3341551 |
1 |
|
|
T32 |
68393 |
|
T34 |
184 |
|
T50 |
182 |
| auto[1] |
auto[0] |
auto[1] |
486997 |
1 |
|
|
T32 |
10146 |
|
T34 |
10 |
|
T50 |
40 |
| auto[1] |
auto[1] |
auto[0] |
3375099 |
1 |
|
|
T32 |
66453 |
|
T34 |
162 |
|
T50 |
350 |
| auto[1] |
auto[1] |
auto[1] |
493539 |
1 |
|
|
T32 |
9937 |
|
T34 |
5 |
|
T50 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10006069 |
1 |
|
|
T32 |
158718 |
|
T33 |
14861 |
|
T34 |
574 |
| auto[1] |
7729107 |
1 |
|
|
T32 |
163274 |
|
T34 |
613 |
|
T50 |
536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16760361 |
1 |
|
|
T32 |
301610 |
|
T33 |
14861 |
|
T34 |
1163 |
| auto[1] |
974815 |
1 |
|
|
T32 |
20382 |
|
T34 |
24 |
|
T50 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10066683 |
1 |
|
|
T32 |
165874 |
|
T33 |
14861 |
|
T34 |
549 |
| auto[1] |
7668493 |
1 |
|
|
T32 |
156118 |
|
T34 |
638 |
|
T50 |
619 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3342352 |
1 |
|
|
T32 |
68833 |
|
T34 |
277 |
|
T50 |
210 |
| auto[1] |
auto[0] |
auto[1] |
485945 |
1 |
|
|
T32 |
10423 |
|
T34 |
14 |
|
T50 |
57 |
| auto[1] |
auto[1] |
auto[0] |
3351326 |
1 |
|
|
T32 |
66903 |
|
T34 |
337 |
|
T50 |
288 |
| auto[1] |
auto[1] |
auto[1] |
488870 |
1 |
|
|
T32 |
9959 |
|
T34 |
10 |
|
T50 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9999553 |
1 |
|
|
T32 |
166179 |
|
T33 |
14861 |
|
T34 |
685 |
| auto[1] |
7735623 |
1 |
|
|
T32 |
155813 |
|
T34 |
502 |
|
T50 |
627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757781 |
1 |
|
|
T32 |
300224 |
|
T33 |
14861 |
|
T34 |
1157 |
| auto[1] |
977395 |
1 |
|
|
T32 |
21768 |
|
T34 |
30 |
|
T50 |
83 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040366 |
1 |
|
|
T32 |
157604 |
|
T33 |
14861 |
|
T34 |
547 |
| auto[1] |
7694810 |
1 |
|
|
T32 |
164388 |
|
T34 |
640 |
|
T50 |
437 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3367071 |
1 |
|
|
T32 |
73813 |
|
T34 |
323 |
|
T50 |
134 |
| auto[1] |
auto[0] |
auto[1] |
489701 |
1 |
|
|
T32 |
11178 |
|
T34 |
13 |
|
T50 |
28 |
| auto[1] |
auto[1] |
auto[0] |
3350344 |
1 |
|
|
T32 |
68807 |
|
T34 |
287 |
|
T50 |
220 |
| auto[1] |
auto[1] |
auto[1] |
487694 |
1 |
|
|
T32 |
10590 |
|
T34 |
17 |
|
T50 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050783 |
1 |
|
|
T32 |
164711 |
|
T33 |
14861 |
|
T34 |
573 |
| auto[1] |
7684393 |
1 |
|
|
T32 |
157281 |
|
T34 |
614 |
|
T50 |
676 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16752814 |
1 |
|
|
T32 |
301758 |
|
T33 |
14861 |
|
T34 |
1163 |
| auto[1] |
982362 |
1 |
|
|
T32 |
20234 |
|
T34 |
24 |
|
T50 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10022597 |
1 |
|
|
T32 |
165917 |
|
T33 |
14861 |
|
T34 |
501 |
| auto[1] |
7712579 |
1 |
|
|
T32 |
156075 |
|
T34 |
686 |
|
T50 |
602 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3377445 |
1 |
|
|
T32 |
66765 |
|
T34 |
284 |
|
T50 |
203 |
| auto[1] |
auto[0] |
auto[1] |
494271 |
1 |
|
|
T32 |
10060 |
|
T34 |
11 |
|
T50 |
50 |
| auto[1] |
auto[1] |
auto[0] |
3352772 |
1 |
|
|
T32 |
69076 |
|
T34 |
378 |
|
T50 |
286 |
| auto[1] |
auto[1] |
auto[1] |
488091 |
1 |
|
|
T32 |
10174 |
|
T34 |
13 |
|
T50 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10017617 |
1 |
|
|
T32 |
166416 |
|
T33 |
14861 |
|
T34 |
476 |
| auto[1] |
7717559 |
1 |
|
|
T32 |
155576 |
|
T34 |
711 |
|
T50 |
647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16763426 |
1 |
|
|
T32 |
300857 |
|
T33 |
14861 |
|
T34 |
1169 |
| auto[1] |
971750 |
1 |
|
|
T32 |
21135 |
|
T34 |
18 |
|
T50 |
147 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071103 |
1 |
|
|
T32 |
160819 |
|
T33 |
14861 |
|
T34 |
725 |
| auto[1] |
7664073 |
1 |
|
|
T32 |
161173 |
|
T34 |
462 |
|
T50 |
732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3351013 |
1 |
|
|
T32 |
73636 |
|
T34 |
173 |
|
T50 |
280 |
| auto[1] |
auto[0] |
auto[1] |
485555 |
1 |
|
|
T32 |
11146 |
|
T34 |
6 |
|
T50 |
66 |
| auto[1] |
auto[1] |
auto[0] |
3341310 |
1 |
|
|
T32 |
66402 |
|
T34 |
271 |
|
T50 |
305 |
| auto[1] |
auto[1] |
auto[1] |
486195 |
1 |
|
|
T32 |
9989 |
|
T34 |
12 |
|
T50 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026662 |
1 |
|
|
T32 |
154992 |
|
T33 |
14861 |
|
T34 |
616 |
| auto[1] |
7708514 |
1 |
|
|
T32 |
167000 |
|
T34 |
571 |
|
T50 |
532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16759809 |
1 |
|
|
T32 |
302084 |
|
T33 |
14861 |
|
T34 |
1168 |
| auto[1] |
975367 |
1 |
|
|
T32 |
19908 |
|
T34 |
19 |
|
T50 |
84 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10059788 |
1 |
|
|
T32 |
169521 |
|
T33 |
14861 |
|
T34 |
724 |
| auto[1] |
7675388 |
1 |
|
|
T32 |
152471 |
|
T34 |
463 |
|
T50 |
458 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3352404 |
1 |
|
|
T32 |
64787 |
|
T34 |
183 |
|
T50 |
270 |
| auto[1] |
auto[0] |
auto[1] |
489342 |
1 |
|
|
T32 |
9630 |
|
T34 |
9 |
|
T50 |
54 |
| auto[1] |
auto[1] |
auto[0] |
3347617 |
1 |
|
|
T32 |
67776 |
|
T34 |
261 |
|
T50 |
104 |
| auto[1] |
auto[1] |
auto[1] |
486025 |
1 |
|
|
T32 |
10278 |
|
T34 |
10 |
|
T50 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10016541 |
1 |
|
|
T32 |
165130 |
|
T33 |
14861 |
|
T34 |
428 |
| auto[1] |
7718635 |
1 |
|
|
T32 |
156862 |
|
T34 |
759 |
|
T50 |
578 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16748956 |
1 |
|
|
T32 |
300394 |
|
T33 |
14861 |
|
T34 |
1164 |
| auto[1] |
986220 |
1 |
|
|
T32 |
21598 |
|
T34 |
23 |
|
T50 |
64 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9984563 |
1 |
|
|
T32 |
159220 |
|
T33 |
14861 |
|
T34 |
514 |
| auto[1] |
7750613 |
1 |
|
|
T32 |
162772 |
|
T34 |
673 |
|
T50 |
370 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3380832 |
1 |
|
|
T32 |
74867 |
|
T34 |
225 |
|
T50 |
131 |
| auto[1] |
auto[0] |
auto[1] |
493634 |
1 |
|
|
T32 |
11758 |
|
T34 |
8 |
|
T50 |
32 |
| auto[1] |
auto[1] |
auto[0] |
3383561 |
1 |
|
|
T32 |
66307 |
|
T34 |
425 |
|
T50 |
175 |
| auto[1] |
auto[1] |
auto[1] |
492586 |
1 |
|
|
T32 |
9840 |
|
T34 |
15 |
|
T50 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10002687 |
1 |
|
|
T32 |
158764 |
|
T33 |
14861 |
|
T34 |
667 |
| auto[1] |
7732489 |
1 |
|
|
T32 |
163228 |
|
T34 |
520 |
|
T50 |
809 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16759500 |
1 |
|
|
T32 |
300094 |
|
T33 |
14861 |
|
T34 |
1173 |
| auto[1] |
975676 |
1 |
|
|
T32 |
21898 |
|
T34 |
14 |
|
T50 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050185 |
1 |
|
|
T32 |
155932 |
|
T33 |
14861 |
|
T34 |
660 |
| auto[1] |
7684991 |
1 |
|
|
T32 |
166060 |
|
T34 |
527 |
|
T50 |
417 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3346149 |
1 |
|
|
T32 |
68735 |
|
T34 |
326 |
|
T50 |
119 |
| auto[1] |
auto[0] |
auto[1] |
486169 |
1 |
|
|
T32 |
10377 |
|
T34 |
9 |
|
T50 |
34 |
| auto[1] |
auto[1] |
auto[0] |
3363166 |
1 |
|
|
T32 |
75427 |
|
T34 |
187 |
|
T50 |
208 |
| auto[1] |
auto[1] |
auto[1] |
489507 |
1 |
|
|
T32 |
11521 |
|
T34 |
5 |
|
T50 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10066513 |
1 |
|
|
T32 |
162819 |
|
T33 |
14861 |
|
T34 |
734 |
| auto[1] |
7668663 |
1 |
|
|
T32 |
159173 |
|
T34 |
453 |
|
T50 |
738 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16758450 |
1 |
|
|
T32 |
300806 |
|
T33 |
14861 |
|
T34 |
1149 |
| auto[1] |
976726 |
1 |
|
|
T32 |
21186 |
|
T34 |
38 |
|
T50 |
139 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10051269 |
1 |
|
|
T32 |
160650 |
|
T33 |
14861 |
|
T34 |
349 |
| auto[1] |
7683907 |
1 |
|
|
T32 |
161342 |
|
T34 |
838 |
|
T50 |
715 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3375373 |
1 |
|
|
T32 |
70081 |
|
T34 |
499 |
|
T50 |
224 |
| auto[1] |
auto[0] |
auto[1] |
491608 |
1 |
|
|
T32 |
10595 |
|
T34 |
23 |
|
T50 |
59 |
| auto[1] |
auto[1] |
auto[0] |
3331808 |
1 |
|
|
T32 |
70075 |
|
T34 |
301 |
|
T50 |
352 |
| auto[1] |
auto[1] |
auto[1] |
485118 |
1 |
|
|
T32 |
10591 |
|
T34 |
15 |
|
T50 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10035884 |
1 |
|
|
T32 |
161549 |
|
T33 |
14861 |
|
T34 |
559 |
| auto[1] |
7699292 |
1 |
|
|
T32 |
160443 |
|
T34 |
628 |
|
T50 |
368 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16748970 |
1 |
|
|
T32 |
300063 |
|
T33 |
14861 |
|
T34 |
1165 |
| auto[1] |
986206 |
1 |
|
|
T32 |
21929 |
|
T34 |
22 |
|
T50 |
165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9987436 |
1 |
|
|
T32 |
156305 |
|
T33 |
14861 |
|
T34 |
683 |
| auto[1] |
7747740 |
1 |
|
|
T32 |
165687 |
|
T34 |
504 |
|
T50 |
863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3400313 |
1 |
|
|
T32 |
72599 |
|
T34 |
264 |
|
T50 |
493 |
| auto[1] |
auto[0] |
auto[1] |
496862 |
1 |
|
|
T32 |
11086 |
|
T34 |
9 |
|
T50 |
112 |
| auto[1] |
auto[1] |
auto[0] |
3361221 |
1 |
|
|
T32 |
71159 |
|
T34 |
218 |
|
T50 |
205 |
| auto[1] |
auto[1] |
auto[1] |
489344 |
1 |
|
|
T32 |
10843 |
|
T34 |
13 |
|
T50 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026726 |
1 |
|
|
T32 |
162460 |
|
T33 |
14861 |
|
T34 |
648 |
| auto[1] |
7708450 |
1 |
|
|
T32 |
159532 |
|
T34 |
539 |
|
T50 |
513 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757136 |
1 |
|
|
T32 |
301985 |
|
T33 |
14861 |
|
T34 |
1169 |
| auto[1] |
978040 |
1 |
|
|
T32 |
20007 |
|
T34 |
18 |
|
T50 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10035690 |
1 |
|
|
T32 |
168781 |
|
T33 |
14861 |
|
T34 |
563 |
| auto[1] |
7699486 |
1 |
|
|
T32 |
153211 |
|
T34 |
624 |
|
T50 |
680 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3361881 |
1 |
|
|
T32 |
66905 |
|
T34 |
327 |
|
T50 |
336 |
| auto[1] |
auto[0] |
auto[1] |
489838 |
1 |
|
|
T32 |
9974 |
|
T34 |
7 |
|
T50 |
71 |
| auto[1] |
auto[1] |
auto[0] |
3359565 |
1 |
|
|
T32 |
66299 |
|
T34 |
279 |
|
T50 |
220 |
| auto[1] |
auto[1] |
auto[1] |
488202 |
1 |
|
|
T32 |
10033 |
|
T34 |
11 |
|
T50 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033408 |
1 |
|
|
T32 |
159151 |
|
T33 |
14861 |
|
T34 |
699 |
| auto[1] |
7701768 |
1 |
|
|
T32 |
162841 |
|
T34 |
488 |
|
T50 |
546 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16754875 |
1 |
|
|
T32 |
301497 |
|
T33 |
14861 |
|
T34 |
1160 |
| auto[1] |
980301 |
1 |
|
|
T32 |
20495 |
|
T34 |
27 |
|
T50 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011662 |
1 |
|
|
T32 |
164035 |
|
T33 |
14861 |
|
T34 |
583 |
| auto[1] |
7723514 |
1 |
|
|
T32 |
157957 |
|
T34 |
604 |
|
T50 |
543 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3377547 |
1 |
|
|
T32 |
66045 |
|
T34 |
363 |
|
T50 |
256 |
| auto[1] |
auto[0] |
auto[1] |
491329 |
1 |
|
|
T32 |
9889 |
|
T34 |
22 |
|
T50 |
54 |
| auto[1] |
auto[1] |
auto[0] |
3365666 |
1 |
|
|
T32 |
71417 |
|
T34 |
214 |
|
T50 |
179 |
| auto[1] |
auto[1] |
auto[1] |
488972 |
1 |
|
|
T32 |
10606 |
|
T34 |
5 |
|
T50 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10029300 |
1 |
|
|
T32 |
168871 |
|
T33 |
14861 |
|
T34 |
569 |
| auto[1] |
7705876 |
1 |
|
|
T32 |
153121 |
|
T34 |
618 |
|
T50 |
834 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16752604 |
1 |
|
|
T32 |
301061 |
|
T33 |
14861 |
|
T34 |
1163 |
| auto[1] |
982572 |
1 |
|
|
T32 |
20931 |
|
T34 |
24 |
|
T50 |
83 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10010851 |
1 |
|
|
T32 |
161974 |
|
T33 |
14861 |
|
T34 |
617 |
| auto[1] |
7724325 |
1 |
|
|
T32 |
160018 |
|
T34 |
570 |
|
T50 |
461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3347112 |
1 |
|
|
T32 |
73600 |
|
T34 |
236 |
|
T50 |
67 |
| auto[1] |
auto[0] |
auto[1] |
485481 |
1 |
|
|
T32 |
11110 |
|
T34 |
13 |
|
T50 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3394641 |
1 |
|
|
T32 |
65487 |
|
T34 |
310 |
|
T50 |
311 |
| auto[1] |
auto[1] |
auto[1] |
497091 |
1 |
|
|
T32 |
9821 |
|
T34 |
11 |
|
T50 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10020723 |
1 |
|
|
T32 |
163722 |
|
T33 |
14861 |
|
T34 |
540 |
| auto[1] |
7714453 |
1 |
|
|
T32 |
158270 |
|
T34 |
647 |
|
T50 |
514 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16756159 |
1 |
|
|
T32 |
300441 |
|
T33 |
14861 |
|
T34 |
1167 |
| auto[1] |
979017 |
1 |
|
|
T32 |
21551 |
|
T34 |
20 |
|
T50 |
104 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10028568 |
1 |
|
|
T32 |
158032 |
|
T33 |
14861 |
|
T34 |
558 |
| auto[1] |
7706608 |
1 |
|
|
T32 |
163960 |
|
T34 |
629 |
|
T50 |
512 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3364850 |
1 |
|
|
T32 |
73579 |
|
T34 |
225 |
|
T50 |
226 |
| auto[1] |
auto[0] |
auto[1] |
489894 |
1 |
|
|
T32 |
11242 |
|
T34 |
11 |
|
T50 |
55 |
| auto[1] |
auto[1] |
auto[0] |
3362741 |
1 |
|
|
T32 |
68830 |
|
T34 |
384 |
|
T50 |
182 |
| auto[1] |
auto[1] |
auto[1] |
489123 |
1 |
|
|
T32 |
10309 |
|
T34 |
9 |
|
T50 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10062587 |
1 |
|
|
T32 |
161331 |
|
T33 |
14861 |
|
T34 |
726 |
| auto[1] |
7672589 |
1 |
|
|
T32 |
160661 |
|
T34 |
461 |
|
T50 |
745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16752264 |
1 |
|
|
T32 |
301584 |
|
T33 |
14861 |
|
T34 |
1146 |
| auto[1] |
982912 |
1 |
|
|
T32 |
20408 |
|
T34 |
41 |
|
T50 |
103 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10005335 |
1 |
|
|
T32 |
165991 |
|
T33 |
14861 |
|
T34 |
463 |
| auto[1] |
7729841 |
1 |
|
|
T32 |
156001 |
|
T34 |
724 |
|
T50 |
536 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3389529 |
1 |
|
|
T32 |
67498 |
|
T34 |
460 |
|
T50 |
139 |
| auto[1] |
auto[0] |
auto[1] |
493808 |
1 |
|
|
T32 |
10161 |
|
T34 |
30 |
|
T50 |
36 |
| auto[1] |
auto[1] |
auto[0] |
3357400 |
1 |
|
|
T32 |
68095 |
|
T34 |
223 |
|
T50 |
294 |
| auto[1] |
auto[1] |
auto[1] |
489104 |
1 |
|
|
T32 |
10247 |
|
T34 |
11 |
|
T50 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10029073 |
1 |
|
|
T32 |
159775 |
|
T33 |
14861 |
|
T34 |
630 |
| auto[1] |
7706103 |
1 |
|
|
T32 |
162217 |
|
T34 |
557 |
|
T50 |
490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757751 |
1 |
|
|
T32 |
299807 |
|
T33 |
14861 |
|
T34 |
1171 |
| auto[1] |
977425 |
1 |
|
|
T32 |
22185 |
|
T34 |
16 |
|
T50 |
95 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038249 |
1 |
|
|
T32 |
154700 |
|
T33 |
14861 |
|
T34 |
546 |
| auto[1] |
7696927 |
1 |
|
|
T32 |
167292 |
|
T34 |
641 |
|
T50 |
460 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3350684 |
1 |
|
|
T32 |
68759 |
|
T34 |
305 |
|
T50 |
250 |
| auto[1] |
auto[0] |
auto[1] |
486002 |
1 |
|
|
T32 |
10445 |
|
T34 |
9 |
|
T50 |
61 |
| auto[1] |
auto[1] |
auto[0] |
3368818 |
1 |
|
|
T32 |
76348 |
|
T34 |
320 |
|
T50 |
115 |
| auto[1] |
auto[1] |
auto[1] |
491423 |
1 |
|
|
T32 |
11740 |
|
T34 |
7 |
|
T50 |
34 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038816 |
1 |
|
|
T32 |
153288 |
|
T33 |
14861 |
|
T34 |
677 |
| auto[1] |
7696360 |
1 |
|
|
T32 |
168704 |
|
T34 |
510 |
|
T50 |
597 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16760690 |
1 |
|
|
T32 |
301295 |
|
T33 |
14861 |
|
T34 |
1172 |
| auto[1] |
974486 |
1 |
|
|
T32 |
20697 |
|
T34 |
15 |
|
T50 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10065750 |
1 |
|
|
T32 |
162227 |
|
T33 |
14861 |
|
T34 |
712 |
| auto[1] |
7669426 |
1 |
|
|
T32 |
159765 |
|
T34 |
475 |
|
T50 |
530 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3359197 |
1 |
|
|
T32 |
64892 |
|
T34 |
293 |
|
T50 |
176 |
| auto[1] |
auto[0] |
auto[1] |
489290 |
1 |
|
|
T32 |
9544 |
|
T34 |
11 |
|
T50 |
49 |
| auto[1] |
auto[1] |
auto[0] |
3335743 |
1 |
|
|
T32 |
74176 |
|
T34 |
167 |
|
T50 |
246 |
| auto[1] |
auto[1] |
auto[1] |
485196 |
1 |
|
|
T32 |
11153 |
|
T34 |
4 |
|
T50 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071281 |
1 |
|
|
T32 |
163419 |
|
T33 |
14861 |
|
T34 |
683 |
| auto[1] |
7663895 |
1 |
|
|
T32 |
158573 |
|
T34 |
504 |
|
T50 |
536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757284 |
1 |
|
|
T32 |
302173 |
|
T33 |
14861 |
|
T34 |
1177 |
| auto[1] |
977892 |
1 |
|
|
T32 |
19819 |
|
T34 |
10 |
|
T50 |
58 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10039174 |
1 |
|
|
T32 |
169786 |
|
T33 |
14861 |
|
T34 |
778 |
| auto[1] |
7696002 |
1 |
|
|
T32 |
152206 |
|
T34 |
409 |
|
T50 |
338 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3372062 |
1 |
|
|
T32 |
65789 |
|
T34 |
210 |
|
T50 |
106 |
| auto[1] |
auto[0] |
auto[1] |
490317 |
1 |
|
|
T32 |
9740 |
|
T34 |
7 |
|
T50 |
22 |
| auto[1] |
auto[1] |
auto[0] |
3346048 |
1 |
|
|
T32 |
66598 |
|
T34 |
189 |
|
T50 |
174 |
| auto[1] |
auto[1] |
auto[1] |
487575 |
1 |
|
|
T32 |
10079 |
|
T34 |
3 |
|
T50 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |