Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9999553 |
1 |
|
|
T32 |
166179 |
|
T33 |
14861 |
|
T34 |
685 |
| auto[1] |
7735623 |
1 |
|
|
T32 |
155813 |
|
T34 |
502 |
|
T50 |
627 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14610055 |
1 |
|
|
T32 |
259870 |
|
T33 |
14861 |
|
T34 |
745 |
| auto[1] |
3125121 |
1 |
|
|
T32 |
62122 |
|
T34 |
442 |
|
T50 |
218 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011604 |
1 |
|
|
T32 |
158699 |
|
T33 |
14861 |
|
T34 |
650 |
| auto[1] |
7723572 |
1 |
|
|
T32 |
163293 |
|
T34 |
537 |
|
T50 |
521 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2287613 |
1 |
|
|
T32 |
52912 |
|
T34 |
39 |
|
T50 |
135 |
| auto[1] |
auto[0] |
auto[1] |
1557977 |
1 |
|
|
T32 |
31508 |
|
T34 |
222 |
|
T50 |
119 |
| auto[1] |
auto[1] |
auto[0] |
2310838 |
1 |
|
|
T32 |
48259 |
|
T34 |
56 |
|
T50 |
168 |
| auto[1] |
auto[1] |
auto[1] |
1567144 |
1 |
|
|
T32 |
30614 |
|
T34 |
220 |
|
T50 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |